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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [USBSlaveControlBI_simlib.v] - Blame information for rev 408

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// USBSlaveControlBI.v                                          ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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////       
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
`include "usbSlaveControl_h.v"
46
 
47
module USBSlaveControlBI_simlib (address, dataIn, dataOut, writeEn,
48
  strobe_i,
49
  busClk,
50
  rstSyncToBusClk,
51
  usbClk,
52
  rstSyncToUsbClk,
53
  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut, vBusDetIntOut,
54
  endP0TransTypeReg, endP0NAKTransTypeReg,
55
  endP1TransTypeReg, endP1NAKTransTypeReg,
56
  endP2TransTypeReg, endP2NAKTransTypeReg,
57
  endP3TransTypeReg, endP3NAKTransTypeReg,
58
  endP0ControlReg,
59
  endP1ControlReg,
60
  endP2ControlReg,
61
  endP3ControlReg,
62
  EP0StatusReg,
63
  EP1StatusReg,
64
  EP2StatusReg,
65
  EP3StatusReg,
66
  SCAddrReg, frameNum,
67
  connectStateIn,
68
  vBusDetectIn,
69
  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
70
  slaveControlSelect,
71
  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
72
  TxLineState,
73
  LineDirectControlEn,
74
  fullSpeedPol,
75
  fullSpeedRate,
76
  connectSlaveToHost,
77
  SCGlobalEn
78
  );
79
input [4:0] address;
80
input [7:0] dataIn;
81
input writeEn;
82
input strobe_i;
83
input busClk;
84
input rstSyncToBusClk;
85
input usbClk;
86
input rstSyncToUsbClk;
87
output [7:0] dataOut;
88
output SOFRxedIntOut;
89
output resetEventIntOut;
90
output resumeIntOut;
91
output transDoneIntOut;
92
output NAKSentIntOut;
93
output vBusDetIntOut;
94
 
95
input [1:0] endP0TransTypeReg;
96
input [1:0] endP0NAKTransTypeReg;
97
input [1:0] endP1TransTypeReg;
98
input [1:0] endP1NAKTransTypeReg;
99
input [1:0] endP2TransTypeReg;
100
input [1:0] endP2NAKTransTypeReg;
101
input [1:0] endP3TransTypeReg;
102
input [1:0] endP3NAKTransTypeReg;
103
output [4:0] endP0ControlReg;
104
output [4:0] endP1ControlReg;
105
output [4:0] endP2ControlReg;
106
output [4:0] endP3ControlReg;
107
input [7:0] EP0StatusReg;
108
input [7:0] EP1StatusReg;
109
input [7:0] EP2StatusReg;
110
input [7:0] EP3StatusReg;
111
output [6:0] SCAddrReg;
112
input [10:0] frameNum;
113
input [1:0] connectStateIn;
114
input vBusDetectIn;
115
input SOFRxedIn;
116
input resetEventIn;
117
input resumeIntIn;
118
input transDoneIn;
119
input NAKSentIn;
120
input slaveControlSelect;
121
input clrEP0Ready;
122
input clrEP1Ready;
123
input clrEP2Ready;
124
input clrEP3Ready;
125
output [1:0] TxLineState;
126
output LineDirectControlEn;
127
output fullSpeedPol;
128
output fullSpeedRate;
129
output connectSlaveToHost;
130
output SCGlobalEn;
131
 
132
wire [4:0] address;
133
wire [7:0] dataIn;
134
wire writeEn;
135
wire strobe_i;
136
wire busClk;
137
wire rstSyncToBusClk;
138
wire usbClk;
139
wire rstSyncToUsbClk;
140
reg [7:0] dataOut;
141
 
142
reg SOFRxedIntOut;
143
reg resetEventIntOut;
144
reg resumeIntOut;
145
reg transDoneIntOut;
146
reg NAKSentIntOut;
147
reg vBusDetIntOut;
148
 
149
wire [1:0] endP0TransTypeReg;
150
wire [1:0] endP0NAKTransTypeReg;
151
wire [1:0] endP1TransTypeReg;
152
wire [1:0] endP1NAKTransTypeReg;
153
wire [1:0] endP2TransTypeReg;
154
wire [1:0] endP2NAKTransTypeReg;
155
wire [1:0] endP3TransTypeReg;
156
wire [1:0] endP3NAKTransTypeReg;
157
reg [4:0] endP0ControlReg;
158
reg [4:0] endP0ControlReg1;
159
reg [4:0] endP1ControlReg;
160
reg [4:0] endP1ControlReg1;
161
reg [4:0] endP2ControlReg;
162
reg [4:0] endP2ControlReg1;
163
reg [4:0] endP3ControlReg;
164
reg [4:0] endP3ControlReg1;
165
wire [7:0] EP0StatusReg;
166
wire [7:0] EP1StatusReg;
167
wire [7:0] EP2StatusReg;
168
wire [7:0] EP3StatusReg;
169
reg [6:0] SCAddrReg;
170
reg [3:0] TxEndPReg;
171
wire [10:0] frameNum;
172
wire [1:0] connectStateIn;
173
 
174
wire SOFRxedIn;
175
wire resetEventIn;
176
wire resumeIntIn;
177
wire transDoneIn;
178
wire NAKSentIn;
179
wire slaveControlSelect;
180
wire clrEP0Ready;
181
wire clrEP1Ready;
182
wire clrEP2Ready;
183
wire clrEP3Ready;
184
reg [1:0] TxLineState;
185
reg [1:0] TxLineState_reg1;
186
reg LineDirectControlEn;
187
reg LineDirectControlEn_reg1;
188
reg fullSpeedPol;
189
reg fullSpeedPol_reg1;
190
reg fullSpeedRate;
191
reg fullSpeedRate_reg1;
192
reg connectSlaveToHost;
193
reg connectSlaveToHost_reg1;
194
reg SCGlobalEn;
195
reg SCGlobalEn_reg1;
196
 
197
//internal wire and regs
198
reg [6:0] SCControlReg;
199
reg clrVBusDetReq;
200
reg clrNAKReq;
201
reg clrSOFReq;
202
reg clrResetReq;
203
reg clrResInReq;
204
reg clrTransDoneReq;
205
reg SOFRxedInt;
206
reg resetEventInt;
207
reg resumeInt;
208
reg transDoneInt;
209
reg vBusDetInt;
210
reg NAKSentInt;
211
reg [5:0] interruptMaskReg;
212
reg EP0SetReady;
213
reg EP1SetReady;
214
reg EP2SetReady;
215
reg EP3SetReady;
216
reg EP0SendStall;
217
reg EP1SendStall;
218
reg EP2SendStall;
219
reg EP3SendStall;
220
reg EP0IsoEn;
221
reg EP1IsoEn;
222
reg EP2IsoEn;
223
reg EP3IsoEn;
224
reg EP0DataSequence;
225
reg EP1DataSequence;
226
reg EP2DataSequence;
227
reg EP3DataSequence;
228
reg EP0Enable;
229
reg EP1Enable;
230
reg EP2Enable;
231
reg EP3Enable;
232
reg EP0Ready;
233
reg EP1Ready;
234
reg EP2Ready;
235
reg EP3Ready;
236
reg [2:0] SOFRxedInExtend;
237
reg [2:0] resetEventInExtend;
238
reg [2:0] resumeIntInExtend;
239
reg [2:0] transDoneInExtend;
240
reg [2:0] NAKSentInExtend;
241
reg [2:0] clrEP0ReadyExtend;
242
reg [2:0] clrEP1ReadyExtend;
243
reg [2:0] clrEP2ReadyExtend;
244
reg [2:0] clrEP3ReadyExtend;
245
 
246
 
247
//clock domain crossing sync registers
248
//STB = Sync To Busclk
249
reg [4:0] endP0ControlRegSTB;
250
reg [4:0] endP1ControlRegSTB;
251
reg [4:0] endP2ControlRegSTB;
252
reg [4:0] endP3ControlRegSTB;
253
reg [2:0] NAKSentInSTB;
254
reg [2:0] SOFRxedInSTB;
255
reg [2:0] resetEventInSTB;
256
reg [2:0] resumeIntInSTB;
257
reg [2:0] transDoneInSTB;
258
reg [2:0] clrEP0ReadySTB;
259
reg [2:0] clrEP1ReadySTB;
260
reg [2:0] clrEP2ReadySTB;
261
reg [2:0] clrEP3ReadySTB;
262
reg SCGlobalEnSTB;
263
reg [1:0] TxLineStateSTB;
264
reg LineDirectControlEnSTB;
265
reg fullSpeedPolSTB;
266
reg fullSpeedRateSTB;
267
reg connectSlaveToHostSTB;
268
reg [7:0] EP0StatusRegSTB;
269
reg [7:0] EP0StatusRegSTB_reg1;
270
reg [7:0] EP1StatusRegSTB;
271
reg [7:0] EP1StatusRegSTB_reg1;
272
reg [7:0] EP2StatusRegSTB;
273
reg [7:0] EP2StatusRegSTB_reg1;
274
reg [7:0] EP3StatusRegSTB;
275
reg [7:0] EP3StatusRegSTB_reg1;
276
reg [1:0] endP0TransTypeRegSTB;
277
reg [1:0] endP0TransTypeRegSTB_reg1;
278
reg [1:0] endP0NAKTransTypeRegSTB;
279
reg [1:0] endP0NAKTransTypeRegSTB_reg1;
280
reg [1:0] endP1TransTypeRegSTB;
281
reg [1:0] endP1TransTypeRegSTB_reg1;
282
reg [1:0] endP1NAKTransTypeRegSTB;
283
reg [1:0] endP1NAKTransTypeRegSTB_reg1;
284
reg [1:0] endP2TransTypeRegSTB;
285
reg [1:0] endP2TransTypeRegSTB_reg1;
286
reg [1:0] endP2NAKTransTypeRegSTB;
287
reg [1:0] endP2NAKTransTypeRegSTB_reg1;
288
reg [1:0] endP3TransTypeRegSTB;
289
reg [1:0] endP3TransTypeRegSTB_reg1;
290
reg [1:0] endP3NAKTransTypeRegSTB;
291
reg [1:0] endP3NAKTransTypeRegSTB_reg1;
292
reg [10:0] frameNumSTB;
293
reg [10:0] frameNumSTB_reg1;
294
reg [2:0] vBusDetectInSTB;
295
reg [1:0] connectStateInSTB;
296
reg [1:0] connectStateInSTB_reg1;
297
 
298
 
299
//sync write demux
300
always @(posedge busClk)
301
begin
302
  if (rstSyncToBusClk == 1'b1) begin
303
    EP0IsoEn <= 1'b0;
304
    EP0SendStall <= 1'b0;
305
    EP0DataSequence <= 1'b0;
306
    EP0Enable <= 1'b0;
307
    EP1IsoEn <= 1'b0;
308
    EP1SendStall <= 1'b0;
309
    EP1DataSequence <= 1'b0;
310
    EP1Enable <= 1'b0;
311
    EP2IsoEn <= 1'b0;
312
    EP2SendStall <= 1'b0;
313
    EP2DataSequence <= 1'b0;
314
    EP2Enable <= 1'b0;
315
    EP3IsoEn <= 1'b0;
316
    EP3SendStall <= 1'b0;
317
    EP3DataSequence <= 1'b0;
318
    EP3Enable <= 1'b0;
319
    SCControlReg <= 7'h00;
320
    SCAddrReg <= 7'h00;
321
    interruptMaskReg <= 6'h00;
322
  end
323
  else begin
324
    clrVBusDetReq <= 1'b0;
325
    clrNAKReq <= 1'b0;
326
    clrSOFReq <= 1'b0;
327
    clrResetReq <= 1'b0;
328
    clrResInReq <= 1'b0;
329
    clrTransDoneReq <= 1'b0;
330
    EP0SetReady <= 1'b0;
331
    EP1SetReady <= 1'b0;
332
    EP2SetReady <= 1'b0;
333
    EP3SetReady <= 1'b0;
334
    if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
335
    begin
336
      case (address)
337
        `EP0_CTRL_REG : begin
338
          EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
339
          EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
340
          EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
341
          EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
342
          EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
343
        end
344
        `EP1_CTRL_REG : begin
345
          EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
346
          EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
347
          EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
348
          EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
349
          EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
350
        end
351
        `EP2_CTRL_REG : begin
352
          EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
353
          EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
354
          EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
355
          EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
356
          EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
357
        end
358
        `EP3_CTRL_REG : begin
359
          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
360
          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
361
          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
362
          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
363
          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
364
        end
365
        `SC_CONTROL_REG : SCControlReg <= dataIn[6:0];
366
        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
367
        `SC_INTERRUPT_STATUS_REG : begin
368
          clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT];
369
          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
370
          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
371
          clrResetReq <= dataIn[`RESET_EVENT_BIT];
372
          clrResInReq <= dataIn[`RESUME_INT_BIT];
373
          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
374
        end
375
        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[5:0];
376
      endcase
377
    end
378
  end
379
end
380
 
381
//interrupt control 
382
always @(posedge busClk)
383
begin
384
  if (rstSyncToBusClk == 1'b1) begin
385
    vBusDetInt <= 1'b0;
386
    NAKSentInt <= 1'b0;
387
    SOFRxedInt <= 1'b0;
388
    resetEventInt <= 1'b0;
389
    resumeInt <= 1'b0;
390
    transDoneInt <= 1'b0;
391
  end
392
  else begin
393
    if (vBusDetectInSTB[0] != vBusDetectInSTB[1])
394
      vBusDetInt <= 1'b1;
395
    else if (clrVBusDetReq == 1'b1)
396
      vBusDetInt <= 1'b0;
397
 
398
    if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0)
399
      NAKSentInt <= 1'b1;
400
    else if (clrNAKReq == 1'b1)
401
      NAKSentInt <= 1'b0;
402
 
403
    if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0)
404
      SOFRxedInt <= 1'b1;
405
    else if (clrSOFReq == 1'b1)
406
      SOFRxedInt <= 1'b0;
407
 
408
    if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0)
409
      resetEventInt <= 1'b1;
410
    else if (clrResetReq == 1'b1)
411
      resetEventInt <= 1'b0;
412
 
413
    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
414
      resumeInt <= 1'b1;
415
    else if (clrResInReq == 1'b1)
416
      resumeInt <= 1'b0;
417
 
418
    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
419
      transDoneInt <= 1'b1;
420
    else if (clrTransDoneReq == 1'b1)
421
      transDoneInt <= 1'b0;
422
  end
423
end
424
 
425
//mask interrupts
426
always @(*) begin
427
  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
428
  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
429
  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
430
  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
431
  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
432
  vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT];
433
end
434
 
435
//end point ready, set/clear
436
//Since 'busClk' can be a higher freq than 'usbClk',
437
//'EP0SetReady' etc must be delayed with respect to other control signals, thus
438
//ensuring that control signals have been clocked through to 'usbClk' clock
439
//domain before the ready is asserted.
440
//Not sure this is required because there is at least two 'usbClk' ticks between
441
//detection of 'EP0Ready' and sampling of related control signals.
442
always @(posedge busClk)
443
begin
444
  if (rstSyncToBusClk == 1'b1) begin
445
    EP0Ready <= 1'b0;
446
    EP1Ready <= 1'b0;
447
    EP2Ready <= 1'b0;
448
    EP3Ready <= 1'b0;
449
  end
450
  else begin
451
    if (EP0SetReady == 1'b1)
452
      EP0Ready <= 1'b1;
453
    else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0)
454
      EP0Ready <= 1'b0;
455
 
456
    if (EP1SetReady == 1'b1)
457
      EP1Ready <= 1'b1;
458
    else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0)
459
      EP1Ready <= 1'b0;
460
 
461
    if (EP2SetReady == 1'b1)
462
      EP2Ready <= 1'b1;
463
    else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0)
464
      EP2Ready <= 1'b0;
465
 
466
    if (EP3SetReady == 1'b1)
467
      EP3Ready <= 1'b1;
468
    else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0)
469
      EP3Ready <= 1'b0;
470
  end
471
end
472
 
473
//break out control signals
474
always @(SCControlReg) begin
475
  SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
476
  TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
477
  LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
478
  fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT];
479
  fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
480
  connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT];
481
end
482
 
483
//combine endpoint control signals 
484
always @(*)
485
begin
486
  endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
487
  endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
488
  endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
489
  endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
490
end
491
 
492
 
493
// async read mux
494
always @(*)
495
begin
496
  case (address)
497
      `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
498
      `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
499
      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
500
      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
501
      `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
502
      `EP1_STS_REG :  dataOut <= EP1StatusRegSTB;
503
      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
504
      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
505
      `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
506
      `EP2_STS_REG :  dataOut <= EP2StatusRegSTB;
507
      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
508
      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
509
      `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
510
      `EP3_STS_REG :  dataOut <= EP3StatusRegSTB;
511
      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
512
      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
513
      `SC_CONTROL_REG : dataOut <= SCControlReg;
514
      `SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB};
515
      `SC_INTERRUPT_STATUS_REG :  dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
516
      `SC_INTERRUPT_MASK_REG  : dataOut <= {2'b00, interruptMaskReg};
517
      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
518
      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
519
      `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
520
      default: dataOut <= 8'h00;
521
  endcase
522
end
523
 
524
 
525
//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick
526
//pulses to 3 tick pulses
527
always @(posedge usbClk) begin
528
  if (rstSyncToUsbClk == 1'b1) begin
529
    SOFRxedInExtend <= 3'b000;
530
    resetEventInExtend <= 3'b000;
531
    resumeIntInExtend <= 3'b000;
532
    transDoneInExtend <= 3'b000;
533
    NAKSentInExtend <= 3'b000;
534
    clrEP0ReadyExtend <= 3'b000;
535
    clrEP1ReadyExtend <= 3'b000;
536
    clrEP2ReadyExtend <= 3'b000;
537
    clrEP3ReadyExtend <= 3'b000;
538
  end
539
  else begin
540
    if (SOFRxedIn == 1'b1)
541
      SOFRxedInExtend <= 3'b111;
542
    else
543
      SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]};
544
    if (resetEventIn == 1'b1)
545
      resetEventInExtend <= 3'b111;
546
    else
547
      resetEventInExtend <= {1'b0, resetEventInExtend[2:1]};
548
    if (resumeIntIn == 1'b1)
549
      resumeIntInExtend <= 3'b111;
550
    else
551
      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
552
    if (transDoneIn == 1'b1)
553
      transDoneInExtend <= 3'b111;
554
    else
555
      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
556
    if (NAKSentIn == 1'b1)
557
      NAKSentInExtend <= 3'b111;
558
    else
559
      NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]};
560
    if (clrEP0Ready == 1'b1)
561
      clrEP0ReadyExtend <= 3'b111;
562
    else
563
      clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]};
564
    if (clrEP1Ready == 1'b1)
565
      clrEP1ReadyExtend <= 3'b111;
566
    else
567
      clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]};
568
    if (clrEP2Ready == 1'b1)
569
      clrEP2ReadyExtend <= 3'b111;
570
    else
571
      clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]};
572
    if (clrEP3Ready == 1'b1)
573
      clrEP3ReadyExtend <= 3'b111;
574
    else
575
      clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]};
576
  end
577
end
578
 
579
//re-sync from busClk to usbClk. 
580
always @(posedge usbClk) begin
581
  if (rstSyncToUsbClk == 1'b1) begin
582
    endP0ControlReg <= {5{1'b0}};
583
    endP0ControlReg1 <= {5{1'b0}};
584
    endP1ControlReg <= {5{1'b0}};
585
    endP1ControlReg1 <= {5{1'b0}};
586
    endP2ControlReg <= {5{1'b0}};
587
    endP2ControlReg1 <= {5{1'b0}};
588
    endP3ControlReg <= {5{1'b0}};
589
    endP3ControlReg1 <= {5{1'b0}};
590
    SCGlobalEn <= 1'b0;
591
    SCGlobalEn_reg1 <= 1'b0;
592
    TxLineState <= 2'b00;
593
    TxLineState_reg1 <= 2'b00;
594
    LineDirectControlEn <= 1'b0;
595
    LineDirectControlEn_reg1 <= 1'b0;
596
    fullSpeedPol <= 1'b0;
597
    fullSpeedPol_reg1 <= 1'b0;
598
    fullSpeedRate <= 1'b0;
599
    fullSpeedRate_reg1 <= 1'b0;
600
    connectSlaveToHost <= 1'b0;
601
    connectSlaveToHost_reg1 <= 1'b0;
602
  end
603
  else begin
604
    endP0ControlReg1 <= endP0ControlRegSTB;
605
    endP0ControlReg <= endP0ControlReg1;
606
    endP1ControlReg1 <= endP1ControlRegSTB;
607
    endP1ControlReg <= endP1ControlReg1;
608
    endP2ControlReg1 <= endP2ControlRegSTB;
609
    endP2ControlReg <= endP2ControlReg1;
610
    endP3ControlReg1 <= endP3ControlRegSTB;
611
    endP3ControlReg <= endP3ControlReg1;
612
    SCGlobalEn_reg1 <= SCGlobalEnSTB;
613
    SCGlobalEn <= SCGlobalEn_reg1;
614
    TxLineState_reg1 <= TxLineStateSTB;
615
    TxLineState <= TxLineState_reg1;
616
    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
617
    LineDirectControlEn <= LineDirectControlEn_reg1;
618
    fullSpeedPol_reg1 <= fullSpeedPolSTB;
619
    fullSpeedPol <= fullSpeedPol_reg1;
620
    fullSpeedRate_reg1 <= fullSpeedRateSTB;
621
    fullSpeedRate <= fullSpeedRate_reg1;
622
    connectSlaveToHost_reg1 <= connectSlaveToHostSTB;
623
    connectSlaveToHost <= connectSlaveToHost_reg1;
624
  end
625
end
626
 
627
//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc 
628
//are only asserted for 3 usbClk ticks
629
//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq
630
always @(posedge busClk) begin
631
  if (rstSyncToBusClk == 1'b1) begin
632
    vBusDetectInSTB <= 3'b000;
633
    NAKSentInSTB <= 3'b000;
634
    SOFRxedInSTB <= 3'b000;
635
    resetEventInSTB <= 3'b000;
636
    resumeIntInSTB <= 3'b000;
637
    transDoneInSTB <= 3'b000;
638
    clrEP0ReadySTB <= 3'b000;
639
    clrEP1ReadySTB <= 3'b000;
640
    clrEP2ReadySTB <= 3'b000;
641
    clrEP3ReadySTB <= 3'b000;
642
    EP0StatusRegSTB <= 8'h00;
643
    EP0StatusRegSTB_reg1 <= 8'h00;
644
    EP1StatusRegSTB <= 8'h00;
645
    EP1StatusRegSTB_reg1 <= 8'h00;
646
    EP2StatusRegSTB <= 8'h00;
647
    EP2StatusRegSTB_reg1 <= 8'h00;
648
    EP3StatusRegSTB <= 8'h00;
649
    EP3StatusRegSTB_reg1 <= 8'h00;
650
    endP0TransTypeRegSTB <= 2'b00;
651
    endP0TransTypeRegSTB_reg1 <= 2'b00;
652
    endP1TransTypeRegSTB <= 2'b00;
653
    endP1TransTypeRegSTB_reg1 <= 2'b00;
654
    endP2TransTypeRegSTB <= 2'b00;
655
    endP2TransTypeRegSTB_reg1 <= 2'b00;
656
    endP3TransTypeRegSTB <= 2'b00;
657
    endP3TransTypeRegSTB_reg1 <= 2'b00;
658
    endP0NAKTransTypeRegSTB <= 2'b00;
659
    endP0NAKTransTypeRegSTB_reg1 <= 2'b00;
660
    endP1NAKTransTypeRegSTB <= 2'b00;
661
    endP1NAKTransTypeRegSTB_reg1 <= 2'b00;
662
    endP2NAKTransTypeRegSTB <= 2'b00;
663
    endP2NAKTransTypeRegSTB_reg1 <= 2'b00;
664
    endP3NAKTransTypeRegSTB <= 2'b00;
665
    endP3NAKTransTypeRegSTB_reg1 <= 2'b00;
666
    frameNumSTB <= {11{1'b0}};
667
    frameNumSTB_reg1 <= {11{1'b0}};
668
    connectStateInSTB <= 2'b00;
669
    connectStateInSTB_reg1 <= 2'b00;
670
  end
671
  else begin
672
    vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]};
673
    NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]};
674
    SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]};
675
    resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]};
676
    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
677
    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
678
    clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]};
679
    clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]};
680
    clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]};
681
    clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]};
682
    EP0StatusRegSTB_reg1 <= EP0StatusReg;
683
    EP0StatusRegSTB <= EP0StatusRegSTB_reg1;
684
    EP1StatusRegSTB_reg1 <= EP1StatusReg;
685
    EP1StatusRegSTB <= EP1StatusRegSTB_reg1;
686
    EP2StatusRegSTB_reg1 <= EP2StatusReg;
687
    EP2StatusRegSTB <= EP2StatusRegSTB_reg1;
688
    EP3StatusRegSTB_reg1 <= EP3StatusReg;
689
    EP3StatusRegSTB <= EP3StatusRegSTB_reg1;
690
    endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg;
691
    endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1;
692
    endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg;
693
    endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1;
694
    endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg;
695
    endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1;
696
    endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg;
697
    endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1;
698
    endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg;
699
    endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1;
700
    endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg;
701
    endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1;
702
    endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg;
703
    endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1;
704
    endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg;
705
    endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1;
706
    frameNumSTB_reg1 <= frameNum;
707
    frameNumSTB <= frameNumSTB_reg1;
708
    connectStateInSTB_reg1 <= connectStateIn;
709
    connectStateInSTB <= connectStateInSTB_reg1;
710
  end
711
end
712
 
713
 
714
endmodule

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