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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [USBTxWireArbiter_simlib.v] - Blame information for rev 408

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1 408 julius
 
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// File        : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v
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// Generated   : 11/10/06 05:37:24
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// From        : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// usbTxWireArbiter
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbConstants_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module USBTxWireArbiter_simlib (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
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input   SIETxCtrl;
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input   [1:0] SIETxData;
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input   SIETxFSRate;
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input   SIETxReq;
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input   SIETxWEn;
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input   USBWireRdyIn;
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input   clk;
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input   prcTxByteCtrl;
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input   [1:0] prcTxByteData;
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input   prcTxByteFSRate;
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input   prcTxByteReq;
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input   prcTxByteWEn;
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input   rst;
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output  SIETxGnt;
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output  [1:0] TxBits;
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output  TxCtl;
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output  TxFSRate;
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output  USBWireRdyOut;
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output  USBWireWEn;
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output  prcTxByteGnt;
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wire    SIETxCtrl;
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wire    [1:0] SIETxData;
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wire    SIETxFSRate;
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reg     SIETxGnt, next_SIETxGnt;
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wire    SIETxReq;
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wire    SIETxWEn;
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reg     [1:0] TxBits, next_TxBits;
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reg     TxCtl, next_TxCtl;
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reg     TxFSRate, next_TxFSRate;
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wire    USBWireRdyIn;
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reg     USBWireRdyOut, next_USBWireRdyOut;
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reg     USBWireWEn, next_USBWireWEn;
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wire    clk;
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wire    prcTxByteCtrl;
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wire    [1:0] prcTxByteData;
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wire    prcTxByteFSRate;
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reg     prcTxByteGnt, next_prcTxByteGnt;
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wire    prcTxByteReq;
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wire    prcTxByteWEn;
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wire    rst;
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// diagram signals declarations
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reg  muxSIENotPTXB, next_muxSIENotPTXB;
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// BINARY ENCODED state machine: txWireArb
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// State codes definitions:
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`define START_TARB 2'b00
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`define TARB_WAIT_REQ 2'b01
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`define PTXB_ACT 2'b10
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`define SIE_TX_ACT 2'b11
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reg [1:0] CurrState_txWireArb;
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reg [1:0] NextState_txWireArb;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// processTxByte/SIETransmitter mux
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always @(USBWireRdyIn)
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begin
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    USBWireRdyOut <= USBWireRdyIn;
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end
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always @(muxSIENotPTXB or SIETxWEn or SIETxData or
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SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
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SIETxFSRate or prcTxByteFSRate)
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begin
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    if (muxSIENotPTXB  == 1'b1)
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    begin
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        USBWireWEn <= SIETxWEn;
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        TxBits <= SIETxData;
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        TxCtl <= SIETxCtrl;
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        TxFSRate <= SIETxFSRate;
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    end
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    else
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    begin
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        USBWireWEn <= prcTxByteWEn;
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        TxBits <= prcTxByteData;
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        TxCtl <= prcTxByteCtrl;
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        TxFSRate <= prcTxByteFSRate;
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    end
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end
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//--------------------------------------------------------------------
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// Machine: txWireArb
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
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begin : txWireArb_NextState
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  NextState_txWireArb <= CurrState_txWireArb;
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  // Set default values for outputs and signals
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  next_prcTxByteGnt <= prcTxByteGnt;
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  next_muxSIENotPTXB <= muxSIENotPTXB;
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  next_SIETxGnt <= SIETxGnt;
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  case (CurrState_txWireArb)
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    `START_TARB:
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      NextState_txWireArb <= `TARB_WAIT_REQ;
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    `TARB_WAIT_REQ:
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      if (prcTxByteReq == 1'b1)
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      begin
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        NextState_txWireArb <= `PTXB_ACT;
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        next_prcTxByteGnt <= 1'b1;
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        next_muxSIENotPTXB <= 1'b0;
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      end
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      else if (SIETxReq == 1'b1)
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      begin
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        NextState_txWireArb <= `SIE_TX_ACT;
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        next_SIETxGnt <= 1'b1;
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        next_muxSIENotPTXB <= 1'b1;
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      end
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    `PTXB_ACT:
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      if (prcTxByteReq == 1'b0)
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      begin
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        NextState_txWireArb <= `TARB_WAIT_REQ;
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        next_prcTxByteGnt <= 1'b0;
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      end
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    `SIE_TX_ACT:
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      if (SIETxReq == 1'b0)
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      begin
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        NextState_txWireArb <= `TARB_WAIT_REQ;
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        next_SIETxGnt <= 1'b0;
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      end
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : txWireArb_CurrentState
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  if (rst)
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    CurrState_txWireArb <= `START_TARB;
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  else
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    CurrState_txWireArb <= NextState_txWireArb;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : txWireArb_RegOutput
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  if (rst)
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  begin
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    muxSIENotPTXB <= 1'b0;
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    prcTxByteGnt <= 1'b0;
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    SIETxGnt <= 1'b0;
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  end
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  else
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  begin
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    muxSIENotPTXB <= next_muxSIENotPTXB;
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    prcTxByteGnt <= next_prcTxByteGnt;
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    SIETxGnt <= next_SIETxGnt;
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  end
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end
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endmodule

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