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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [processRxBit_simlib.v] - Blame information for rev 408

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1 408 julius
 
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// File        : ../RTL/serialInterfaceEngine/processRxBit.v
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// Generated   : 11/10/06 05:37:22
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// From        : ../RTL/serialInterfaceEngine/processRxBit.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// processrxbit
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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module processRxBit_simlib (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
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input   [1:0] JBit;
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input   [1:0] KBit;
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input   [1:0] RxBitsIn;
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input   RxWireActive;
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input   clk;
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input   processRxBitsWEn;
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input   processRxByteRdy;
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input   rst;
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output  [7:0] RxCtrlOut;
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output  [7:0] RxDataOut;
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output  processRxBitRdy;
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output  processRxByteWEn;
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output  resumeDetected;
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wire    [1:0] JBit;
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wire    [1:0] KBit;
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wire    [1:0] RxBitsIn;
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reg     [7:0] RxCtrlOut, next_RxCtrlOut;
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reg     [7:0] RxDataOut, next_RxDataOut;
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wire    RxWireActive;
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wire    clk;
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reg     processRxBitRdy, next_processRxBitRdy;
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wire    processRxBitsWEn;
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wire    processRxByteRdy;
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reg     processRxByteWEn, next_processRxByteWEn;
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reg     resumeDetected, next_resumeDetected;
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wire    rst;
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// diagram signals declarations
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reg  [3:0]RXBitCount, next_RXBitCount;
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reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
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reg  [7:0]RXByte, next_RXByte;
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reg  [3:0]RXSameBitCount, next_RXSameBitCount;
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reg  [1:0]RxBits, next_RxBits;
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reg  bitStuffError, next_bitStuffError;
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reg  [1:0]oldRXBits, next_oldRXBits;
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reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
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// BINARY ENCODED state machine: prRxBit
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// State codes definitions:
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`define START 4'b0000
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`define IDLE_FIRST_BIT 4'b0001
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`define WAIT_BITS 4'b0010
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`define IDLE_CHK_KBIT 4'b0011
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`define DATA_RX_LAST_BIT 4'b0100
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`define DATA_RX_CHK_SE0 4'b0101
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`define DATA_RX_DATA_DESTUFF 4'b0110
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`define DATA_RX_BYTE_SEND2 4'b0111
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`define DATA_RX_BYTE_WAIT_RDY 4'b1000
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`define RES_RX_CHK 4'b1001
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`define DATA_RX_ERROR_CHK_RES 4'b1010
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`define RES_END_CHK1 4'b1011
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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reg [3:0] CurrState_prRxBit;
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reg [3:0] NextState_prRxBit;
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//--------------------------------------------------------------------
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// Machine: prRxBit
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
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begin : prRxBit_NextState
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  NextState_prRxBit <= CurrState_prRxBit;
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  // Set default values for outputs and signals
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  next_processRxByteWEn <= processRxByteWEn;
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  next_RxCtrlOut <= RxCtrlOut;
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  next_RxDataOut <= RxDataOut;
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  next_resumeDetected <= resumeDetected;
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  next_RXBitStMachCurrState <= RXBitStMachCurrState;
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  next_RxBits <= RxBits;
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  next_RXSameBitCount <= RXSameBitCount;
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  next_RXBitCount <= RXBitCount;
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  next_oldRXBits <= oldRXBits;
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  next_RXByte <= RXByte;
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  next_bitStuffError <= bitStuffError;
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  next_resumeWaitCnt <= resumeWaitCnt;
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  next_processRxBitRdy <= processRxBitRdy;
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  case (CurrState_prRxBit)
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    `START:
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    begin
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      next_processRxByteWEn <= 1'b0;
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      next_RxCtrlOut <= 8'h00;
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      next_RxDataOut <= 8'h00;
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      next_resumeDetected <= 1'b0;
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      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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      next_RxBits <= 2'b00;
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      next_RXSameBitCount <= 4'h0;
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      next_RXBitCount <= 4'h0;
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      next_oldRXBits <= 2'b00;
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      next_RXByte <= 8'h00;
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      next_bitStuffError <= 1'b0;
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      next_resumeWaitCnt <= 5'h0;
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      next_processRxBitRdy <= 1'b1;
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      NextState_prRxBit <= `WAIT_BITS;
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    end
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    `WAIT_BITS:
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      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
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      begin
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        NextState_prRxBit <= `RES_RX_CHK;
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        next_RxBits <= RxBitsIn;
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        next_processRxBitRdy <= 1'b0;
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      end
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      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
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      begin
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        NextState_prRxBit <= `DATA_RX_CHK_SE0;
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        next_RxBits <= RxBitsIn;
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        next_processRxBitRdy <= 1'b0;
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      end
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      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
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      begin
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        NextState_prRxBit <= `IDLE_CHK_KBIT;
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        next_RxBits <= RxBitsIn;
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        next_processRxBitRdy <= 1'b0;
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      end
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      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
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      begin
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        NextState_prRxBit <= `RES_END_CHK1;
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        next_RxBits <= RxBitsIn;
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        next_processRxBitRdy <= 1'b0;
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      end
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    `IDLE_FIRST_BIT:
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    begin
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      next_processRxByteWEn <= 1'b0;
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      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
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      next_RXSameBitCount <= 4'h0;
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      next_RXBitCount <= 4'h1;
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      next_oldRXBits <= RxBits;
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      //zero is always the first RZ data bit of a new packet
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      next_RXByte <= 8'h00;
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      NextState_prRxBit <= `WAIT_BITS;
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      next_processRxBitRdy <= 1'b1;
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    end
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    `IDLE_CHK_KBIT:
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      if ((RxBits == KBit) && (RxWireActive == 1'b1))
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        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
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      else
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      begin
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        NextState_prRxBit <= `WAIT_BITS;
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        next_processRxBitRdy <= 1'b1;
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      end
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    `IDLE_WAIT_PRB_RDY:
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      if (processRxByteRdy == 1'b1)
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      begin
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        NextState_prRxBit <= `IDLE_FIRST_BIT;
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        next_RxDataOut <= 8'h00;
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        //redundant data
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        next_RxCtrlOut <= `DATA_START;
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        //start of packet
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        next_processRxByteWEn <= 1'b1;
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      end
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    `DATA_RX_LAST_BIT:
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    begin
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      next_processRxByteWEn <= 1'b0;
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      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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      NextState_prRxBit <= `WAIT_BITS;
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      next_processRxBitRdy <= 1'b1;
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    end
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    `DATA_RX_CHK_SE0:
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    begin
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      next_bitStuffError <= 1'b0;
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      if (RxBits == `SE0)
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        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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      else
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      begin
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        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
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        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
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        begin
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          next_RXSameBitCount <= RXSameBitCount + 1'b1;
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            //inc 'RXSameBitCount'
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            if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
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            next_bitStuffError <= 1'b1;
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                //flag 'bitStuffError'
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            else                                          //else no bit stuffing error
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            begin
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            next_RXBitCount <= RXBitCount + 1'b1;
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                if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
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              next_processRxBitRdy <= 1'b1;
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                    //early indication of ready
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                        end
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            next_RXByte <= { 1'b1, RXByte[7:1]};
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                //RZ bit = 1 (ie no change in 'RxBits')
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            end
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        end
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        else                                            //else current 'RxBits' are different from old 'RxBits'
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        begin
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            if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
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            begin
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            next_RXBitCount <= RXBitCount + 1'b1;
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                if (RXBitCount != 4'h7) begin
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              next_processRxBitRdy <= 1'b1;
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                    //early indication of ready
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                        end
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            next_RXByte <= {1'b0, RXByte[7:1]};
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                //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
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            end
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           next_RXSameBitCount <= 4'h0;
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              //reset 'RXSameBitCount'
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        end
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        next_oldRXBits <= RxBits;
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      end
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    end
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    `DATA_RX_WAIT_PRB_RDY:
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      if (processRxByteRdy == 1'b1)
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      begin
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        NextState_prRxBit <= `DATA_RX_LAST_BIT;
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        next_RxDataOut <= 8'h00;
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        //redundant data
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        next_RxCtrlOut <= `DATA_STOP;
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        //end of packet
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        next_processRxByteWEn <= 1'b1;
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      end
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    `DATA_RX_DATA_DESTUFF:
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      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
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        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
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      else if (bitStuffError == 1'b1)
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        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
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      else
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      begin
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        NextState_prRxBit <= `WAIT_BITS;
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        next_processRxBitRdy <= 1'b1;
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      end
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    `DATA_RX_BYTE_SEND2:
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    begin
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      next_processRxByteWEn <= 1'b0;
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      NextState_prRxBit <= `WAIT_BITS;
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      next_processRxBitRdy <= 1'b1;
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    end
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    `DATA_RX_BYTE_WAIT_RDY:
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      if (processRxByteRdy == 1'b1)
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      begin
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        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
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        next_RXBitCount <= 4'h0;
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        next_RxDataOut <= RXByte;
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        next_RxCtrlOut <= `DATA_STREAM;
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        next_processRxByteWEn <= 1'b1;
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      end
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    `DATA_RX_ERROR_CHK_RES:
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    begin
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      next_processRxByteWEn <= 1'b0;
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      if (RxBits == JBit)                           //if current bit is a JBit, then
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        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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          //next state is idle
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      else                                          //else
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      begin
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        next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
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          //check for resume
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        next_resumeWaitCnt <= 5'h0;
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      end
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      NextState_prRxBit <= `WAIT_BITS;
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      next_processRxBitRdy <= 1'b1;
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    end
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    `DATA_RX_ERROR_WAIT_RDY:
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      if (processRxByteRdy == 1'b1)
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      begin
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        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
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        next_RxDataOut <= 8'h00;
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        //redundant data
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        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
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        next_processRxByteWEn <= 1'b1;
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      end
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    `RES_RX_CHK:
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    begin
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      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
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        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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      else
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      begin
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        next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
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          //if we've waited long enough, then
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          if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
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          begin
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          next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
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          next_resumeDetected <= 1'b1;
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              //report resume detected
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          end
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      end
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      NextState_prRxBit <= `WAIT_BITS;
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      next_processRxBitRdy <= 1'b1;
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    end
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    `RES_END_CHK1:
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    begin
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      if (RxBits != KBit)  //line must leave KBit state for the end of resume
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      begin
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        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
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        next_resumeDetected <= 1'b0;
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          //clear resume detected flag
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      end
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      NextState_prRxBit <= `WAIT_BITS;
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      next_processRxBitRdy <= 1'b1;
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    end
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : prRxBit_CurrentState
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  if (rst)
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    CurrState_prRxBit <= `START;
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  else
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    CurrState_prRxBit <= NextState_prRxBit;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
368
begin : prRxBit_RegOutput
369
  if (rst)
370
  begin
371
    RXBitStMachCurrState <= `IDLE_BIT_ST;
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    RxBits <= 2'b00;
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    RXSameBitCount <= 4'h0;
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    RXBitCount <= 4'h0;
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    oldRXBits <= 2'b00;
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    RXByte <= 8'h00;
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    bitStuffError <= 1'b0;
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    resumeWaitCnt <= 5'h0;
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    processRxByteWEn <= 1'b0;
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    RxCtrlOut <= 8'h00;
381
    RxDataOut <= 8'h00;
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    resumeDetected <= 1'b0;
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    processRxBitRdy <= 1'b1;
384
  end
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  else
386
  begin
387
    RXBitStMachCurrState <= next_RXBitStMachCurrState;
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    RxBits <= next_RxBits;
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    RXSameBitCount <= next_RXSameBitCount;
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    RXBitCount <= next_RXBitCount;
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    oldRXBits <= next_oldRXBits;
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    RXByte <= next_RXByte;
393
    bitStuffError <= next_bitStuffError;
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    resumeWaitCnt <= next_resumeWaitCnt;
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    processRxByteWEn <= next_processRxByteWEn;
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    RxCtrlOut <= next_RxCtrlOut;
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    RxDataOut <= next_RxDataOut;
398
    resumeDetected <= next_resumeDetected;
399
    processRxBitRdy <= next_processRxBitRdy;
400
  end
401
end
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endmodule

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