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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [sendPacket_simlib.v] - Blame information for rev 408

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// File        : ../RTL/hostController/sendpacket.v
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// Generated   : 11/10/06 05:37:20
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// From        : ../RTL/hostController/sendpacket.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// sendPacket
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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module sendPacket_simlib (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, rst, sendPacketRdy, sendPacketWEn);
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input   HCTxPortGnt;
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input   HCTxPortRdy;
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input   [3:0] PID;
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input   [6:0] TxAddr;
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input   [3:0] TxEndP;
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input   clk;
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input   [7:0] fifoData;
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input   fifoEmpty;
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input   fullSpeedPolarity;
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input   rst;
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input   sendPacketWEn;
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output  [7:0] HCTxPortCntl;
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output  [7:0] HCTxPortData;
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output  HCTxPortReq;
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output  HCTxPortWEn;
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output  fifoReadEn;
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output  [10:0] frameNum;
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output  sendPacketRdy;
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reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
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reg     [7:0] HCTxPortData, next_HCTxPortData;
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wire    HCTxPortGnt;
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wire    HCTxPortRdy;
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reg     HCTxPortReq, next_HCTxPortReq;
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reg     HCTxPortWEn, next_HCTxPortWEn;
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wire    [3:0] PID;
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wire    [6:0] TxAddr;
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wire    [3:0] TxEndP;
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wire    clk;
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wire    [7:0] fifoData;
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wire    fifoEmpty;
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reg     fifoReadEn, next_fifoReadEn;
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reg     [10:0] frameNum, next_frameNum;
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wire    fullSpeedPolarity;
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wire    rst;
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reg     sendPacketRdy, next_sendPacketRdy;
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wire    sendPacketWEn;
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// diagram signals declarations
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reg  [7:0]PIDNotPID;
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// BINARY ENCODED state machine: sndPkt
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// State codes definitions:
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`define START_SP 5'b00000
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`define WAIT_ENABLE 5'b00001
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`define SP_WAIT_GNT 5'b00010
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`define SEND_PID_WAIT_RDY 5'b00011
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`define SEND_PID_FIN 5'b00100
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`define FIN_SP 5'b00101
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`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
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`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
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`define OUT_IN_SETUP_FIN 5'b01000
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`define SEND_SOF_FIN1 5'b01001
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`define SEND_SOF_WAIT_RDY3 5'b01010
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`define SEND_SOF_WAIT_RDY4 5'b01011
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`define DATA0_DATA1_READ_FIFO 5'b01100
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`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
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`define DATA0_DATA1_FIFO_EMPTY 5'b01110
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`define DATA0_DATA1_FIN 5'b01111
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`define DATA0_DATA1_TERM_BYTE 5'b10000
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`define OUT_IN_SETUP_CLR_WEN1 5'b10001
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`define SEND_SOF_CLR_WEN1 5'b10010
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`define DATA0_DATA1_CLR_WEN 5'b10011
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`define DATA0_DATA1_CLR_REN 5'b10100
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`define LS_EOP_WAIT_RDY 5'b10101
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`define LS_EOP_FIN 5'b10110
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reg [4:0] CurrState_sndPkt;
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reg [4:0] NextState_sndPkt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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always @(PID)
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begin
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    PIDNotPID <=  { (PID ^ 4'hf), PID };
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end
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//--------------------------------------------------------------------
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// Machine: sndPkt
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or PID or fullSpeedPolarity or HCTxPortRdy or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
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begin : sndPkt_NextState
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  NextState_sndPkt <= CurrState_sndPkt;
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  // Set default values for outputs and signals
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  next_sendPacketRdy <= sendPacketRdy;
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  next_HCTxPortReq <= HCTxPortReq;
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  next_HCTxPortWEn <= HCTxPortWEn;
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  next_HCTxPortData <= HCTxPortData;
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  next_HCTxPortCntl <= HCTxPortCntl;
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  next_frameNum <= frameNum;
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  next_fifoReadEn <= fifoReadEn;
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  case (CurrState_sndPkt)
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    `START_SP:
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      NextState_sndPkt <= `WAIT_ENABLE;
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    `WAIT_ENABLE:
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      if (sendPacketWEn == 1'b1)
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      begin
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        NextState_sndPkt <= `SP_WAIT_GNT;
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        next_sendPacketRdy <= 1'b0;
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        next_HCTxPortReq <= 1'b1;
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      end
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    `SP_WAIT_GNT:
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      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
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        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
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      else if (HCTxPortGnt == 1'b1)
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        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
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    `FIN_SP:
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    begin
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      NextState_sndPkt <= `WAIT_ENABLE;
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      next_sendPacketRdy <= 1'b1;
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      next_HCTxPortReq <= 1'b0;
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    end
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    `SEND_PID_WAIT_RDY:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `SEND_PID_FIN;
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= PIDNotPID;
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        next_HCTxPortCntl <= `TX_PACKET_START;
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      end
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    `SEND_PID_FIN:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      if (PID == `DATA0 || PID == `DATA1)
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        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
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      else if (PID == `SOF)
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        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
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      else if (PID == `OUT ||
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        PID == `IN ||
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        PID == `SETUP)
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        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
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      else
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        NextState_sndPkt <= `FIN_SP;
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    end
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    `OUT_IN_SETUP_WAIT_RDY1:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
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        next_HCTxPortCntl <= `TX_PACKET_STREAM;
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      end
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    `OUT_IN_SETUP_WAIT_RDY2:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
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        next_HCTxPortCntl <= `TX_PACKET_STREAM;
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      end
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    `OUT_IN_SETUP_FIN:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      NextState_sndPkt <= `FIN_SP;
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    end
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    `OUT_IN_SETUP_CLR_WEN1:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
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    end
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    `SEND_SOF_FIN1:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      next_frameNum <= frameNum + 1'b1;
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      NextState_sndPkt <= `FIN_SP;
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    end
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    `SEND_SOF_WAIT_RDY3:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= frameNum[7:0];
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        next_HCTxPortCntl <= `TX_PACKET_STREAM;
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      end
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    `SEND_SOF_WAIT_RDY4:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `SEND_SOF_FIN1;
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
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        next_HCTxPortCntl <= `TX_PACKET_STREAM;
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      end
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    `SEND_SOF_CLR_WEN1:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
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    end
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    `DATA0_DATA1_READ_FIFO:
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    begin
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      next_HCTxPortWEn <= 1'b1;
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      next_HCTxPortData <= fifoData;
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      next_HCTxPortCntl <= `TX_PACKET_STREAM;
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      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
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    end
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    `DATA0_DATA1_WAIT_READ_FIFO:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
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        next_fifoReadEn <= 1'b1;
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      end
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    `DATA0_DATA1_FIFO_EMPTY:
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      if (fifoEmpty == 1'b0)
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        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
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      else
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        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
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    `DATA0_DATA1_FIN:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      NextState_sndPkt <= `FIN_SP;
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    end
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    `DATA0_DATA1_TERM_BYTE:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `DATA0_DATA1_FIN;
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        //Last byte is not valid data,
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        //but the 'TX_PACKET_STOP' flag is required
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        //by the SIE state machine to detect end of data packet
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= 8'h00;
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        next_HCTxPortCntl <= `TX_PACKET_STOP;
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      end
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    `DATA0_DATA1_CLR_WEN:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
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    end
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    `DATA0_DATA1_CLR_REN:
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    begin
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      next_fifoReadEn <= 1'b0;
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      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
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    end
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    `LS_EOP_WAIT_RDY:
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      if (HCTxPortRdy == 1'b1)
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      begin
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        NextState_sndPkt <= `LS_EOP_FIN;
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        next_HCTxPortWEn <= 1'b1;
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        next_HCTxPortData <= 8'h00;
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        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
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      end
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    `LS_EOP_FIN:
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    begin
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      next_HCTxPortWEn <= 1'b0;
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      NextState_sndPkt <= `FIN_SP;
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    end
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : sndPkt_CurrentState
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  if (rst)
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    CurrState_sndPkt <= `START_SP;
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  else
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    CurrState_sndPkt <= NextState_sndPkt;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : sndPkt_RegOutput
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  if (rst)
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  begin
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    sendPacketRdy <= 1'b1;
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    HCTxPortReq <= 1'b0;
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    HCTxPortWEn <= 1'b0;
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    HCTxPortData <= 8'h00;
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    HCTxPortCntl <= 8'h00;
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    frameNum <= 11'h000;
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    fifoReadEn <= 1'b0;
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  end
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  else
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  begin
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    sendPacketRdy <= next_sendPacketRdy;
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    HCTxPortReq <= next_HCTxPortReq;
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    HCTxPortWEn <= next_HCTxPortWEn;
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    HCTxPortData <= next_HCTxPortData;
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    HCTxPortCntl <= next_HCTxPortCntl;
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    frameNum <= next_frameNum;
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    fifoReadEn <= next_fifoReadEn;
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  end
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end
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endmodule

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