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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [slaveDirectControl_simlib.v] - Blame information for rev 408

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1 408 julius
 
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// File        : ../RTL/slaveController/slaveDirectcontrol.v
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// Generated   : 11/10/06 05:37:25
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// From        : ../RTL/slaveController/slaveDirectcontrol.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// slaveDirectControl
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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module slaveDirectControl_simlib (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
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input   SCTxPortGnt;
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input   SCTxPortRdy;
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input   clk;
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input   directControlEn;
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input   [1:0] directControlLineState;
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input   rst;
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output  [7:0] SCTxPortCntl;
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output  [7:0] SCTxPortData;
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output  SCTxPortReq;
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output  SCTxPortWEn;
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reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
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reg     [7:0] SCTxPortData, next_SCTxPortData;
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wire    SCTxPortGnt;
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wire    SCTxPortRdy;
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reg     SCTxPortReq, next_SCTxPortReq;
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reg     SCTxPortWEn, next_SCTxPortWEn;
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wire    clk;
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wire    directControlEn;
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wire    [1:0] directControlLineState;
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wire    rst;
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// BINARY ENCODED state machine: slvDrctCntl
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// State codes definitions:
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`define START_SDC 3'b000
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`define CHK_DRCT_CNTL 3'b001
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`define DRCT_CNTL_WAIT_GNT 3'b010
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`define DRCT_CNTL_CHK_LOOP 3'b011
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`define DRCT_CNTL_WAIT_RDY 3'b100
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`define IDLE_FIN 3'b101
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`define IDLE_WAIT_GNT 3'b110
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`define IDLE_WAIT_RDY 3'b111
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reg [2:0] CurrState_slvDrctCntl;
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reg [2:0] NextState_slvDrctCntl;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// diagram ACTION
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//--------------------------------------------------------------------
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// Machine: slvDrctCntl
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
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begin : slvDrctCntl_NextState
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  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
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  // Set default values for outputs and signals
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  next_SCTxPortReq <= SCTxPortReq;
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  next_SCTxPortWEn <= SCTxPortWEn;
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  next_SCTxPortData <= SCTxPortData;
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  next_SCTxPortCntl <= SCTxPortCntl;
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  case (CurrState_slvDrctCntl)
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    `START_SDC:
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      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
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    `CHK_DRCT_CNTL:
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      if (directControlEn == 1'b1)
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      begin
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        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
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        next_SCTxPortReq <= 1'b1;
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      end
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      else
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      begin
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        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
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        next_SCTxPortReq <= 1'b1;
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      end
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    `DRCT_CNTL_WAIT_GNT:
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      if (SCTxPortGnt == 1'b1)
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        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
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    `DRCT_CNTL_CHK_LOOP:
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    begin
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      next_SCTxPortWEn <= 1'b0;
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      if (directControlEn == 1'b0)
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      begin
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        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
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        next_SCTxPortReq <= 1'b0;
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      end
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      else
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        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
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    end
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    `DRCT_CNTL_WAIT_RDY:
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      if (SCTxPortRdy == 1'b1)
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      begin
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        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
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        next_SCTxPortWEn <= 1'b1;
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        next_SCTxPortData <= {6'b000000, directControlLineState};
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        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
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      end
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    `IDLE_FIN:
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    begin
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      next_SCTxPortWEn <= 1'b0;
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      next_SCTxPortReq <= 1'b0;
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      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
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    end
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    `IDLE_WAIT_GNT:
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      if (SCTxPortGnt == 1'b1)
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        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
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    `IDLE_WAIT_RDY:
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      if (SCTxPortRdy == 1'b1)
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      begin
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        NextState_slvDrctCntl <= `IDLE_FIN;
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        next_SCTxPortWEn <= 1'b1;
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        next_SCTxPortData <= 8'h00;
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        next_SCTxPortCntl <= `TX_IDLE;
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      end
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : slvDrctCntl_CurrentState
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  if (rst)
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    CurrState_slvDrctCntl <= `START_SDC;
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  else
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    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : slvDrctCntl_RegOutput
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  if (rst)
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  begin
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    SCTxPortCntl <= 8'h00;
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    SCTxPortData <= 8'h00;
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    SCTxPortWEn <= 1'b0;
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    SCTxPortReq <= 1'b0;
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  end
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  else
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  begin
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    SCTxPortCntl <= next_SCTxPortCntl;
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    SCTxPortData <= next_SCTxPortData;
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    SCTxPortWEn <= next_SCTxPortWEn;
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    SCTxPortReq <= next_SCTxPortReq;
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  end
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end
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endmodule

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