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julius |
// USB stimulus
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// Adam Edvardsson, adam.edvardsson@orsoc.se
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// Julius Baxter, julius.baxter@orsoc.se
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// Adapted from testbench for usbhostslave project on Opencores by
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// Steve Fielding: http://opencores.org/project,usbhostslave
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// To enable USB host tests, enable core USB0 or USB1 in host-only mode.
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// To enable USB slave tests, enable USB1 in slave only mode
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wire usbClk;
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// We'll hook up the host to these wires
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wire [1:0] usbhostwiredataout;
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wire [1:0] usbhostwiredatain;
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wire usbhostwirectrlout;
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wire usbhostfullspeed;
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// We'll hook up the host to these wires
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wire [1:0] usbslavewiredataout;
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wire [1:0] usbslavewiredatain;
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wire usbslavewirectrlout;
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wire usbslavefullspeed;
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// Depending on which USB core is enabled, and if it's got slave compatibility,
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// we assign the host wires
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`ifdef USB0
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// USB0 can either be host, or hostslave, either way it's got host capability
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// if it's defined
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assign usbhostwiredataout = usb0dat_pad_o;
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assign usbhostwirectrlout = usb0ctrl_pad_o;
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assign usbhostfullspeed = usb0fullspeed_pad_o;
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assign usb0dat_pad_i = usbhostwiredatain;
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`define USB_HOST_TESTS_ENABLE
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`endif // `ifdef USB0
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// check if USB1 should be used as a HOST if USB0 isn't enable
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`ifndef USB_HOST_TESTS_ENABLE
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`ifdef USB1
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`ifndef USB1_ONLY_SLAVE
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// ... and that it's in slave-only configuration
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// then we can use USB1 host instead
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assign usbhostwiredataout = usb1dat_pad_o;
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assign usbhostwirectrlout = usb1ctrl_pad_o;
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assign usbhostfullspeed = usb1fullspeed_pad_o;
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assign usb1dat_pad_i = usbhostwiredatain;
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`define USB_HOST_TESTS_ENABLE
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`endif // `ifndef USB1_ONLY_SLAVE
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`endif // `ifdef USB1
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`endif // `ifndef USB_HOST_TESTS_ENABLE
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`ifdef USB1
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`ifdef USB1_ONLY_SLAVE
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// USB1 is slave only, so we can do the slave tests
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assign usbslavewiredataout = usb1dat_pad_o;
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assign usbslavewirectrlout = usb1ctrl_pad_o;
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assign usbslavefullspeed = usb1fullspeed_pad_o;
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assign usb1dat_pad_i = usbslavewiredatain;
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`define USB_SLAVE_TESTS_ENABLE
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`endif // `ifdef USB1_ONLY_SLAVE
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`endif // `ifdef USB1
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`define SIM_SLAVE_BASE_ADDR 9'h100
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`define CLK_48MHZ_HALF_PERIOD 10.4167
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wire DPlusPullup;
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wire DPlusPullDown;
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wire DMinusPullup;
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wire DMinusPullDown;
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pullup(DPlusPullup);
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pulldown(DPlusPullDown);
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pullup(DMinusPullup);
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pulldown(DMinusPullDown);
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// USB clock generation
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reg usb_clk_generated = 0;
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always
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begin
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#(`CLK_48MHZ_HALF_PERIOD) usb_clk_generated <= !rst_n ? 0 : ~usb_clk_generated;
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end
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assign usbClk = usb_clk_generated;
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// Did we detect a USB host in the design?
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`ifdef USB_HOST_TESTS_ENABLE
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wire [8:0] usbslave_wbmaster_adr;
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wire [7:0] usbslave_wbmaster_din;
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wire [7:0] usbslave_wbmaster_dout;
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wire usbslave_wbmaster_stb;
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wire usbslave_wbmaster_we;
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wire usbslave_wbmaster_ack;
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wire usbhostwirectrlout_oe;
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wire [1:0] usbtbslaveWireDataIn;
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wire [1:0] usbtbslaveWireDataOut;
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wire usbtbslaveDPlusPullup;
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wire usbtbslaveDMinusPullup;
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wire usbtbslaveWireCtrlOut;
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reg USBSlaveWireVP;
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reg USBSlaveWireVM;
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assign usbhostwirectrlout_oe = ~usbhostwirectrlout;
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assign usbhostwiredatain = {USBSlaveWireVP, USBSlaveWireVM};
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assign usbtbslaveWireDataIn = {USBSlaveWireVP, USBSlaveWireVM};
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always @(*) begin
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if (usbhostwirectrlout_oe == 1'b1 && usbtbslaveWireCtrlOut == 1'b0)
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{USBSlaveWireVP, USBSlaveWireVM} <= usbhostwiredataout;
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else if (usbhostwirectrlout_oe == 1'b0 && usbtbslaveWireCtrlOut == 1'b1)
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{USBSlaveWireVP, USBSlaveWireVM} <= usbtbslaveWireDataOut;
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else if (usbhostwirectrlout_oe == 1'b1 && usbtbslaveWireCtrlOut == 1'b1)
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{USBSlaveWireVP, USBSlaveWireVM} <= 2'bxx;
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else if (usbhostwirectrlout_oe == 1'b0 && usbtbslaveWireCtrlOut == 1'b0)
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begin
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if (usbtbslaveDPlusPullup == 1'b1)
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USBSlaveWireVP <= DPlusPullup;
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else
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USBSlaveWireVP <= DPlusPullDown;
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if (usbtbslaveDMinusPullup == 1'b1)
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USBSlaveWireVM <= DMinusPullup;
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else
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USBSlaveWireVM <= DMinusPullDown;
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end
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end
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//Parameters declaration:
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defparam u_slave.EP0_FIFO_DEPTH = 64;
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parameter EP0_FIFO_DEPTH = 64;
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defparam u_slave.EP0_FIFO_ADDR_WIDTH = 6;
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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defparam u_slave.EP1_FIFO_DEPTH = 64;
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parameter EP1_FIFO_DEPTH = 64;
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defparam u_slave.EP1_FIFO_ADDR_WIDTH = 6;
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parameter EP1_FIFO_ADDR_WIDTH = 6;
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defparam u_slave.EP2_FIFO_DEPTH = 64;
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parameter EP2_FIFO_DEPTH = 64;
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defparam u_slave.EP2_FIFO_ADDR_WIDTH = 6;
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parameter EP2_FIFO_ADDR_WIDTH = 6;
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defparam u_slave.EP3_FIFO_DEPTH = 64;
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parameter EP3_FIFO_DEPTH = 64;
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defparam u_slave.EP3_FIFO_ADDR_WIDTH = 6;
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parameter EP3_FIFO_ADDR_WIDTH = 6;
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wire usb_tbslavesofrxed_irq;
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wire usb_tbslaveresetevent_irq;
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wire usb_tbslaveresume_irq;
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wire usb_tbslavetransdone_irq;
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wire usb_tbslavenaksent_irq;
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wire usb_tbslavevbusdet_irq;
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wire usb_tboe, usb_tboe_n;
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// USB slave instantiation
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usbslave_simlib u_slave
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(
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// USB PHY lines
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// In
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.clk_i (clk), // Board clock
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.rst_i (!rst_n),
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.address_i (usbslave_wbmaster_adr[7:0]),
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.data_i (usbslave_wbmaster_dout),
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.data_o (usbslave_wbmaster_din),
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.we_i (usbslave_wbmaster_we),
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.strobe_i (usbslave_wbmaster_stb),
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.ack_o (usbslave_wbmaster_ack),
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.usbClk (usbClk), // logic clock,48MHz +/-0.25%
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// Interrupt lines
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.slaveSOFRxedIntOut (usb_tbslavesofrxed_irq),
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.slaveResetEventIntOut (usb_tbslaveresetevent_irq),
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.slaveResumeIntOut (usb_tbslaveresume_irq),
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.slaveTransDoneIntOut (usb_tbslavetransdone_irq),
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.slaveNAKSentIntOut (usb_tbslavenaksent_irq),
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.slaveVBusDetIntOut (usb_tbslavevbusdet_irq),
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.USBWireDataIn(usbtbslaveWireDataIn),
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.USBWireDataInTick(),
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.USBWireDataOut(usbtbslaveWireDataOut),
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.USBWireDataOutTick(),
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.USBWireCtrlOut(usbtbslaveWireCtrlOut),
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.USBFullSpeed(),
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.USBDPlusPullup(usbtbslaveDPlusPullup),
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.USBDMinusPullup(usbtbslaveDMinusPullup),
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.vBusDetect(1'b1)
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);
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// Wishbone bus master, for controlling USB slave
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wb_master_model
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#(
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.dwidth(8),
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.awidth(9)
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)
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usbslave_wbm
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(
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.clk(clk),
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.rst(!rst_n),
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.adr(usbslave_wbmaster_adr),
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.din(usbslave_wbmaster_din),
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.dout(usbslave_wbmaster_dout),
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.cyc(),
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.stb(usbslave_wbmaster_stb),
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.we(usbslave_wbmaster_we),
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.sel(),
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.ack(usbslave_wbmaster_ack),
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.err(1'b0),
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.rty(1'b0)
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);
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reg [7:0] hostTestData;
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reg [15:0] hostTestDataWord;
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reg [7:0] hostTestDataRead;
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reg [7:0] hostTestDataWrite;
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reg [7:0] hostTestUSBAddress;
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integer hostTestDataSize;
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integer hostTestDataItr;
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// Don't have vbus detect in this system...
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//assign usbhostvbusdetect = 1'b1;
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// Perform transactions and tests through a USB slave to the USB host in the
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// the DUT
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initial
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begin
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wait (usbhostfullspeed);
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$write("USB host tb: USB Host test starts at:%t\n",$time);
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usbslave_wbm.wb_read(1,
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`SIM_SLAVE_BASE_ADDR +
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`HOST_SLAVE_CONTROL_BASE +
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`HOST_SLAVE_VERSION_REG , hostTestDataRead);
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$write("USB host tb: Slave Version number = 0x%0x\n", hostTestDataRead);
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$write("USB host tb: Configure host and slave mode\n");
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usbslave_wbm.wb_write(1,8'he0,8'h0);
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usbslave_wbm.wb_write(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_CONTROL_REG , 8'h70);
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#30000;
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//expecting connection event interrupt
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//expecting change in reset state event, and change in vbus state event
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usbslave_wbm.wb_cmp(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_INTERRUPT_STATUS_REG , 8'h24);
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//expecting full speed connect and vbus present
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usbslave_wbm.wb_cmp(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_LINE_STATUS_REG , 8'h06);
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$write("USB host tb: :USB slave connected and fullspeed enabled\n");
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hostTestUSBAddress = 8'h00;
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#200;
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$write("USB host tb: Slave ENABLE Transport tO EP1\n");
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//enable endpoint, and make ready
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usbslave_wbm.wb_write(1, `SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_CONTROL_REG , 8'h71);
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usbslave_wbm.wb_write(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_ADDRESS , 8'h00);
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usbslave_wbm.wb_write(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`EP0_CTRL_REG , 8'h03);
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//cancel interrupt
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usbslave_wbm.wb_write(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_INTERRUPT_STATUS_REG , 8'hff);
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usbslave_wbm.wb_read(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_INTERRUPT_STATUS_REG , hostTestData);
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while (hostTestData != 8'h01) begin
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usbslave_wbm.wb_read(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_INTERRUPT_STATUS_REG , hostTestData);
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end
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usbslave_wbm.wb_cmp(1,
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`SIM_SLAVE_BASE_ADDR +
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`SCREG_BASE +
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`SC_INTERRUPT_STATUS_REG , 8'h01);
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//endpoint enabled, and endpoint ready cleared
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usbslave_wbm.wb_cmp(1,
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|
|
`SIM_SLAVE_BASE_ADDR +
|
| 328 |
|
|
`SCREG_BASE +
|
| 329 |
|
|
`EP0_CTRL_REG , 8'h01);
|
| 330 |
|
|
$write("USB host tb: Checking receive hostTestData ");
|
| 331 |
|
|
hostTestData = 8'h00;
|
| 332 |
|
|
for (hostTestDataItr=0;
|
| 333 |
|
|
hostTestDataItr<hostTestDataSize;
|
| 334 |
|
|
hostTestDataItr=hostTestDataItr+1) begin
|
| 335 |
|
|
usbslave_wbm.wb_cmp(1,
|
| 336 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 337 |
|
|
`EP0_RX_FIFO_BASE +
|
| 338 |
|
|
`FIFO_DATA_REG , hostTestData);
|
| 339 |
|
|
hostTestData = hostTestData + 1'b1;
|
| 340 |
|
|
end
|
| 341 |
|
|
$write("- PASSED T4\n");
|
| 342 |
|
|
|
| 343 |
|
|
$write("USB host tb: Trans test: Device address = 0x5a, 64 byte OUT DATA0 transaction to Endpoint 1\n");
|
| 344 |
|
|
hostTestUSBAddress = 8'h5a;
|
| 345 |
|
|
hostTestDataSize = 64;
|
| 346 |
|
|
|
| 347 |
|
|
//enable endpoint, and make ready
|
| 348 |
|
|
usbslave_wbm.wb_write(1,
|
| 349 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 350 |
|
|
`SCREG_BASE +
|
| 351 |
|
|
`SC_CONTROL_REG , 8'h71);
|
| 352 |
|
|
usbslave_wbm.wb_write(1, `SIM_SLAVE_BASE_ADDR +
|
| 353 |
|
|
`SCREG_BASE +
|
| 354 |
|
|
`SC_ADDRESS , hostTestUSBAddress);
|
| 355 |
|
|
usbslave_wbm.wb_write(1,
|
| 356 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 357 |
|
|
`SCREG_BASE +
|
| 358 |
|
|
`EP1_CTRL_REG , 8'h03);
|
| 359 |
|
|
//cancel interrupt
|
| 360 |
|
|
usbslave_wbm.wb_write(1,
|
| 361 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 362 |
|
|
`SCREG_BASE +
|
| 363 |
|
|
`SC_INTERRUPT_STATUS_REG , 8'hff);
|
| 364 |
|
|
|
| 365 |
|
|
usbslave_wbm.wb_read(1,
|
| 366 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 367 |
|
|
`SCREG_BASE +
|
| 368 |
|
|
`SC_INTERRUPT_STATUS_REG , hostTestData);
|
| 369 |
|
|
while (hostTestData != 8'h01) begin
|
| 370 |
|
|
usbslave_wbm.wb_read(1,
|
| 371 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 372 |
|
|
`SCREG_BASE +
|
| 373 |
|
|
`SC_INTERRUPT_STATUS_REG , hostTestData);
|
| 374 |
|
|
end
|
| 375 |
|
|
|
| 376 |
|
|
usbslave_wbm.wb_cmp(1,
|
| 377 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 378 |
|
|
`SCREG_BASE +
|
| 379 |
|
|
`SC_INTERRUPT_STATUS_REG , 8'h01);
|
| 380 |
|
|
//endpoint enabled, and endpoint ready cleared
|
| 381 |
|
|
usbslave_wbm.wb_cmp(1,
|
| 382 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 383 |
|
|
`SCREG_BASE +
|
| 384 |
|
|
`EP0_CTRL_REG , 8'h01);
|
| 385 |
|
|
$write("USB host tb: Checking receive hostTestData ");
|
| 386 |
|
|
hostTestData = 8'h00;
|
| 387 |
|
|
for (hostTestDataItr=0;
|
| 388 |
|
|
hostTestDataItr<hostTestDataSize;
|
| 389 |
|
|
hostTestDataItr=hostTestDataItr+1) begin
|
| 390 |
|
|
usbslave_wbm.wb_cmp(1,
|
| 391 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 392 |
|
|
`EP1_RX_FIFO_BASE +
|
| 393 |
|
|
`FIFO_DATA_REG , hostTestData);
|
| 394 |
|
|
hostTestData = hostTestData + 1'b1;
|
| 395 |
|
|
end
|
| 396 |
|
|
$write("- PASSED T5\n");
|
| 397 |
|
|
|
| 398 |
|
|
#2000;
|
| 399 |
|
|
$write("USB host tb: Trans test: Device address = 0x01, 2 byte IN transaction to Endpoint 2\n");
|
| 400 |
|
|
hostTestUSBAddress = 8'h01;
|
| 401 |
|
|
hostTestDataSize = 64;
|
| 402 |
|
|
$write("USB host tb: USB Host test starts at:%t\n",$time);
|
| 403 |
|
|
//enable endpoint, and make ready
|
| 404 |
|
|
usbslave_wbm.wb_write(1,
|
| 405 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 406 |
|
|
`SCREG_BASE +
|
| 407 |
|
|
`SC_CONTROL_REG , 8'h71);
|
| 408 |
|
|
usbslave_wbm.wb_write(1,
|
| 409 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 410 |
|
|
`SCREG_BASE +
|
| 411 |
|
|
`SC_ADDRESS , hostTestUSBAddress);
|
| 412 |
|
|
usbslave_wbm.wb_write(1,
|
| 413 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 414 |
|
|
`SCREG_BASE +
|
| 415 |
|
|
`EP2_CTRL_REG , 8'h03);
|
| 416 |
|
|
usbslave_wbm.wb_write(1,
|
| 417 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 418 |
|
|
`SCREG_BASE +
|
| 419 |
|
|
`SC_INTERRUPT_STATUS_REG , 8'hff);
|
| 420 |
|
|
hostTestData = 8'hC0;
|
| 421 |
|
|
for (hostTestDataItr=64;
|
| 422 |
|
|
hostTestDataItr>0;
|
| 423 |
|
|
hostTestDataItr=hostTestDataItr-1) begin
|
| 424 |
|
|
usbslave_wbm.wb_write(1,
|
| 425 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 426 |
|
|
`EP2_TX_FIFO_BASE +
|
| 427 |
|
|
`FIFO_DATA_REG , hostTestData);
|
| 428 |
|
|
hostTestData = hostTestData - 3'b011;
|
| 429 |
|
|
end
|
| 430 |
|
|
|
| 431 |
|
|
usbslave_wbm.wb_read(1,
|
| 432 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 433 |
|
|
`SCREG_BASE +
|
| 434 |
|
|
`SC_INTERRUPT_STATUS_REG , hostTestData);
|
| 435 |
|
|
while (hostTestData != 8'h01) begin
|
| 436 |
|
|
usbslave_wbm.wb_read(1,
|
| 437 |
|
|
`SIM_SLAVE_BASE_ADDR +
|
| 438 |
|
|
`SCREG_BASE +
|
| 439 |
|
|
`SC_INTERRUPT_STATUS_REG , hostTestData);
|
| 440 |
|
|
end
|
| 441 |
|
|
#3500;
|
| 442 |
|
|
|
| 443 |
|
|
$write("USB host tb: PASSED USB test\n");
|
| 444 |
|
|
$write("USB host tb: Finished all tests\n");
|
| 445 |
|
|
|
| 446 |
|
|
end
|
| 447 |
|
|
|
| 448 |
|
|
|
| 449 |
|
|
`endif // `ifdef USB_HOST_TESTS_ENABLE
|
| 450 |
|
|
|
| 451 |
|
|
|
| 452 |
|
|
`ifdef USB_SLAVE_TESTS_ENABLE
|
| 453 |
|
|
|
| 454 |
|
|
`define SIM_HOST_BASE_ADDR 9'h000
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
wire [8:0] usbhost_wbmaster_adr;
|
| 458 |
|
|
wire [7:0] usbhost_wbmaster_dout;
|
| 459 |
|
|
wire [7:0] usbhost_wbmaster_din;
|
| 460 |
|
|
wire usbhost_wbmaster_we;
|
| 461 |
|
|
wire usbhost_wbmaster_ack;
|
| 462 |
|
|
wire usbhost_wbmaster_stb;
|
| 463 |
|
|
|
| 464 |
|
|
wire usb_tbhostSOFSentIntOut;
|
| 465 |
|
|
wire usb_tbhostConnEventIntOut;
|
| 466 |
|
|
wire usb_tbhostResumeIntOut;
|
| 467 |
|
|
wire usb_tbhostTransDoneIntOut;
|
| 468 |
|
|
|
| 469 |
|
|
reg USBHostWireVP;
|
| 470 |
|
|
reg USBHostWireVM;
|
| 471 |
|
|
|
| 472 |
|
|
wire hostUSBWireCtrlOut;
|
| 473 |
|
|
|
| 474 |
|
|
|
| 475 |
|
|
wire [1:0] hostUSBWireDataIn;
|
| 476 |
|
|
wire [1:0] hostUSBWireDataOut;
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
assign hostUSBWireDataIn = {USBHostWireVP, USBHostWireVM};
|
| 480 |
|
|
assign usbslavewiredatain = {USBHostWireVP, USBHostWireVM};
|
| 481 |
|
|
|
| 482 |
|
|
always @(*) begin
|
| 483 |
|
|
if (hostUSBWireCtrlOut == 1'b1 && !usbslavewirectrlout == 1'b0)
|
| 484 |
|
|
{USBHostWireVP, USBHostWireVM} <= hostUSBWireDataOut;
|
| 485 |
|
|
else if (hostUSBWireCtrlOut == 1'b0 && !usbslavewirectrlout == 1'b1)
|
| 486 |
|
|
{USBHostWireVP, USBHostWireVM} <= usbslavewiredataout;
|
| 487 |
|
|
else if (hostUSBWireCtrlOut == 1'b1 && !usbslavewirectrlout == 1'b1)
|
| 488 |
|
|
{USBHostWireVP, USBHostWireVM} <= 2'bxx;
|
| 489 |
|
|
else if (hostUSBWireCtrlOut == 1'b0 && !usbslavewirectrlout == 1'b0) begin
|
| 490 |
|
|
// No indication of pullup/downs in our design...
|
| 491 |
|
|
// assume VP pullup and VM pull down(!?)
|
| 492 |
|
|
USBHostWireVP <= DPlusPullup;
|
| 493 |
|
|
USBHostWireVM <= DMinusPullDown;
|
| 494 |
|
|
end
|
| 495 |
|
|
end
|
| 496 |
|
|
|
| 497 |
|
|
|
| 498 |
|
|
|
| 499 |
|
|
//Parameters declaration:
|
| 500 |
|
|
defparam u_usbhost.HOST_FIFO_DEPTH = 64;
|
| 501 |
|
|
parameter HOST_FIFO_DEPTH = 64;
|
| 502 |
|
|
defparam u_usbhost.HOST_FIFO_ADDR_WIDTH = 6;
|
| 503 |
|
|
parameter HOST_FIFO_ADDR_WIDTH = 6;
|
| 504 |
|
|
|
| 505 |
|
|
usbhost_simlib u_usbhost
|
| 506 |
|
|
(
|
| 507 |
|
|
.clk_i(clk),
|
| 508 |
|
|
.rst_i(!rst_n),
|
| 509 |
|
|
.address_i(usbhost_wbmaster_adr[7:0]),
|
| 510 |
|
|
.data_i(usbhost_wbmaster_dout),
|
| 511 |
|
|
.data_o(usbhost_wbmaster_din),
|
| 512 |
|
|
.we_i(usbhost_wbmaster_we),
|
| 513 |
|
|
.strobe_i(usbhost_wbmaster_stb),
|
| 514 |
|
|
.ack_o(usbhost_wbmaster_ack),
|
| 515 |
|
|
.usbClk(usbClk),
|
| 516 |
|
|
|
| 517 |
|
|
.hostSOFSentIntOut(usb_tbhostSOFSentIntOut),
|
| 518 |
|
|
.hostConnEventIntOut(usb_tbhostConnEventIntOut),
|
| 519 |
|
|
.hostResumeIntOut(usb_tbhostResumeIntOut),
|
| 520 |
|
|
.hostTransDoneIntOut(usb_tbhostTransDoneIntOut),
|
| 521 |
|
|
.USBWireDataIn(hostUSBWireDataIn),
|
| 522 |
|
|
.USBWireDataInTick(),
|
| 523 |
|
|
.USBWireDataOut(hostUSBWireDataOut),
|
| 524 |
|
|
.USBWireDataOutTick(),
|
| 525 |
|
|
.USBWireCtrlOut(hostUSBWireCtrlOut),
|
| 526 |
|
|
.USBFullSpeed()
|
| 527 |
|
|
|
| 528 |
|
|
|
| 529 |
|
|
);
|
| 530 |
|
|
wb_master_model
|
| 531 |
|
|
#(
|
| 532 |
|
|
.dwidth(8),
|
| 533 |
|
|
.awidth(9)
|
| 534 |
|
|
)
|
| 535 |
|
|
usbhost_wbm
|
| 536 |
|
|
(
|
| 537 |
|
|
.clk(clk),
|
| 538 |
|
|
.rst(!rst_n),
|
| 539 |
|
|
.adr(usbhost_wbmaster_adr),
|
| 540 |
|
|
.din(usbhost_wbmaster_din),
|
| 541 |
|
|
.dout(usbhost_wbmaster_dout),
|
| 542 |
|
|
.cyc(),
|
| 543 |
|
|
.stb(usbhost_wbmaster_stb),
|
| 544 |
|
|
.we(usbhost_wbmaster_we),
|
| 545 |
|
|
.sel(),
|
| 546 |
|
|
.ack(usbhost_wbmaster_ack),
|
| 547 |
|
|
.err(1'b0),
|
| 548 |
|
|
.rty(1'b0)
|
| 549 |
|
|
);
|
| 550 |
|
|
|
| 551 |
|
|
|
| 552 |
|
|
reg [7:0] slaveTestData;
|
| 553 |
|
|
reg [15:0] slaveTestDataWord;
|
| 554 |
|
|
reg [7:0] slaveTestDataRead;
|
| 555 |
|
|
reg [7:0] slaveTestDataWrite;
|
| 556 |
|
|
reg [7:0] slaveTestUSBAddress;
|
| 557 |
|
|
reg [7:0] slaveTestUSBEndPoint;
|
| 558 |
|
|
reg [7:0] slaveTestTransType;
|
| 559 |
|
|
integer slaveTestDataSize;
|
| 560 |
|
|
integer slaveTestDataItr;
|
| 561 |
|
|
|
| 562 |
|
|
// Don't have vbusdetect in this system
|
| 563 |
|
|
//assign usbslavevbusdetect = 1'b1;
|
| 564 |
|
|
|
| 565 |
|
|
initial
|
| 566 |
|
|
begin
|
| 567 |
|
|
|
| 568 |
|
|
wait (usbslavefullspeed);
|
| 569 |
|
|
$write("USB Slave test starts at:%t\n",$time);
|
| 570 |
|
|
|
| 571 |
|
|
#14000;
|
| 572 |
|
|
|
| 573 |
|
|
usbhost_wbm.wb_read(1,
|
| 574 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 575 |
|
|
`HOST_SLAVE_CONTROL_BASE +
|
| 576 |
|
|
`HOST_SLAVE_VERSION_REG , slaveTestDataRead);
|
| 577 |
|
|
$display("Host Version number = 0x%0x\n", slaveTestDataRead);
|
| 578 |
|
|
|
| 579 |
|
|
$write("USB slave tb: Testing host register read/write ");
|
| 580 |
|
|
usbhost_wbm.wb_write(1,
|
| 581 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 582 |
|
|
`HCREG_BASE +
|
| 583 |
|
|
`TX_LINE_CONTROL_REG , 8'h18);
|
| 584 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 585 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 586 |
|
|
`HCREG_BASE +
|
| 587 |
|
|
`TX_LINE_CONTROL_REG , 8'h18);
|
| 588 |
|
|
$write("- PASSED\n");
|
| 589 |
|
|
|
| 590 |
|
|
|
| 591 |
|
|
$write("USB slave tb: Testing register reset ");
|
| 592 |
|
|
usbhost_wbm.wb_write(1,
|
| 593 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 594 |
|
|
`HOST_SLAVE_CONTROL_BASE +
|
| 595 |
|
|
`HOST_SLAVE_CONTROL_REG , 8'h2);
|
| 596 |
|
|
//usbhost_wbm.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
|
| 597 |
|
|
#1000;
|
| 598 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 599 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 600 |
|
|
`HCREG_BASE +
|
| 601 |
|
|
`TX_LINE_CONTROL_REG , 8'h00);
|
| 602 |
|
|
//usbhost_wbm.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h00);
|
| 603 |
|
|
$write("- PASSED\n");
|
| 604 |
|
|
#1000;
|
| 605 |
|
|
|
| 606 |
|
|
$write("USB slave tb: Configuring host\n");
|
| 607 |
|
|
usbhost_wbm.wb_write(1,
|
| 608 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 609 |
|
|
`HOST_SLAVE_CONTROL_BASE +
|
| 610 |
|
|
`HOST_SLAVE_CONTROL_REG , 8'h1);
|
| 611 |
|
|
$write("USB slave tb: Connect full speed ");
|
| 612 |
|
|
usbhost_wbm.wb_write(1,
|
| 613 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 614 |
|
|
`HCREG_BASE +
|
| 615 |
|
|
`TX_LINE_CONTROL_REG , 8'h18);
|
| 616 |
|
|
#20000;
|
| 617 |
|
|
usbhost_wbm.wb_write(1,
|
| 618 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 619 |
|
|
`HCREG_BASE +
|
| 620 |
|
|
`INTERRUPT_STATUS_REG , 8'h04);
|
| 621 |
|
|
|
| 622 |
|
|
$write("- PASSED\n");
|
| 623 |
|
|
#225000;
|
| 624 |
|
|
|
| 625 |
|
|
//Transfer 1
|
| 626 |
|
|
$write("USB slave tb: Trans test 1: Device address = 0x63, 2 byte SETUP transaction to Endpoint 0\n");
|
| 627 |
|
|
slaveTestUSBAddress = 8'h63;
|
| 628 |
|
|
slaveTestUSBEndPoint = 8'h00;
|
| 629 |
|
|
slaveTestTransType = `SETUP_TRANS;
|
| 630 |
|
|
slaveTestDataSize = 2;
|
| 631 |
|
|
|
| 632 |
|
|
usbhost_wbm.wb_write(1,
|
| 633 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 634 |
|
|
`HCREG_BASE +
|
| 635 |
|
|
`INTERRUPT_STATUS_REG , 8'h04);
|
| 636 |
|
|
usbhost_wbm.wb_write(1,
|
| 637 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 638 |
|
|
`HCREG_BASE +
|
| 639 |
|
|
`TX_ADDR_REG , slaveTestUSBAddress);
|
| 640 |
|
|
usbhost_wbm.wb_write(1,
|
| 641 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 642 |
|
|
`HCREG_BASE +
|
| 643 |
|
|
`TX_ENDP_REG , slaveTestUSBEndPoint);
|
| 644 |
|
|
usbhost_wbm.wb_write(1,
|
| 645 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 646 |
|
|
`HCREG_BASE +
|
| 647 |
|
|
`TX_TRANS_TYPE_REG , slaveTestTransType);
|
| 648 |
|
|
slaveTestData = 8'h00;
|
| 649 |
|
|
for (slaveTestDataItr=0;
|
| 650 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 651 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 652 |
|
|
usbhost_wbm.wb_write(1,
|
| 653 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 654 |
|
|
`HOST_TX_FIFO_BASE +
|
| 655 |
|
|
`FIFO_DATA_REG , slaveTestData);
|
| 656 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 657 |
|
|
end
|
| 658 |
|
|
usbhost_wbm.wb_write(1,
|
| 659 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 660 |
|
|
`HCREG_BASE +
|
| 661 |
|
|
`TX_CONTROL_REG , 8'h01);
|
| 662 |
|
|
#35000
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 666 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 667 |
|
|
`HCREG_BASE +
|
| 668 |
|
|
`INTERRUPT_STATUS_REG , 8'h01);
|
| 669 |
|
|
$write("USB slave tb: Transaction done correct interrupt recived\n" );
|
| 670 |
|
|
|
| 671 |
|
|
|
| 672 |
|
|
$write("USB slave tb: Checking receive slaveTestData ");
|
| 673 |
|
|
slaveTestData = 8'h00;
|
| 674 |
|
|
for (slaveTestDataItr=0;
|
| 675 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 676 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 677 |
|
|
|
| 678 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 679 |
|
|
end
|
| 680 |
|
|
$write("- PASSED\n");
|
| 681 |
|
|
|
| 682 |
|
|
//Transfer 2
|
| 683 |
|
|
$write("USB slave tb: Trans test 2: Device address = 0x63, 20 byte OUT DATA0 transaction to Endpoint 1\n");
|
| 684 |
|
|
slaveTestUSBAddress = 8'h63;
|
| 685 |
|
|
slaveTestUSBEndPoint = 8'h00;
|
| 686 |
|
|
slaveTestTransType = `OUTDATA0_TRANS;
|
| 687 |
|
|
slaveTestDataSize = 20;
|
| 688 |
|
|
usbhost_wbm.wb_write(1,
|
| 689 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 690 |
|
|
`HCREG_BASE +
|
| 691 |
|
|
`INTERRUPT_STATUS_REG , 8'h04);
|
| 692 |
|
|
|
| 693 |
|
|
usbhost_wbm.wb_write(1,
|
| 694 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 695 |
|
|
`HCREG_BASE +
|
| 696 |
|
|
`TX_ADDR_REG , slaveTestUSBAddress);
|
| 697 |
|
|
usbhost_wbm.wb_write(1,
|
| 698 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 699 |
|
|
`HCREG_BASE +
|
| 700 |
|
|
`TX_ENDP_REG , slaveTestUSBEndPoint);
|
| 701 |
|
|
usbhost_wbm.wb_write(1,
|
| 702 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 703 |
|
|
`HCREG_BASE +
|
| 704 |
|
|
`TX_TRANS_TYPE_REG , slaveTestTransType);
|
| 705 |
|
|
slaveTestData = 8'h00;
|
| 706 |
|
|
for (slaveTestDataItr=0;
|
| 707 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 708 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 709 |
|
|
usbhost_wbm.wb_write(1,
|
| 710 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 711 |
|
|
`HOST_TX_FIFO_BASE +
|
| 712 |
|
|
`FIFO_DATA_REG , slaveTestData);
|
| 713 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 714 |
|
|
end
|
| 715 |
|
|
usbhost_wbm.wb_write(1,
|
| 716 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 717 |
|
|
`HCREG_BASE +
|
| 718 |
|
|
`TX_CONTROL_REG , 8'h01);
|
| 719 |
|
|
#20000
|
| 720 |
|
|
|
| 721 |
|
|
$write("USB slave tb: Checking received Transaction done interupt\n");
|
| 722 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 723 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 724 |
|
|
`HCREG_BASE +
|
| 725 |
|
|
`INTERRUPT_STATUS_REG , 8'h01);
|
| 726 |
|
|
|
| 727 |
|
|
$write("USB slave tb: Checking receive slaveTestData ");
|
| 728 |
|
|
slaveTestData = 8'h00;
|
| 729 |
|
|
for (slaveTestDataItr=0;
|
| 730 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 731 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 732 |
|
|
//usbhost_wbm.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
|
| 733 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 734 |
|
|
end
|
| 735 |
|
|
$write("- PASSED\n");
|
| 736 |
|
|
#200000
|
| 737 |
|
|
|
| 738 |
|
|
//Transfer 3
|
| 739 |
|
|
$write("USB slave tb: Trans test 3: Device address = 0x63, 20 byte OUT DATA0 transaction to Endpoint 1\n");
|
| 740 |
|
|
slaveTestUSBAddress = 8'h63;
|
| 741 |
|
|
slaveTestUSBEndPoint = 8'h00;
|
| 742 |
|
|
slaveTestTransType = `OUTDATA0_TRANS;
|
| 743 |
|
|
slaveTestDataSize = 2;
|
| 744 |
|
|
usbhost_wbm.wb_write(1,
|
| 745 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 746 |
|
|
`HCREG_BASE +
|
| 747 |
|
|
`INTERRUPT_STATUS_REG , 8'h04);
|
| 748 |
|
|
//enable endpoint, and make ready
|
| 749 |
|
|
|
| 750 |
|
|
usbhost_wbm.wb_write(1,
|
| 751 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 752 |
|
|
`HCREG_BASE +
|
| 753 |
|
|
`TX_ADDR_REG , slaveTestUSBAddress);
|
| 754 |
|
|
usbhost_wbm.wb_write(1,
|
| 755 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 756 |
|
|
`HCREG_BASE +
|
| 757 |
|
|
`TX_ENDP_REG , slaveTestUSBEndPoint);
|
| 758 |
|
|
usbhost_wbm.wb_write(1,
|
| 759 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 760 |
|
|
`HCREG_BASE +
|
| 761 |
|
|
`TX_TRANS_TYPE_REG , slaveTestTransType);
|
| 762 |
|
|
slaveTestData = 8'h00;
|
| 763 |
|
|
for (slaveTestDataItr=0;
|
| 764 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 765 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 766 |
|
|
usbhost_wbm.wb_write(1,
|
| 767 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 768 |
|
|
`HOST_TX_FIFO_BASE +
|
| 769 |
|
|
`FIFO_DATA_REG , slaveTestData);
|
| 770 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 771 |
|
|
end
|
| 772 |
|
|
usbhost_wbm.wb_write(1,
|
| 773 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 774 |
|
|
`HCREG_BASE +
|
| 775 |
|
|
`TX_CONTROL_REG , 8'h01);
|
| 776 |
|
|
#20000
|
| 777 |
|
|
|
| 778 |
|
|
$write("USB slave tb: Checking received Transaction done interupt ");
|
| 779 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 780 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 781 |
|
|
`HCREG_BASE +
|
| 782 |
|
|
`INTERRUPT_STATUS_REG , 8'h01);
|
| 783 |
|
|
|
| 784 |
|
|
|
| 785 |
|
|
slaveTestData = 8'h00;
|
| 786 |
|
|
for (slaveTestDataItr=0;
|
| 787 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 788 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 789 |
|
|
//usbhost_wbm.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , slaveTestData);
|
| 790 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 791 |
|
|
end
|
| 792 |
|
|
$write("- PASSED\n");
|
| 793 |
|
|
#200000
|
| 794 |
|
|
|
| 795 |
|
|
//Transfer 4
|
| 796 |
|
|
$write("USB slave tb: Trans test 4: Device address = 0x63, 2 byte IN transaction to Endpoint 2\n");
|
| 797 |
|
|
slaveTestUSBAddress = 8'h63;
|
| 798 |
|
|
slaveTestUSBEndPoint = 8'h02;
|
| 799 |
|
|
slaveTestTransType = `IN_TRANS;
|
| 800 |
|
|
slaveTestDataSize = 20;
|
| 801 |
|
|
//enable endpoint, and make ready
|
| 802 |
|
|
usbhost_wbm.wb_write(1,
|
| 803 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 804 |
|
|
`HCREG_BASE +
|
| 805 |
|
|
`INTERRUPT_STATUS_REG , 8'h3f);
|
| 806 |
|
|
usbhost_wbm.wb_write(1,
|
| 807 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 808 |
|
|
`HCREG_BASE +
|
| 809 |
|
|
`TX_ADDR_REG , slaveTestUSBAddress);
|
| 810 |
|
|
usbhost_wbm.wb_write(1,
|
| 811 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 812 |
|
|
`HCREG_BASE +
|
| 813 |
|
|
`TX_ENDP_REG , slaveTestUSBEndPoint);
|
| 814 |
|
|
usbhost_wbm.wb_write(1,
|
| 815 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 816 |
|
|
`HCREG_BASE +
|
| 817 |
|
|
`TX_TRANS_TYPE_REG , slaveTestTransType);
|
| 818 |
|
|
slaveTestData = 8'h00;
|
| 819 |
|
|
for (slaveTestDataItr=0;
|
| 820 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 821 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 822 |
|
|
//usbhost_wbm.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , slaveTestData);
|
| 823 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 824 |
|
|
end
|
| 825 |
|
|
#20000
|
| 826 |
|
|
usbhost_wbm.wb_write(1,
|
| 827 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 828 |
|
|
`HCREG_BASE +
|
| 829 |
|
|
`TX_CONTROL_REG , 8'h01);
|
| 830 |
|
|
#200000
|
| 831 |
|
|
//expecting transaction done interrupt
|
| 832 |
|
|
$write("USB slave tb: USB Slave transaction done interrupt at:%t\n",$time);
|
| 833 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 834 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 835 |
|
|
`HCREG_BASE +
|
| 836 |
|
|
`INTERRUPT_STATUS_REG , 8'h01);
|
| 837 |
|
|
|
| 838 |
|
|
|
| 839 |
|
|
$write("USB slave tb: Checking receive slaveTestData ");
|
| 840 |
|
|
slaveTestData = 8'h0;
|
| 841 |
|
|
for (slaveTestDataItr=0;
|
| 842 |
|
|
slaveTestDataItr<slaveTestDataSize;
|
| 843 |
|
|
slaveTestDataItr=slaveTestDataItr+1) begin
|
| 844 |
|
|
usbhost_wbm.wb_cmp(1,
|
| 845 |
|
|
`SIM_HOST_BASE_ADDR +
|
| 846 |
|
|
`HOST_RX_FIFO_BASE +
|
| 847 |
|
|
`FIFO_DATA_REG ,slaveTestData);
|
| 848 |
|
|
slaveTestData = slaveTestData + 1'b1;
|
| 849 |
|
|
end
|
| 850 |
|
|
$write("-PASSED\n");
|
| 851 |
|
|
|
| 852 |
|
|
$write("Finished all tests\n");
|
| 853 |
|
|
|
| 854 |
|
|
end
|
| 855 |
|
|
|
| 856 |
|
|
|
| 857 |
|
|
|
| 858 |
|
|
|
| 859 |
|
|
|
| 860 |
|
|
`endif
|
| 861 |
|
|
|
| 862 |
|
|
|
| 863 |
|
|
|
