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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Blame information for rev 397

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/*$$HEADER*/
/******************************************************************************/
/*                                                                            */
/*                    H E A D E R   I N F O R M A T I O N                     */
/*                                                                            */
/******************************************************************************/
 
// Project Name                   : ORPSoCv2
// File Name                      : rsp-rtl_sim.c
// Prepared By                    : jb, jb@orsoc.se
// Project Start                  : 2009-05-01
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/*                                                                            */
/*                      C O P Y R I G H T   N O T I C E                       */
/*                                                                            */
/******************************************************************************/
/*
  This library is free software; you can redistribute it and/or
  modify it under the terms of the GNU Lesser General Public
  License as published by the Free Software Foundation;
  version 2.1 of the License, a copy of which is available from
  http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
 
  This library is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  Lesser General Public License for more details.
 
  You should have received a copy of the GNU Lesser General Public
  License along with this library; if not, write to the Free Software
  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
*/
 
 
/* Establishes GDB proxy server and communicates via pipes
   to some functions running under the VPI in an RTL sim */
 
#include <stdio.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <assert.h>
 
#include <ctype.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdarg.h>
#include <fcntl.h>
#include <errno.h>
#include <signal.h>
 
#include "gdb.h"
#include "rsp-rtl_sim.h"
#include "rsp-vpi.h"
 
static int err = 0;
 
/* Currently selected scan chain - just to prevent unnecessary
   transfers. */
static int current_chain = -1;
 
/* The chain that should be currently selected. */
static int dbg_chain = -1;
 
/* Crc of current read or written data.  */
static int crc_r, crc_w = 0;
 
/* Generates new crc, sending in new bit input_bit */
static uint32_t crc_calc(uint32_t crc, int input_bit) {
  uint32_t d = (input_bit&1) ? 0xfffffff : 0x0000000;
  uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
  crc <<= 1;
  return crc ^ (d ^ crc_32) & DBG_CRC_POLY;
}
 
/* VPI communication prototyopes */
static void get_response_from_vpi();
static void get_word_from_vpi();
static void get_byte_from_vpi();
static void get_block_data_from_vpi(int len, uint32_t *data);
static void send_data_to_vpi(uint32_t data);
static void send_block_data_to_vpi(int len, uint32_t *data);
static void send_address_to_vpi(uint32_t address);
static void send_command_to_vpi(char CMD);
 
void send_command_to_vpi(char CMD)
{
  // first thing we do  is send a command
  // and wait for an ack
  int n;
  char cmd_resp;
 
  if (DBG_CALLS)printf("send_command_to_vpi: cmd 0x%x \n", CMD);
 
  //n = write(rsp_to_vpi_pipe[1],&CMD, 1); // send the command to the sim
  n = write(command_pipe[1],&CMD, 1); // send the command to the sim
 
  if (n < 0)   error("ERROR writing to VPI FIFO");
 
  n = read(vpi_to_rsp_pipe[0],&cmd_resp,1); // block and wait for the ack
 
  if (cmd_resp != CMD) error("Response from RTL sim incorrect"); //check it acked with cmd
 
  return;
}
 
void send_address_to_vpi(uint32_t address)
{
  // Now send address
  int n;
 
  char* send_buf;
 
  if (DBG_CALLS)printf("send_address_to_vpi: address 0x%.8x\n",address);
 
  send_buf = (char *) &address;
 
  n = write(rsp_to_vpi_pipe[1],send_buf, 4); // send the address to the sim
 
  if (n < 0)   error("ERROR writing to VPI socket");
 
  return;
}
 
void send_data_to_vpi(uint32_t data)
{
  // Now send data
  int n;
 
  char* send_buf;
 
  if (DBG_CALLS)printf("send_data_to_vpi: data 0x%.8x\n",data);
 
  send_buf = (char *) &data;
 
  n = write(rsp_to_vpi_pipe[1],send_buf, 4); // Write the data to the socket
 
  if (n < 0)   error("ERROR writing to VPI socket");
 
  return;
 
}
 
void send_block_data_to_vpi(int len, uint32_t *data)
{
  // Now send data
  int n, i;
 
  char* send_buf;
 
  if (DBG_CALLS)printf("send_block_data_to_vpi: len %d\n",len);
 
  send_buf = (char *) data;
 
  n = write(rsp_to_vpi_pipe[1],send_buf, len); // Write the data to the fifo
 
  if (n < 0)   error("ERROR writing to VPI socket");
 
  return;
 
}
 
 
void get_byte_from_vpi(uint8_t* data)
{
 
  int n;
 
  uint8_t inc_data;
 
  char* recv_buf;
 
  recv_buf = (char*) &inc_data;
 
  n = read(vpi_to_rsp_pipe[0],recv_buf,1); // block and wait for the data
 
  if (DBG_VPI) printf("rsp-rtl_sim: get_byte_from_vpi: 0x%.8x\n",inc_data);
 
  *data = inc_data;
 
  return;
 
}
 
void get_word_from_vpi(uint32_t* data)
{
 
  int n;
 
  uint32_t inc_data;
 
  char* recv_buf;
 
  recv_buf = (char*) &inc_data;
 
  n = read(vpi_to_rsp_pipe[0],recv_buf,4); // block and wait for the data
 
  if (DBG_VPI) printf("rsp-rtl_sim: get_word_from_vpi: 0x%.8x\n",inc_data);
 
  *data = inc_data;
 
  return;
 
}
 
void get_block_data_from_vpi(int len, uint32_t* data)
{
  int n, i, status;
 
  uint32_t inc_data;
 
  char* recv_buf;
 
  uint32_t* data_ptr;
 
  recv_buf = (char *) data;
 
  n=0;
 
  if (DBG_CALLS)printf("rsp_rtl_sim: get_block_data_from_vpi len %d\n",len);
 
  while (n < len)
    {
 
      status = read(vpi_to_rsp_pipe[0], recv_buf, len - n); // block and wait for the data
 
      if (status > 0) n += status; // we read "status" number of bytes
 
    }
 
 
  if (DBG_VPI){
    printf("rsp-rtl_sim: get_block_data_from_vpi: %d bytes: ",len);
    for (i = 0;i < (len); i++)
      {
        if ((i%12) == 0) printf("\n\t");
        printf("%.2x",recv_buf[i]);
        if ((i%3) == 0) printf(" ");
 
      }
    printf("\n");
  }
 
  return;
 
}
 
void get_response_from_vpi()
{
  // Basically just wait for the response from VPI
  // by blocking wait on recv
 
  int n = 0;
  char tmp;
 
  if (DBG_CALLS)printf("get_response_from_vpi..");
 
  n = read(vpi_to_rsp_pipe[0],&tmp,1); // block and wait
 
  if (DBG_CALLS)printf("OK\n");
 
  return;
}
 
static void jp2_reset_JTAG() {
  int i;
 
  debug2("\nreset(");
 
  send_command_to_vpi(CMD_RESET);
 
  get_response_from_vpi();
 
  debug2(")\n");
 
}
 
/* Resets JTAG, and sets DEBUG scan chain */
 int dbg_reset() {
 
   int err;
   uint32_t id;
 
   jp2_reset_JTAG();
 
  /* set idcode jtag chain */
  send_command_to_vpi(CMD_JTAG_SET_IR);
 
  send_data_to_vpi(JI_IDCODE);
 
  get_response_from_vpi();
 
  /* now read out the jtag id */
  send_command_to_vpi(CMD_READ_JTAG_ID);
 
  //id = get_word_from_vpi();  
  get_word_from_vpi((uint32_t *)&id);
 
  get_response_from_vpi();
 
  printf("JTAG ID = %08x\n", id);
 
  /* now set the chain to debug */
  send_command_to_vpi(CMD_JTAG_SET_IR);
 
  send_data_to_vpi(JI_DEBUG);
 
  get_response_from_vpi();
 
  current_chain = -1;
  return DBG_ERR_OK;
}
 
/* counts retries and returns zero if we should abort */
/* TODO: dinamically adjust timings for jp2 */
static int retry_no = 0;
int retry_do() {
  int i, err;
  printf("RETRY\n");
  //exit(2);
  if (retry_no >= NUM_SOFT_RETRIES) {
    if ((err = dbg_reset())) return err;
  }
  if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {
    retry_no = 0;
    return 0;
  }
  retry_no++;
  return 1;
}
 
/* resets retry counter */
void retry_ok() {
  retry_no = 0;
}
 
/* Sets scan chain.  */
int dbg_set_chain(int chain) {
 
  debug("\n");
  debug2("dbg_set_chain %d\n", chain);
 
  if (current_chain == chain)
    return DBG_ERR_OK;
 
  if (DBG_CALLS)printf("dbg_set_chain chain %d \n", chain);
 
  dbg_chain = chain;
 
  send_command_to_vpi(CMD_SET_DEBUG_CHAIN);
 
  send_data_to_vpi(chain);
 
  get_response_from_vpi();
 
  current_chain = chain;
 
  return DBG_ERR_OK;
}
 
/* writes a ctrl reg */
int dbg_ctrl(int reset, int stall)
{
 
  debug("\n");
  debug2("ctrl\n");
 
  if (DBG_CALLS)printf("dbg_ctrl: reset %d stall %d \n", reset, stall);
 
  dbg_set_chain(dbg_chain);
 
  send_command_to_vpi(CMD_CPU_CTRL_WR);
 
  //send_data_to_vpi(((reset & 0x1) | ((stall&0x1)<<1)));
  send_data_to_vpi(((stall & 0x1) | ((reset&0x1)<<1)));
 
  get_response_from_vpi();
 
  return DBG_ERR_OK;
}
 
/* reads control register */
int dbg_ctrl_read(int *reset, int *stall)
{
 
  uint32_t resp;
 
  dbg_set_chain(dbg_chain);
 
  debug("\n");
  debug2("ctrl\n");
 
  if (DBG_CALLS)printf("dbg_ctrl_read\n");
 
  dbg_set_chain(dbg_chain);
 
  send_command_to_vpi(CMD_CPU_CTRL_RD);
 
  get_word_from_vpi((uint32_t *)&resp);
 
  if (DBG_VPI) printf("rsp-rtl_sim: dbg_ctrl_read: 0x%.8x\n",resp);
 
  get_response_from_vpi();
 
  *reset = (int)(resp & 0x00000001);
 
  *stall = (int)((resp >> 1) & 0x00000001);
 
  return DBG_ERR_OK;
}
 
/* read a word from wishbone */
int dbg_wb_read32(uint32_t adr, uint32_t *data)
{
  if (DBG_CALLS)printf("dbg_wb_read32: adr 0x%.8x \n",adr);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_RD32);
 
  send_address_to_vpi(adr);
 
  get_word_from_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* read a word from wishbone */
int dbg_wb_read8(uint32_t adr, uint8_t *data)
{
  if (DBG_CALLS)printf("dbg_wb_read8: adr 0x%.8x \n",adr);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_RD8);
 
  send_address_to_vpi(adr);
 
  get_byte_from_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* write a word to wishbone */
int dbg_wb_write32(uint32_t adr, uint32_t data)
{
 
  if (DBG_CALLS)printf("dbg_wb_write32: adr 0x%.8x data 0x%.8x\n",adr, data);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_WR);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(sizeof(data));
 
  send_data_to_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* write a hword to wishbone */
int dbg_wb_write16(uint32_t adr, uint16_t data)
{
 
  if (DBG_CALLS)printf("dbg_wb_write16: adr 0x%.8x data 0x%.4x\n",adr, data);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_WR);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(sizeof(data));
 
  send_data_to_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* write a word to wishbone */
int dbg_wb_write8(uint32_t adr, uint8_t data)
{
 
  if (DBG_CALLS)printf("dbg_wb_write8: adr 0x%.8x data 0x%.2x\n",adr, data);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_WR);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(sizeof(data));
 
  send_data_to_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
 
/* read a block from wishbone */
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len)
{
 
  // len is in B Y T E S ! !
 
  if (DBG_VPI) printf("xbrsp-rtl_sim: block read len: %d from addr: 0x%.8x\n",len, adr);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_BLOCK_RD32);
 
  send_data_to_vpi(adr);
 
  send_data_to_vpi(len);
 
  get_block_data_from_vpi(len, data);
 
  get_response_from_vpi();
 
  return DBG_ERR_OK;
}
 
/* write a block to wishbone */
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len)
{
 
  if (DBG_CALLS)printf("dbg_wb_block32: adr 0x%.8x len %d bytes\n",adr, len);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_BLOCK_WR32);
 
  send_data_to_vpi(adr);
 
  send_data_to_vpi(len);
 
  send_block_data_to_vpi(len, data);
 
  get_response_from_vpi();
 
  return DBG_ERR_OK;
}
 
/* read a register from cpu */
int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length)
{
 
  if (DBG_CALLS)printf("dbg_cpu0_read: adr 0x%.8x\n",adr);
 
  dbg_set_chain(DC_CPU0);
 
  send_command_to_vpi(CMD_CPU_RD_REG);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(length); // Added 090901 --jb
 
  get_block_data_from_vpi(length, data); // changed 090901 --jb //get_word_from_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
 
}
 
/* write a cpu register */
int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length)
{
 
  if (DBG_CALLS)printf("dbg_cpu0_write: adr 0x%.8x\n",adr);
 
  dbg_set_chain(DC_CPU0);
 
  send_command_to_vpi(CMD_CPU_WR_REG);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(length); // Added 090901 -- jb
 
  send_block_data_to_vpi(length, data); // Added 090901 -- jb
 
  get_response_from_vpi();
 
  return 0;
}
 
/* read a register from cpu */
int dbg_cpu1_read(uint32_t adr, uint32_t *data) {
  /*
  int err;
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_command(0x6, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
  *data = ntohl(*data);
  */
  return DBG_ERR_OK;
}
 
/* write a cpu register */
int dbg_cpu1_write(uint32_t adr, uint32_t data) {
  /*
  int err;
  data = ntohl(data);
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_command(0x2, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
  */
  return DBG_ERR_OK;
}
 
/* read a register from cpu module */
int dbg_cpu1_read_ctrl(uint32_t adr, unsigned char *data) {
  /*
    int err;
    int r, s;
    if ((err = dbg_set_chain(DC_CPU1))) return err;
    if ((err = dbg_ctrl_read(&r, &s))) return err;
    *data = (r << 1) | s;
    */
  return DBG_ERR_OK;
}
 
/* write a cpu module register */
int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data) {
  int err;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
  return DBG_ERR_OK;
}
 
/* read a register from cpu module */
int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data) {
  int err;
  int r, s;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_ctrl_read(&r, &s))) return err;
  *data = (r << 1) | s;
  return DBG_ERR_OK;
}
 
void dbg_test() {
  int i;
  uint32_t npc, ppc, r1, insn, result;
  unsigned char stalled;
  //    uint32_t stalled;
  unsigned char read_byte;
 
  printf("  Stall or1k\n");
  dbg_cpu0_write_ctrl(0, 0x01);      // stall or1k
 
  dbg_cpu0_read_ctrl(0, &stalled);
  if (!(stalled & 0x1)) {
    printf("\tor1k stall failed. read: 0x%x\n", stalled);   // check stall or1k
    //exit(1);
  }
 
  /* Read NPC,PPC and SR regs, they are consecutive in CPU, at adr. 16, 17 and 18 */
  uint32_t pcs_and_sr[3];
  debug2("  Reading npc, ppc\n");
  dbg_cpu0_read(16, (uint32_t *)pcs_and_sr, 3 * 4);
 
  debug2("  Reading r1\n");
  dbg_cpu0_read(0x401, &r1, 4);
  printf("  Read      npc = %.8x ppc = %.8x r1 = %.8x\n",
         pcs_and_sr[0], pcs_and_sr[2], r1);
 
}
 
// Catch the term/int signals, close gdb then close ourselves
void catch_sigint(int sig_num)
{
  gdb_close();
  exit(0);
}
 
void dbg_client_detached(void)
{
  // Send this message back to the sim
  send_command_to_vpi(CMD_GDB_DETACH);
}
 
 
// This function is called after the fork in the VPI function.
 
void run_rsp_server(int portNum)
{
  // Send commands to init and reset debug interface
  dbg_reset();
  // Stall and read NPC, PPC etc
  dbg_test();
 
  set_rsp_server_port(portNum);
 
  // Install SIGINT/SIGTERM handlers, to close down gracefully
  signal(SIGINT, catch_sigint);
  signal(SIGTERM, catch_sigint);
 
  if (DBG_ON) printf("rsp-rtl_sim: starting handle_rsp()\n");
  // Now, start the RSP server. This should not return
  handle_rsp ();
 
  // Exit gracefully if it returns (shouldn't though)
  exit(0);
 
}
 
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Blame information for rev 397

Line No.	Rev	Author	Line
1	40	julius	`/$$HEADER/`
2			`/******************************************************************************/`
3			`/* */`
4			`/* H E A D E R I N F O R M A T I O N */`
5			`/* */`
6			`/******************************************************************************/`
7
8			`// Project Name : ORPSoCv2`
9			`// File Name : rsp-rtl_sim.c`
10			`// Prepared By : jb, jb@orsoc.se`
11			`// Project Start : 2009-05-01`
12
13			`/$$COPYRIGHT NOTICE/`
14			`/******************************************************************************/`
15			`/* */`
16			`/* C O P Y R I G H T N O T I C E */`
17			`/* */`
18			`/******************************************************************************/`
19			`/*`
20			`This library is free software; you can redistribute it and/or`
21			`modify it under the terms of the GNU Lesser General Public`
22			`License as published by the Free Software Foundation;`
23			`version 2.1 of the License, a copy of which is available from`
24			`http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.`
25
26			`This library is distributed in the hope that it will be useful,`
27			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
29			`Lesser General Public License for more details.`
30
31			`You should have received a copy of the GNU Lesser General Public`
32			`License along with this library; if not, write to the Free Software`
33			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
34			`*/`
35
36
37			`/* Establishes GDB proxy server and communicates via pipes`
38			`to some functions running under the VPI in an RTL sim */`
39
40			`#include <stdio.h>`
41			`#include <sys/stat.h>`
42			`#include <sys/types.h>`
43			`#include <assert.h>`
44
45			`#include <ctype.h>`
46			`#include <stdint.h>`
47			`#include <string.h>`
48			`#include <stdlib.h>`
49			`#include <unistd.h>`
50			`#include <stdarg.h>`
51			`#include <fcntl.h>`
52			`#include <errno.h>`
53			`#include <signal.h>`
54
55			`#include "gdb.h"`
56			`#include "rsp-rtl_sim.h"`
57			`#include "rsp-vpi.h"`
58
59			`static int err = 0;`
60
61			`/* Currently selected scan chain - just to prevent unnecessary`
62			`transfers. */`
63			`static int current_chain = -1;`
64
65			`/* The chain that should be currently selected. */`
66			`static int dbg_chain = -1;`
67
68			`/* Crc of current read or written data. */`
69			`static int crc_r, crc_w = 0;`
70
71			`/* Generates new crc, sending in new bit input_bit */`
72			`static uint32_t crc_calc(uint32_t crc, int input_bit) {`
73			`uint32_t d = (input_bit&1) ? 0xfffffff : 0x0000000;`
74			`uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;`
75			`crc <<= 1;`
76			`return crc ^ (d ^ crc_32) & DBG_CRC_POLY;`
77			`}`
78
79			`/* VPI communication prototyopes */`
80			`static void get_response_from_vpi();`
81	397	julius	`static void get_word_from_vpi();`
82			`static void get_byte_from_vpi();`
83	40	julius	`static void get_block_data_from_vpi(int len, uint32_t *data);`
84			`static void send_data_to_vpi(uint32_t data);`
85			`static void send_block_data_to_vpi(int len, uint32_t *data);`
86			`static void send_address_to_vpi(uint32_t address);`
87			`static void send_command_to_vpi(char CMD);`
88
89			`void send_command_to_vpi(char CMD)`
90			`{`
91			`// first thing we do is send a command`
92			`// and wait for an ack`
93			`int n;`
94			`char cmd_resp;`
95
96	46	julius	`if (DBG_CALLS)printf("send_command_to_vpi: cmd 0x%x \n", CMD);`
97	40	julius
98			`//n = write(rsp_to_vpi_pipe[1],&CMD, 1); // send the command to the sim`
99			`n = write(command_pipe[1],&CMD, 1); // send the command to the sim`
100
101			`if (n < 0) error("ERROR writing to VPI FIFO");`
102
103			`n = read(vpi_to_rsp_pipe[0],&cmd_resp,1); // block and wait for the ack`
104
105			`if (cmd_resp != CMD) error("Response from RTL sim incorrect"); //check it acked with cmd`
106
107			`return;`
108			`}`
109
110			`void send_address_to_vpi(uint32_t address)`
111			`{`
112			`// Now send address`
113			`int n;`
114
115			`char* send_buf;`
116
117	46	julius	`if (DBG_CALLS)printf("send_address_to_vpi: address 0x%.8x\n",address);`
118
119	40	julius	`send_buf = (char *) &address;`
120
121			`n = write(rsp_to_vpi_pipe[1],send_buf, 4); // send the address to the sim`
122
123			`if (n < 0) error("ERROR writing to VPI socket");`
124
125			`return;`
126			`}`
127
128			`void send_data_to_vpi(uint32_t data)`
129			`{`
130			`// Now send data`
131			`int n;`
132
133			`char* send_buf;`
134
135	46	julius	`if (DBG_CALLS)printf("send_data_to_vpi: data 0x%.8x\n",data);`
136
137	40	julius	`send_buf = (char *) &data;`
138
139			`n = write(rsp_to_vpi_pipe[1],send_buf, 4); // Write the data to the socket`
140
141			`if (n < 0) error("ERROR writing to VPI socket");`
142
143			`return;`
144
145			`}`
146
147			`void send_block_data_to_vpi(int len, uint32_t *data)`
148			`{`
149			`// Now send data`
150			`int n, i;`
151
152			`char* send_buf;`
153	46	julius
154			`if (DBG_CALLS)printf("send_block_data_to_vpi: len %d\n",len);`
155	40	julius
156			`send_buf = (char *) data;`
157
158			`n = write(rsp_to_vpi_pipe[1],send_buf, len); // Write the data to the fifo`
159
160			`if (n < 0) error("ERROR writing to VPI socket");`
161
162			`return;`
163
164			`}`
165
166	397	julius
167			`void get_byte_from_vpi(uint8_t* data)`
168	40	julius	`{`
169
170			`int n;`
171
172	397	julius	`uint8_t inc_data;`
173
174			`char* recv_buf;`
175
176			`recv_buf = (char*) &inc_data;`
177
178			`n = read(vpi_to_rsp_pipe[0],recv_buf,1); // block and wait for the data`
179
180			`if (DBG_VPI) printf("rsp-rtl_sim: get_byte_from_vpi: 0x%.8x\n",inc_data);`
181
182			`*data = inc_data;`
183
184			`return;`
185
186			`}`
187
188			`void get_word_from_vpi(uint32_t* data)`
189			`{`
190
191			`int n;`
192
193	40	julius	`uint32_t inc_data;`
194
195			`char* recv_buf;`
196
197			`recv_buf = (char*) &inc_data;`
198
199			`n = read(vpi_to_rsp_pipe[0],recv_buf,4); // block and wait for the data`
200
201	397	julius	`if (DBG_VPI) printf("rsp-rtl_sim: get_word_from_vpi: 0x%.8x\n",inc_data);`
202	40	julius
203			`*data = inc_data;`
204
205			`return;`
206
207			`}`
208
209			`void get_block_data_from_vpi(int len, uint32_t* data)`
210			`{`
211			`int n, i, status;`
212
213			`uint32_t inc_data;`
214
215			`char* recv_buf;`
216
217			`uint32_t* data_ptr;`
218
219			`recv_buf = (char *) data;`
220
221			`n=0;`
222
223	46	julius	`if (DBG_CALLS)printf("rsp_rtl_sim: get_block_data_from_vpi len %d\n",len);`
224
225	40	julius	`while (n < len)`
226			`{`
227
228			`status = read(vpi_to_rsp_pipe[0], recv_buf, len - n); // block and wait for the data`
229
230			`if (status > 0) n += status; // we read "status" number of bytes`
231
232			`}`
233	46	julius
234
235	40	julius	`if (DBG_VPI){`
236	46	julius	`printf("rsp-rtl_sim: get_block_data_from_vpi: %d bytes: ",len);`
237			`for (i = 0;i < (len); i++)`
238	40	julius	`{`
239	46	julius	`if ((i%12) == 0) printf("\n\t");`
240			`printf("%.2x",recv_buf[i]);`
241			`if ((i%3) == 0) printf(" ");`
242
243	40	julius	`}`
244			`printf("\n");`
245			`}`
246
247			`return;`
248
249			`}`
250
251			`void get_response_from_vpi()`
252			`{`
253			`// Basically just wait for the response from VPI`
254			`// by blocking wait on recv`
255
256			`int n = 0;`
257			`char tmp;`
258
259	397	julius	`if (DBG_CALLS)printf("get_response_from_vpi..");`
260	46	julius
261	40	julius	`n = read(vpi_to_rsp_pipe[0],&tmp,1); // block and wait`
262	397	julius
263			`if (DBG_CALLS)printf("OK\n");`
264	40	julius
265			`return;`
266			`}`
267
268			`static void jp2_reset_JTAG() {`
269			`int i;`
270
271			`debug2("\nreset(");`
272
273			`send_command_to_vpi(CMD_RESET);`
274
275			`get_response_from_vpi();`
276
277			`debug2(")\n");`
278
279			`}`
280
281			`/* Resets JTAG, and sets DEBUG scan chain */`
282			`int dbg_reset() {`
283
284			`int err;`
285			`uint32_t id;`
286
287			`jp2_reset_JTAG();`
288
289			`/* set idcode jtag chain */`
290			`send_command_to_vpi(CMD_JTAG_SET_IR);`
291
292			`send_data_to_vpi(JI_IDCODE);`
293
294			`get_response_from_vpi();`
295
296			`/* now read out the jtag id */`
297			`send_command_to_vpi(CMD_READ_JTAG_ID);`
298
299	397	julius	`//id = get_word_from_vpi();`
300			`get_word_from_vpi((uint32_t *)&id);`
301	40	julius
302			`get_response_from_vpi();`
303
304			`printf("JTAG ID = %08x\n", id);`
305
306			`/* now set the chain to debug */`
307			`send_command_to_vpi(CMD_JTAG_SET_IR);`
308
309			`send_data_to_vpi(JI_DEBUG);`
310
311			`get_response_from_vpi();`
312
313			`current_chain = -1;`
314			`return DBG_ERR_OK;`
315			`}`
316
317			`/* counts retries and returns zero if we should abort */`
318			`/* TODO: dinamically adjust timings for jp2 */`
319			`static int retry_no = 0;`
320			`int retry_do() {`
321			`int i, err;`
322			`printf("RETRY\n");`
323			`//exit(2);`
324			`if (retry_no >= NUM_SOFT_RETRIES) {`
325			`if ((err = dbg_reset())) return err;`
326			`}`
327			`if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {`
328			`retry_no = 0;`
329			`return 0;`
330			`}`
331			`retry_no++;`
332			`return 1;`
333			`}`
334
335			`/* resets retry counter */`
336			`void retry_ok() {`
337			`retry_no = 0;`
338			`}`
339
340			`/* Sets scan chain. */`
341			`int dbg_set_chain(int chain) {`
342
343			`debug("\n");`
344			`debug2("dbg_set_chain %d\n", chain);`
345
346			`if (current_chain == chain)`
347			`return DBG_ERR_OK;`
348	46	julius
349			`if (DBG_CALLS)printf("dbg_set_chain chain %d \n", chain);`
350	40	julius
351			`dbg_chain = chain;`
352
353			`send_command_to_vpi(CMD_SET_DEBUG_CHAIN);`
354
355			`send_data_to_vpi(chain);`
356
357			`get_response_from_vpi();`
358
359			`current_chain = chain;`
360
361			`return DBG_ERR_OK;`
362			`}`
363
364			`/* writes a ctrl reg */`
365			`int dbg_ctrl(int reset, int stall)`
366			`{`
367
368			`debug("\n");`
369			`debug2("ctrl\n");`
370	46	julius
371			`if (DBG_CALLS)printf("dbg_ctrl: reset %d stall %d \n", reset, stall);`
372	40	julius
373			`dbg_set_chain(dbg_chain);`
374
375			`send_command_to_vpi(CMD_CPU_CTRL_WR);`
376
377			`//send_data_to_vpi(((reset & 0x1) \| ((stall&0x1)<<1)));`
378			`send_data_to_vpi(((stall & 0x1) \| ((reset&0x1)<<1)));`
379
380			`get_response_from_vpi();`
381
382			`return DBG_ERR_OK;`
383			`}`
384
385			`/* reads control register */`
386			`int dbg_ctrl_read(int reset, int stall)`
387			`{`
388
389			`uint32_t resp;`
390
391			`dbg_set_chain(dbg_chain);`
392
393			`debug("\n");`
394			`debug2("ctrl\n");`
395	46	julius
396			`if (DBG_CALLS)printf("dbg_ctrl_read\n");`
397	40	julius
398			`dbg_set_chain(dbg_chain);`
399
400			`send_command_to_vpi(CMD_CPU_CTRL_RD);`
401
402	397	julius	`get_word_from_vpi((uint32_t *)&resp);`
403	40	julius
404			`if (DBG_VPI) printf("rsp-rtl_sim: dbg_ctrl_read: 0x%.8x\n",resp);`
405
406			`get_response_from_vpi();`
407
408			`*reset = (int)(resp & 0x00000001);`
409
410			`*stall = (int)((resp >> 1) & 0x00000001);`
411
412			`return DBG_ERR_OK;`
413			`}`
414
415			`/* read a word from wishbone */`
416			`int dbg_wb_read32(uint32_t adr, uint32_t *data)`
417			`{`
418	46	julius	`if (DBG_CALLS)printf("dbg_wb_read32: adr 0x%.8x \n",adr);`
419	40	julius
420			`dbg_set_chain(DC_WISHBONE);`
421
422			`send_command_to_vpi(CMD_WB_RD32);`
423
424			`send_address_to_vpi(adr);`
425
426	397	julius	`get_word_from_vpi(data);`
427	40	julius
428			`get_response_from_vpi();`
429
430			`return 0;`
431			`}`
432
433	397	julius	`/* read a word from wishbone */`
434			`int dbg_wb_read8(uint32_t adr, uint8_t *data)`
435			`{`
436			`if (DBG_CALLS)printf("dbg_wb_read8: adr 0x%.8x \n",adr);`
437
438			`dbg_set_chain(DC_WISHBONE);`
439
440			`send_command_to_vpi(CMD_WB_RD8);`
441
442			`send_address_to_vpi(adr);`
443
444			`get_byte_from_vpi(data);`
445
446			`get_response_from_vpi();`
447
448			`return 0;`
449			`}`
450
451	40	julius	`/* write a word to wishbone */`
452			`int dbg_wb_write32(uint32_t adr, uint32_t data)`
453			`{`
454	46	julius
455			`if (DBG_CALLS)printf("dbg_wb_write32: adr 0x%.8x data 0x%.8x\n",adr, data);`
456
457			`dbg_set_chain(DC_WISHBONE);`
458
459			`send_command_to_vpi(CMD_WB_WR);`
460
461			`send_address_to_vpi(adr);`
462	40	julius
463	46	julius	`send_data_to_vpi(sizeof(data));`
464
465			`send_data_to_vpi(data);`
466
467			`get_response_from_vpi();`
468
469			`return 0;`
470			`}`
471
472			`/* write a hword to wishbone */`
473			`int dbg_wb_write16(uint32_t adr, uint16_t data)`
474			`{`
475
476			`if (DBG_CALLS)printf("dbg_wb_write16: adr 0x%.8x data 0x%.4x\n",adr, data);`
477
478	40	julius	`dbg_set_chain(DC_WISHBONE);`
479
480	46	julius	`send_command_to_vpi(CMD_WB_WR);`
481	40	julius
482			`send_address_to_vpi(adr);`
483
484	46	julius	`send_data_to_vpi(sizeof(data));`
485
486	40	julius	`send_data_to_vpi(data);`
487
488			`get_response_from_vpi();`
489
490			`return 0;`
491			`}`
492
493	46	julius	`/* write a word to wishbone */`
494			`int dbg_wb_write8(uint32_t adr, uint8_t data)`
495			`{`
496
497			`if (DBG_CALLS)printf("dbg_wb_write8: adr 0x%.8x data 0x%.2x\n",adr, data);`
498
499			`dbg_set_chain(DC_WISHBONE);`
500
501			`send_command_to_vpi(CMD_WB_WR);`
502
503			`send_address_to_vpi(adr);`
504
505			`send_data_to_vpi(sizeof(data));`
506
507			`send_data_to_vpi(data);`
508
509			`get_response_from_vpi();`
510
511			`return 0;`
512			`}`
513
514
515	40	julius	`/* read a block from wishbone */`
516			`int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len)`
517			`{`
518
519			`// len is in B Y T E S ! !`
520
521	46	julius	`if (DBG_VPI) printf("xbrsp-rtl_sim: block read len: %d from addr: 0x%.8x\n",len, adr);`
522	40	julius
523			`dbg_set_chain(DC_WISHBONE);`
524
525			`send_command_to_vpi(CMD_WB_BLOCK_RD32);`
526
527			`send_data_to_vpi(adr);`
528
529			`send_data_to_vpi(len);`
530
531			`get_block_data_from_vpi(len, data);`
532
533			`get_response_from_vpi();`
534
535			`return DBG_ERR_OK;`
536			`}`
537
538			`/* write a block to wishbone */`
539			`int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len)`
540			`{`
541	46	julius
542			`if (DBG_CALLS)printf("dbg_wb_block32: adr 0x%.8x len %d bytes\n",adr, len);`
543	40	julius
544			`dbg_set_chain(DC_WISHBONE);`
545
546			`send_command_to_vpi(CMD_WB_BLOCK_WR32);`
547
548			`send_data_to_vpi(adr);`
549
550			`send_data_to_vpi(len);`
551
552			`send_block_data_to_vpi(len, data);`
553
554			`get_response_from_vpi();`
555
556			`return DBG_ERR_OK;`
557			`}`
558
559			`/* read a register from cpu */`
560	49	julius	`int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length)`
561	40	julius	`{`
562	46	julius
563			`if (DBG_CALLS)printf("dbg_cpu0_read: adr 0x%.8x\n",adr);`
564	40	julius
565			`dbg_set_chain(DC_CPU0);`
566
567			`send_command_to_vpi(CMD_CPU_RD_REG);`
568
569			`send_address_to_vpi(adr);`
570	49	julius
571			`send_data_to_vpi(length); // Added 090901 --jb`
572
573	397	julius	`get_block_data_from_vpi(length, data); // changed 090901 --jb //get_word_from_vpi(data);`
574	40	julius
575			`get_response_from_vpi();`
576
577			`return 0;`
578
579			`}`
580
581			`/* write a cpu register */`
582	49	julius	`int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length)`
583	40	julius	`{`
584
585	46	julius	`if (DBG_CALLS)printf("dbg_cpu0_write: adr 0x%.8x\n",adr);`
586	40	julius
587			`dbg_set_chain(DC_CPU0);`
588
589			`send_command_to_vpi(CMD_CPU_WR_REG);`
590
591			`send_address_to_vpi(adr);`
592
593	49	julius	`send_data_to_vpi(length); // Added 090901 -- jb`
594
595			`send_block_data_to_vpi(length, data); // Added 090901 -- jb`
596	40	julius
597			`get_response_from_vpi();`
598
599			`return 0;`
600			`}`
601
602			`/* read a register from cpu */`
603			`int dbg_cpu1_read(uint32_t adr, uint32_t *data) {`
604			`/*`
605			`int err;`
606			`if ((err = dbg_set_chain(DC_CPU1))) return err;`
607			`if ((err = dbg_command(0x6, adr, 4))) return err;`
608			`if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;`
609			`data = ntohl(data);`
610			`*/`
611			`return DBG_ERR_OK;`
612			`}`
613
614			`/* write a cpu register */`
615			`int dbg_cpu1_write(uint32_t adr, uint32_t data) {`
616			`/*`
617			`int err;`
618			`data = ntohl(data);`
619			`if ((err = dbg_set_chain(DC_CPU1))) return err;`
620			`if ((err = dbg_command(0x2, adr, 4))) return err;`
621			`if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;`
622			`*/`
623			`return DBG_ERR_OK;`
624			`}`
625
626			`/* read a register from cpu module */`
627			`int dbg_cpu1_read_ctrl(uint32_t adr, unsigned char *data) {`
628			`/*`
629			`int err;`
630			`int r, s;`
631			`if ((err = dbg_set_chain(DC_CPU1))) return err;`
632			`if ((err = dbg_ctrl_read(&r, &s))) return err;`
633			`*data = (r << 1) \| s;`
634			`*/`
635			`return DBG_ERR_OK;`
636			`}`
637
638			`/* write a cpu module register */`
639			`int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data) {`
640			`int err;`
641			`if ((err = dbg_set_chain(DC_CPU0))) return err;`
642			`if ((err = dbg_ctrl(data & 2, data &1))) return err;`
643			`return DBG_ERR_OK;`
644			`}`
645
646			`/* read a register from cpu module */`
647			`int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data) {`
648			`int err;`
649			`int r, s;`
650			`if ((err = dbg_set_chain(DC_CPU0))) return err;`
651			`if ((err = dbg_ctrl_read(&r, &s))) return err;`
652			`*data = (r << 1) \| s;`
653			`return DBG_ERR_OK;`
654			`}`
655
656			`void dbg_test() {`
657			`int i;`
658			`uint32_t npc, ppc, r1, insn, result;`
659			`unsigned char stalled;`
660			`// uint32_t stalled;`
661			`unsigned char read_byte;`
662
663			`printf(" Stall or1k\n");`
664			`dbg_cpu0_write_ctrl(0, 0x01); // stall or1k`
665
666			`dbg_cpu0_read_ctrl(0, &stalled);`
667			`if (!(stalled & 0x1)) {`
668			`printf("\tor1k stall failed. read: 0x%x\n", stalled); // check stall or1k`
669			`//exit(1);`
670			`}`
671	49	julius
672			`/* Read NPC,PPC and SR regs, they are consecutive in CPU, at adr. 16, 17 and 18 */`
673			`uint32_t pcs_and_sr[3];`
674			`debug2(" Reading npc, ppc\n");`
675			`dbg_cpu0_read(16, (uint32_t )pcs_and_sr, 3 4);`
676	40	julius
677			`debug2(" Reading r1\n");`
678	49	julius	`dbg_cpu0_read(0x401, &r1, 4);`
679			`printf(" Read npc = %.8x ppc = %.8x r1 = %.8x\n",`
680			`pcs_and_sr[0], pcs_and_sr[2], r1);`
681	40	julius
682			`}`
683
684			`// Catch the term/int signals, close gdb then close ourselves`
685			`void catch_sigint(int sig_num)`
686			`{`
687			`gdb_close();`
688			`exit(0);`
689			`}`
690
691			`void dbg_client_detached(void)`
692			`{`
693			`// Send this message back to the sim`
694			`send_command_to_vpi(CMD_GDB_DETACH);`
695			`}`
696
697
698			`// This function is called after the fork in the VPI function.`
699
700			`void run_rsp_server(int portNum)`
701			`{`
702			`// Send commands to init and reset debug interface`
703			`dbg_reset();`
704			`// Stall and read NPC, PPC etc`
705			`dbg_test();`
706
707			`set_rsp_server_port(portNum);`
708
709			`// Install SIGINT/SIGTERM handlers, to close down gracefully`
710			`signal(SIGINT, catch_sigint);`
711			`signal(SIGTERM, catch_sigint);`
712
713			`if (DBG_ON) printf("rsp-rtl_sim: starting handle_rsp()\n");`
714			`// Now, start the RSP server. This should not return`
715			`handle_rsp ();`
716
717			`// Exit gracefully if it returns (shouldn't though)`
718			`exit(0);`
719
720			`}`
721
722