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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Blame information for rev 485

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1 408 julius
//////////////////////////////////////////////////////////////////////
2
///                                                               //// 
3
/// ORPSoC top for ordb1 board                                    ////
4
///                                                               ////
5
/// Instantiates modules, depending on ORPSoC defines file        ////
6
///                                                               ////
7
/// Julius Baxter, julius@opencores.org                           ////
8
///                                                               ////
9
//////////////////////////////////////////////////////////////////////
10
////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
12
////                                                              ////
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//// This source file may be used and distributed without         ////
14
//// restriction provided that this copyright statement is not    ////
15
//// removed from the file and that any derivative work contains  ////
16
//// the original copyright notice and the associated disclaimer. ////
17
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
19
//// and/or modify it under the terms of the GNU Lesser General   ////
20
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
22
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
25
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
26
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
27
//// PURPOSE.  See the GNU Lesser General Public License for more ////
28
//// details.                                                     ////
29
////                                                              ////
30
//// You should have received a copy of the GNU Lesser General    ////
31
//// Public License along with this source; if not, download it   ////
32
//// from http://www.opencores.org/lgpl.shtml                     ////
33
////                                                              ////
34
//////////////////////////////////////////////////////////////////////
35
 
36
`include "orpsoc-defines.v"
37
`include "synthesis-defines.v"
38
module orpsoc_top
39
  (
40
`ifdef JTAG_DEBUG
41
    tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i,
42
`endif
43
`ifdef VERSATILE_SDRAM
44
    sdram_ba_pad_o,sdram_a_pad_o,sdram_cs_n_pad_o, sdram_ras_pad_o,
45
    sdram_cas_pad_o, sdram_we_pad_o, sdram_dq_pad_io, sdram_dqm_pad_o,
46
    sdram_cke_pad_o,
47
`endif
48
`ifdef UART0
49
    uart0_srx_pad_i, uart0_stx_pad_o,
50
`endif
51
`ifdef SPI0
52
    spi0_sck_o, spi0_mosi_o, spi0_miso_i, spi0_hold_n_o, spi0_w_n_o,
53
 `ifdef SPI0_SLAVE_SELECTS
54
    spi0_ss_o,
55
 `endif
56
`endif
57
`ifdef SPI1
58
    spi1_sck_o, spi1_mosi_o, spi1_miso_i,
59
    `ifdef SPI1_SLAVE_SELECTS
60
    spi1_ss_o,
61
    `endif
62
`endif
63
`ifdef SPI2
64
    spi2_sck_o, spi2_mosi_o, spi2_miso_i,
65
    `ifdef SPI2_SLAVE_SELECTS
66
    spi2_ss_o,
67
    `endif
68
`endif
69
`ifdef I2C0
70
    i2c0_sda_io, i2c0_scl_io,
71
`endif
72
`ifdef I2C1
73
    i2c1_sda_io, i2c1_scl_io,
74
`endif
75
`ifdef I2C2
76
    i2c2_sda_io, i2c2_scl_io,
77
`endif
78
`ifdef I2C3
79
    i2c3_sda_io, i2c3_scl_io,
80
`endif
81
`ifdef USB0
82
    usb0dat_pad_i, usb0dat_pad_o, usb0ctrl_pad_o, usb0fullspeed_pad_o,
83
`endif
84
`ifdef USB1
85
    usb1dat_pad_i, usb1dat_pad_o, usb1ctrl_pad_o, usb1fullspeed_pad_o,
86
`endif
87
`ifdef GPIO0
88
    gpio0_io,
89
`endif
90
 
91
`ifdef ETH0
92
 `ifdef SMII0
93
    eth0_smii_sync_pad_o, eth0_smii_tx_pad_o, eth0_smii_rx_pad_i,
94
 `else
95
    eth0_tx_clk, eth0_tx_data, eth0_tx_en, eth0_tx_er,
96
    eth0_rx_clk, eth0_rx_data, eth0_dv, eth0_rx_er,
97
    eth0_col, eth0_crs,
98
 `endif
99
    eth0_mdc_pad_o, eth0_md_pad_io,
100
`endif //  `ifdef ETH0
101
`ifdef ETH0_PHY_RST
102
    eth0_rst_n_o,
103
`endif
104
`ifdef ETH_CLK
105
    eth_clk_pad_i,
106
`endif
107
 
108
    sys_clk_pad_i,
109
 
110
    rst_n_pad_i
111
 
112 439 julius
    )/* synthesis syn_global_buffers = 8; */;
113 408 julius
 
114
`include "orpsoc-params.v"
115
 
116
   input sys_clk_pad_i;
117
 
118
   input rst_n_pad_i;
119
 
120
`ifdef JTAG_DEBUG
121
   output tdo_pad_o;
122
   input  tms_pad_i;
123
   input  tck_pad_i;
124
   input  tdi_pad_i;
125
`endif
126
`ifdef VERSATILE_SDRAM
127
   output [1:0] sdram_ba_pad_o;
128
   output [12:0] sdram_a_pad_o;
129
   output        sdram_cs_n_pad_o;
130
   output        sdram_ras_pad_o;
131
   output        sdram_cas_pad_o;
132
   output        sdram_we_pad_o;
133
   inout [15:0]  sdram_dq_pad_io;
134
   output [1:0]  sdram_dqm_pad_o;
135
   output        sdram_cke_pad_o;
136
`endif
137
`ifdef UART0
138
   input         uart0_srx_pad_i;
139
   output        uart0_stx_pad_o;
140
`endif
141
`ifdef SPI0
142
   output        spi0_sck_o;
143
   output        spi0_mosi_o;
144
 `ifdef SPI0_SLAVE_SELECTS
145
   output [spi0_ss_width-1:0] spi0_ss_o;
146
 `endif
147
   output                     spi0_hold_n_o;
148
   output                     spi0_w_n_o;
149
   input                      spi0_miso_i;
150
`endif
151
`ifdef SPI1
152
   output                     spi1_sck_o;
153
   output                     spi1_mosi_o;
154
 `ifdef SPI1_SLAVE_SELECTS
155
   output [spi1_ss_width-1:0] spi1_ss_o;
156
 `endif
157
   input                      spi1_miso_i;
158
`endif
159
`ifdef SPI2
160
   output                     spi2_sck_o;
161
   output                     spi2_mosi_o;
162
 `ifdef SPI2_SLAVE_SELECTS
163
   output [spi2_ss_width-1:0] spi2_ss_o;
164
 `endif
165
   input                      spi2_miso_i;
166
`endif
167
`ifdef I2C0
168
   inout                      i2c0_sda_io, i2c0_scl_io;
169
`endif
170
`ifdef I2C1
171
   inout                      i2c1_sda_io, i2c1_scl_io;
172
`endif
173
`ifdef I2C2
174
   inout                      i2c2_sda_io, i2c2_scl_io;
175
`endif
176
`ifdef I2C3
177
   inout                      i2c3_sda_io, i2c3_scl_io;
178
`endif
179
`ifdef USB0
180
   input [1:0]                 usb0dat_pad_i;
181
   //   input                 usb0vbusdetect;
182
   output [1:0]        usb0dat_pad_o;
183
   output                     usb0ctrl_pad_o;
184
   output                     usb0fullspeed_pad_o;
185
`endif
186
`ifdef USB1
187
   input [1:0]                 usb1dat_pad_i;
188
   //   input                 usb1vbusdetect;
189
   output [1:0]        usb1dat_pad_o;
190
   output                     usb1ctrl_pad_o;
191
   output                     usb1fullspeed_pad_o;
192
`endif
193
`ifdef GPIO0
194
   inout [gpio0_io_width-1:0] gpio0_io;
195
`endif
196
`ifdef ETH0
197
 `ifdef SMII0
198
   output                     eth0_smii_sync_pad_o, eth0_smii_tx_pad_o;
199
   input                      eth0_smii_rx_pad_i;
200
 `else
201
   input                      eth0_tx_clk;
202
   output [3:0]        eth0_tx_data;
203
   output                     eth0_tx_en;
204
   output                     eth0_tx_er;
205
   input                      eth0_rx_clk;
206
   input [3:0]                 eth0_rx_data;
207
   input                      eth0_dv;
208
   input                      eth0_rx_er;
209
   input                      eth0_col;
210
   input                      eth0_crs;
211
 `endif // !`ifdef SMII0
212
   output                     eth0_mdc_pad_o;
213
   inout                      eth0_md_pad_io;
214
`endif //  `ifdef ETH0
215
`ifdef ETH_CLK
216
   input                      eth_clk_pad_i;
217
`endif
218
 
219
   ////////////////////////////////////////////////////////////////////////
220
   //
221
   // Clock and reset generation module
222
   // 
223
   ////////////////////////////////////////////////////////////////////////
224
 
225
   //
226
   // Wires
227
   //
228
   wire                       wb_clk, wb_rst;
229
   wire                       sdram_clk, sdram_rst;
230
   wire                       ddr2_if_clk, ddr2_if_rst;
231
   wire                       clk200;
232
   wire                       usb_clk;
233
   wire                       spw_clk;
234
   wire                       eth_smii_clk, eth_smii_rst;
235
   wire                       dbg_tck;
236
 
237
 
238
   clkgen clkgen0
239
     (
240
      .sys_clk_pad_i             (sys_clk_pad_i),
241
 
242
      .wb_clk_o                  (wb_clk),
243
      .wb_rst_o                  (wb_rst),
244
 
245
`ifdef JTAG_DEBUG
246
      .tck_pad_i                 (tck_pad_i),
247
      .dbg_tck_o                 (dbg_tck),
248
`endif
249
`ifdef VERSATILE_SDRAM
250
      .sdram_clk_o               (sdram_clk),
251
      .sdram_rst_o               (sdram_rst),
252
`endif
253
`ifdef ETH_CLK
254
      .eth_clk_pad_i             (eth_clk_pad_i),
255
      .eth_clk_o                 (eth_smii_clk),
256
      .eth_rst_o                 (eth_smii_rst),
257
`endif
258
`ifdef USB_CLK
259
      .usb_clk_o                 (usb_clk),
260
`endif
261
 
262
      // Asynchronous active low reset
263
      .rst_n_pad_i               (rst_n_pad_i)
264
      );
265
 
266
 
267
   ////////////////////////////////////////////////////////////////////////
268
   //
269
   // Arbiter
270
   // 
271
   ////////////////////////////////////////////////////////////////////////
272
 
273
   // Wire naming convention:
274
   // First: wishbone master or slave (wbm/wbs)
275
   // Second: Which bus it's on instruction or data (i/d)
276
   // Third: Between which module and the arbiter the wires are
277
   // Fourth: Signal name
278
   // Fifth: Direction relative to module (not bus/arbiter!)
279
   //        ie. wbm_d_or12_adr_o is address OUT from the or1200
280
 
281
   // OR1200 instruction bus wires
282
   wire [wb_aw-1:0]            wbm_i_or12_adr_o;
283
   wire [wb_dw-1:0]            wbm_i_or12_dat_o;
284
   wire [3:0]                  wbm_i_or12_sel_o;
285
   wire                       wbm_i_or12_we_o;
286
   wire                       wbm_i_or12_cyc_o;
287
   wire                       wbm_i_or12_stb_o;
288
   wire [2:0]                  wbm_i_or12_cti_o;
289
   wire [1:0]                  wbm_i_or12_bte_o;
290
 
291
   wire [wb_dw-1:0]            wbm_i_or12_dat_i;
292
   wire                       wbm_i_or12_ack_i;
293
   wire                       wbm_i_or12_err_i;
294
   wire                       wbm_i_or12_rty_i;
295
 
296
   // OR1200 data bus wires   
297
   wire [wb_aw-1:0]            wbm_d_or12_adr_o;
298
   wire [wb_dw-1:0]            wbm_d_or12_dat_o;
299
   wire [3:0]                  wbm_d_or12_sel_o;
300
   wire                       wbm_d_or12_we_o;
301
   wire                       wbm_d_or12_cyc_o;
302
   wire                       wbm_d_or12_stb_o;
303
   wire [2:0]                  wbm_d_or12_cti_o;
304
   wire [1:0]                  wbm_d_or12_bte_o;
305
 
306
   wire [wb_dw-1:0]            wbm_d_or12_dat_i;
307
   wire                       wbm_d_or12_ack_i;
308
   wire                       wbm_d_or12_err_i;
309
   wire                       wbm_d_or12_rty_i;
310
 
311
   // Debug interface bus wires   
312
   wire [wb_aw-1:0]            wbm_d_dbg_adr_o;
313
   wire [wb_dw-1:0]            wbm_d_dbg_dat_o;
314
   wire [3:0]                  wbm_d_dbg_sel_o;
315
   wire                       wbm_d_dbg_we_o;
316
   wire                       wbm_d_dbg_cyc_o;
317
   wire                       wbm_d_dbg_stb_o;
318
   wire [2:0]                  wbm_d_dbg_cti_o;
319
   wire [1:0]                  wbm_d_dbg_bte_o;
320
 
321
   wire [wb_dw-1:0]            wbm_d_dbg_dat_i;
322
   wire                       wbm_d_dbg_ack_i;
323
   wire                       wbm_d_dbg_err_i;
324
   wire                       wbm_d_dbg_rty_i;
325
 
326
   // Byte bus bridge master signals
327
   wire [wb_aw-1:0]            wbm_b_d_adr_o;
328
   wire [wb_dw-1:0]            wbm_b_d_dat_o;
329
   wire [3:0]                  wbm_b_d_sel_o;
330
   wire                       wbm_b_d_we_o;
331
   wire                       wbm_b_d_cyc_o;
332
   wire                       wbm_b_d_stb_o;
333
   wire [2:0]                  wbm_b_d_cti_o;
334
   wire [1:0]                  wbm_b_d_bte_o;
335
 
336
   wire [wb_dw-1:0]            wbm_b_d_dat_i;
337
   wire                       wbm_b_d_ack_i;
338
   wire                       wbm_b_d_err_i;
339
   wire                       wbm_b_d_rty_i;
340
 
341
   // Instruction bus slave wires //
342
 
343
   // rom0 instruction bus wires
344
   wire [31:0]                 wbs_i_rom0_adr_i;
345
   wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_i;
346
   wire [3:0]                        wbs_i_rom0_sel_i;
347
   wire                             wbs_i_rom0_we_i;
348
   wire                             wbs_i_rom0_cyc_i;
349
   wire                             wbs_i_rom0_stb_i;
350
   wire [2:0]                        wbs_i_rom0_cti_i;
351
   wire [1:0]                        wbs_i_rom0_bte_i;
352
   wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_o;
353
   wire                             wbs_i_rom0_ack_o;
354
   wire                             wbs_i_rom0_err_o;
355
   wire                             wbs_i_rom0_rty_o;
356
 
357
   // mc0 instruction bus wires
358
   wire [31:0]                       wbs_i_mc0_adr_i;
359
   wire [wbs_i_mc0_data_width-1:0]  wbs_i_mc0_dat_i;
360
   wire [3:0]                        wbs_i_mc0_sel_i;
361
   wire                             wbs_i_mc0_we_i;
362
   wire                             wbs_i_mc0_cyc_i;
363
   wire                             wbs_i_mc0_stb_i;
364
   wire [2:0]                        wbs_i_mc0_cti_i;
365
   wire [1:0]                        wbs_i_mc0_bte_i;
366
   wire [wbs_i_mc0_data_width-1:0]  wbs_i_mc0_dat_o;
367
   wire                             wbs_i_mc0_ack_o;
368
   wire                             wbs_i_mc0_err_o;
369
   wire                             wbs_i_mc0_rty_o;
370
 
371
   // Data bus slave wires //
372
 
373
   // mc0 data bus wires
374
   wire [31:0]                       wbs_d_mc0_adr_i;
375
   wire [wbs_d_mc0_data_width-1:0]  wbs_d_mc0_dat_i;
376
   wire [3:0]                        wbs_d_mc0_sel_i;
377
   wire                             wbs_d_mc0_we_i;
378
   wire                             wbs_d_mc0_cyc_i;
379
   wire                             wbs_d_mc0_stb_i;
380
   wire [2:0]                        wbs_d_mc0_cti_i;
381
   wire [1:0]                        wbs_d_mc0_bte_i;
382
   wire [wbs_d_mc0_data_width-1:0]  wbs_d_mc0_dat_o;
383
   wire                             wbs_d_mc0_ack_o;
384
   wire                             wbs_d_mc0_err_o;
385
   wire                             wbs_d_mc0_rty_o;
386
 
387
   // i2c0 wires
388
   wire [31:0]                       wbs_d_i2c0_adr_i;
389
   wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i;
390
   wire [3:0]                        wbs_d_i2c0_sel_i;
391
   wire                             wbs_d_i2c0_we_i;
392
   wire                             wbs_d_i2c0_cyc_i;
393
   wire                             wbs_d_i2c0_stb_i;
394
   wire [2:0]                        wbs_d_i2c0_cti_i;
395
   wire [1:0]                        wbs_d_i2c0_bte_i;
396
   wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o;
397
   wire                             wbs_d_i2c0_ack_o;
398
   wire                             wbs_d_i2c0_err_o;
399
   wire                             wbs_d_i2c0_rty_o;
400
 
401
   // i2c1 wires
402
   wire [31:0]                       wbs_d_i2c1_adr_i;
403
   wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i;
404
   wire [3:0]                        wbs_d_i2c1_sel_i;
405
   wire                             wbs_d_i2c1_we_i;
406
   wire                             wbs_d_i2c1_cyc_i;
407
   wire                             wbs_d_i2c1_stb_i;
408
   wire [2:0]                        wbs_d_i2c1_cti_i;
409
   wire [1:0]                        wbs_d_i2c1_bte_i;
410
   wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o;
411
   wire                             wbs_d_i2c1_ack_o;
412
   wire                             wbs_d_i2c1_err_o;
413
   wire                             wbs_d_i2c1_rty_o;
414
 
415
   // i2c2 wires
416
   wire [31:0]                       wbs_d_i2c2_adr_i;
417
   wire [wbs_d_i2c2_data_width-1:0] wbs_d_i2c2_dat_i;
418
   wire [3:0]                        wbs_d_i2c2_sel_i;
419
   wire                             wbs_d_i2c2_we_i;
420
   wire                             wbs_d_i2c2_cyc_i;
421
   wire                             wbs_d_i2c2_stb_i;
422
   wire [2:0]                        wbs_d_i2c2_cti_i;
423
   wire [1:0]                        wbs_d_i2c2_bte_i;
424
   wire [wbs_d_i2c2_data_width-1:0] wbs_d_i2c2_dat_o;
425
   wire                             wbs_d_i2c2_ack_o;
426
   wire                             wbs_d_i2c2_err_o;
427
   wire                             wbs_d_i2c2_rty_o;
428
 
429
   // i2c3 wires
430
   wire [31:0]                       wbs_d_i2c3_adr_i;
431
   wire [wbs_d_i2c3_data_width-1:0] wbs_d_i2c3_dat_i;
432
   wire [3:0]                        wbs_d_i2c3_sel_i;
433
   wire                             wbs_d_i2c3_we_i;
434
   wire                             wbs_d_i2c3_cyc_i;
435
   wire                             wbs_d_i2c3_stb_i;
436
   wire [2:0]                        wbs_d_i2c3_cti_i;
437
   wire [1:0]                        wbs_d_i2c3_bte_i;
438
   wire [wbs_d_i2c3_data_width-1:0] wbs_d_i2c3_dat_o;
439
   wire                             wbs_d_i2c3_ack_o;
440
   wire                             wbs_d_i2c3_err_o;
441
   wire                             wbs_d_i2c3_rty_o;
442
 
443
   // spi0 wires
444
   wire [31:0]                       wbs_d_spi0_adr_i;
445
   wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i;
446
   wire [3:0]                        wbs_d_spi0_sel_i;
447
   wire                             wbs_d_spi0_we_i;
448
   wire                             wbs_d_spi0_cyc_i;
449
   wire                             wbs_d_spi0_stb_i;
450
   wire [2:0]                        wbs_d_spi0_cti_i;
451
   wire [1:0]                        wbs_d_spi0_bte_i;
452
   wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o;
453
   wire                             wbs_d_spi0_ack_o;
454
   wire                             wbs_d_spi0_err_o;
455
   wire                             wbs_d_spi0_rty_o;
456
 
457
   // spi1 wires
458
   wire [31:0]                       wbs_d_spi1_adr_i;
459
   wire [wbs_d_spi1_data_width-1:0] wbs_d_spi1_dat_i;
460
   wire [3:0]                        wbs_d_spi1_sel_i;
461
   wire                             wbs_d_spi1_we_i;
462
   wire                             wbs_d_spi1_cyc_i;
463
   wire                             wbs_d_spi1_stb_i;
464
   wire [2:0]                        wbs_d_spi1_cti_i;
465
   wire [1:0]                        wbs_d_spi1_bte_i;
466
   wire [wbs_d_spi1_data_width-1:0] wbs_d_spi1_dat_o;
467
   wire                             wbs_d_spi1_ack_o;
468
   wire                             wbs_d_spi1_err_o;
469
   wire                             wbs_d_spi1_rty_o;
470
 
471
   // spi2 wires
472
   wire [31:0]                       wbs_d_spi2_adr_i;
473
   wire [wbs_d_spi2_data_width-1:0] wbs_d_spi2_dat_i;
474
   wire [3:0]                        wbs_d_spi2_sel_i;
475
   wire                             wbs_d_spi2_we_i;
476
   wire                             wbs_d_spi2_cyc_i;
477
   wire                             wbs_d_spi2_stb_i;
478
   wire [2:0]                        wbs_d_spi2_cti_i;
479
   wire [1:0]                        wbs_d_spi2_bte_i;
480
   wire [wbs_d_spi2_data_width-1:0] wbs_d_spi2_dat_o;
481
   wire                             wbs_d_spi2_ack_o;
482
   wire                             wbs_d_spi2_err_o;
483
   wire                             wbs_d_spi2_rty_o;
484
 
485
   // uart0 wires
486
   wire [31:0]                        wbs_d_uart0_adr_i;
487
   wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i;
488
   wire [3:0]                         wbs_d_uart0_sel_i;
489
   wire                              wbs_d_uart0_we_i;
490
   wire                              wbs_d_uart0_cyc_i;
491
   wire                              wbs_d_uart0_stb_i;
492
   wire [2:0]                         wbs_d_uart0_cti_i;
493
   wire [1:0]                         wbs_d_uart0_bte_i;
494
   wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o;
495
   wire                              wbs_d_uart0_ack_o;
496
   wire                              wbs_d_uart0_err_o;
497
   wire                              wbs_d_uart0_rty_o;
498
 
499
   // usb0 wires
500
   wire [31:0]                        wbs_d_usb0_adr_i;
501
   wire [wbs_d_usb0_data_width-1:0]  wbs_d_usb0_dat_i;
502
   wire [3:0]                         wbs_d_usb0_sel_i;
503
   wire                              wbs_d_usb0_we_i;
504
   wire                              wbs_d_usb0_cyc_i;
505
   wire                              wbs_d_usb0_stb_i;
506
   wire [2:0]                         wbs_d_usb0_cti_i;
507
   wire [1:0]                         wbs_d_usb0_bte_i;
508
   wire [wbs_d_usb0_data_width-1:0]  wbs_d_usb0_dat_o;
509
   wire                              wbs_d_usb0_ack_o;
510
   wire                              wbs_d_usb0_err_o;
511
   wire                              wbs_d_usb0_rty_o;
512
 
513
   // usb1 wires
514
   wire [31:0]                        wbs_d_usb1_adr_i;
515
   wire [wbs_d_usb1_data_width-1:0]  wbs_d_usb1_dat_i;
516
   wire [3:0]                         wbs_d_usb1_sel_i;
517
   wire                              wbs_d_usb1_we_i;
518
   wire                              wbs_d_usb1_cyc_i;
519
   wire                              wbs_d_usb1_stb_i;
520
   wire [2:0]                         wbs_d_usb1_cti_i;
521
   wire [1:0]                         wbs_d_usb1_bte_i;
522
   wire [wbs_d_usb1_data_width-1:0]  wbs_d_usb1_dat_o;
523
   wire                              wbs_d_usb1_ack_o;
524
   wire                              wbs_d_usb1_err_o;
525
   wire                              wbs_d_usb1_rty_o;
526
 
527
   // gpio0 wires
528
   wire [31:0]                        wbs_d_gpio0_adr_i;
529
   wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i;
530
   wire [3:0]                         wbs_d_gpio0_sel_i;
531
   wire                              wbs_d_gpio0_we_i;
532
   wire                              wbs_d_gpio0_cyc_i;
533
   wire                              wbs_d_gpio0_stb_i;
534
   wire [2:0]                         wbs_d_gpio0_cti_i;
535
   wire [1:0]                         wbs_d_gpio0_bte_i;
536
   wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o;
537
   wire                              wbs_d_gpio0_ack_o;
538
   wire                              wbs_d_gpio0_err_o;
539
   wire                              wbs_d_gpio0_rty_o;
540
 
541
   // flashROM wires
542
   wire [31:0]                             wbs_d_flashrom_adr_i;
543
   wire [flashrom_wb_data_width-1:0]       wbs_d_flashrom_dat_i;
544
   wire [3:0]                              wbs_d_flashrom_sel_i;
545
   wire                                   wbs_d_flashrom_we_i;
546
   wire                                   wbs_d_flashrom_cyc_i;
547
   wire                                   wbs_d_flashrom_stb_i;
548
   wire [2:0]                              wbs_d_flashrom_cti_i;
549
   wire [1:0]                              wbs_d_flashrom_bte_i;
550
   wire [flashrom_wb_data_width-1:0]       wbs_d_flashrom_dat_o;
551
   wire                                   wbs_d_flashrom_ack_o;
552
   wire                                   wbs_d_flashrom_err_o;
553
   wire                                   wbs_d_flashrom_rty_o;
554
 
555
   // eth0 slave wires
556
   wire [31:0]                             wbs_d_eth0_adr_i;
557
   wire [wbs_d_eth0_data_width-1:0]        wbs_d_eth0_dat_i;
558
   wire [3:0]                              wbs_d_eth0_sel_i;
559
   wire                                   wbs_d_eth0_we_i;
560
   wire                                   wbs_d_eth0_cyc_i;
561
   wire                                   wbs_d_eth0_stb_i;
562
   wire [2:0]                              wbs_d_eth0_cti_i;
563
   wire [1:0]                              wbs_d_eth0_bte_i;
564
   wire [wbs_d_eth0_data_width-1:0]        wbs_d_eth0_dat_o;
565
   wire                                   wbs_d_eth0_ack_o;
566
   wire                                   wbs_d_eth0_err_o;
567
   wire                                   wbs_d_eth0_rty_o;
568
   // eth0 master wires
569
   wire [wbm_eth0_addr_width-1:0]          wbm_eth0_adr_o;
570
   wire [wbm_eth0_data_width-1:0]          wbm_eth0_dat_o;
571
   wire [3:0]                              wbm_eth0_sel_o;
572
   wire                                   wbm_eth0_we_o;
573
   wire                                   wbm_eth0_cyc_o;
574
   wire                                   wbm_eth0_stb_o;
575
   wire [2:0]                              wbm_eth0_cti_o;
576
   wire [1:0]                              wbm_eth0_bte_o;
577
   wire [wbm_eth0_data_width-1:0]         wbm_eth0_dat_i;
578
   wire                                   wbm_eth0_ack_i;
579
   wire                                   wbm_eth0_err_i;
580
   wire                                   wbm_eth0_rty_i;
581
 
582
 
583
 
584
   //
585
   // Wishbone instruction bus arbiter
586
   //
587
 
588
   arbiter_ibus arbiter_ibus0
589
     (
590
      // Instruction Bus Master
591
      // Inputs to arbiter from master
592
      .wbm_adr_o                        (wbm_i_or12_adr_o),
593
      .wbm_dat_o                        (wbm_i_or12_dat_o),
594
      .wbm_sel_o                        (wbm_i_or12_sel_o),
595
      .wbm_we_o                         (wbm_i_or12_we_o),
596
      .wbm_cyc_o                        (wbm_i_or12_cyc_o),
597
      .wbm_stb_o                        (wbm_i_or12_stb_o),
598
      .wbm_cti_o                        (wbm_i_or12_cti_o),
599
      .wbm_bte_o                        (wbm_i_or12_bte_o),
600
      // Outputs to master from arbiter
601
      .wbm_dat_i                        (wbm_i_or12_dat_i),
602
      .wbm_ack_i                        (wbm_i_or12_ack_i),
603
      .wbm_err_i                        (wbm_i_or12_err_i),
604
      .wbm_rty_i                        (wbm_i_or12_rty_i),
605
 
606
      // Slave 0
607
      // Inputs to slave from arbiter
608
      .wbs0_adr_i                       (wbs_i_rom0_adr_i),
609
      .wbs0_dat_i                       (wbs_i_rom0_dat_i),
610
      .wbs0_sel_i                       (wbs_i_rom0_sel_i),
611
      .wbs0_we_i                        (wbs_i_rom0_we_i),
612
      .wbs0_cyc_i                       (wbs_i_rom0_cyc_i),
613
      .wbs0_stb_i                       (wbs_i_rom0_stb_i),
614
      .wbs0_cti_i                       (wbs_i_rom0_cti_i),
615
      .wbs0_bte_i                       (wbs_i_rom0_bte_i),
616
      // Outputs from slave to arbiter      
617
      .wbs0_dat_o                       (wbs_i_rom0_dat_o),
618
      .wbs0_ack_o                       (wbs_i_rom0_ack_o),
619
      .wbs0_err_o                       (wbs_i_rom0_err_o),
620
      .wbs0_rty_o                       (wbs_i_rom0_rty_o),
621
 
622
      // Slave 1
623
      // Inputs to slave from arbiter
624
      .wbs1_adr_i                       (wbs_i_mc0_adr_i),
625
      .wbs1_dat_i                       (wbs_i_mc0_dat_i),
626
      .wbs1_sel_i                       (wbs_i_mc0_sel_i),
627
      .wbs1_we_i                        (wbs_i_mc0_we_i),
628
      .wbs1_cyc_i                       (wbs_i_mc0_cyc_i),
629
      .wbs1_stb_i                       (wbs_i_mc0_stb_i),
630
      .wbs1_cti_i                       (wbs_i_mc0_cti_i),
631
      .wbs1_bte_i                       (wbs_i_mc0_bte_i),
632
      // Outputs from slave to arbiter
633
      .wbs1_dat_o                       (wbs_i_mc0_dat_o),
634
      .wbs1_ack_o                       (wbs_i_mc0_ack_o),
635
      .wbs1_err_o                       (wbs_i_mc0_err_o),
636
      .wbs1_rty_o                       (wbs_i_mc0_rty_o),
637
 
638
      // Clock, reset inputs
639
      .wb_clk                           (wb_clk),
640
      .wb_rst                           (wb_rst));
641
 
642
   defparam arbiter_ibus0.wb_addr_match_width = ibus_arb_addr_match_width;
643
 
644
   defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // FLASH ROM
645
   defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // Main memory
646
 
647
   //
648
   // Wishbone data bus arbiter
649
   //
650
 
651
   arbiter_dbus arbiter_dbus0
652
     (
653
      // Master 0
654
      // Inputs to arbiter from master
655
      .wbm0_adr_o                       (wbm_d_or12_adr_o),
656
      .wbm0_dat_o                       (wbm_d_or12_dat_o),
657
      .wbm0_sel_o                       (wbm_d_or12_sel_o),
658
      .wbm0_we_o                        (wbm_d_or12_we_o),
659
      .wbm0_cyc_o                       (wbm_d_or12_cyc_o),
660
      .wbm0_stb_o                       (wbm_d_or12_stb_o),
661
      .wbm0_cti_o                       (wbm_d_or12_cti_o),
662
      .wbm0_bte_o                       (wbm_d_or12_bte_o),
663
      // Outputs to master from arbiter
664
      .wbm0_dat_i                       (wbm_d_or12_dat_i),
665
      .wbm0_ack_i                       (wbm_d_or12_ack_i),
666
      .wbm0_err_i                       (wbm_d_or12_err_i),
667
      .wbm0_rty_i                       (wbm_d_or12_rty_i),
668
 
669
      // Master 0
670
      // Inputs to arbiter from master
671
      .wbm1_adr_o                       (wbm_d_dbg_adr_o),
672
      .wbm1_dat_o                       (wbm_d_dbg_dat_o),
673
      .wbm1_we_o                        (wbm_d_dbg_we_o),
674
      .wbm1_cyc_o                       (wbm_d_dbg_cyc_o),
675
      .wbm1_sel_o                       (wbm_d_dbg_sel_o),
676
      .wbm1_stb_o                       (wbm_d_dbg_stb_o),
677
      .wbm1_cti_o                       (wbm_d_dbg_cti_o),
678
      .wbm1_bte_o                       (wbm_d_dbg_bte_o),
679
      // Outputs to master from arbiter      
680
      .wbm1_dat_i                       (wbm_d_dbg_dat_i),
681
      .wbm1_ack_i                       (wbm_d_dbg_ack_i),
682
      .wbm1_err_i                       (wbm_d_dbg_err_i),
683
      .wbm1_rty_i                       (wbm_d_dbg_rty_i),
684
 
685
      // Slaves
686
 
687
      .wbs0_adr_i                       (wbs_d_mc0_adr_i),
688
      .wbs0_dat_i                       (wbs_d_mc0_dat_i),
689
      .wbs0_sel_i                       (wbs_d_mc0_sel_i),
690
      .wbs0_we_i                        (wbs_d_mc0_we_i),
691
      .wbs0_cyc_i                       (wbs_d_mc0_cyc_i),
692
      .wbs0_stb_i                       (wbs_d_mc0_stb_i),
693
      .wbs0_cti_i                       (wbs_d_mc0_cti_i),
694
      .wbs0_bte_i                       (wbs_d_mc0_bte_i),
695
      .wbs0_dat_o                       (wbs_d_mc0_dat_o),
696
      .wbs0_ack_o                       (wbs_d_mc0_ack_o),
697
      .wbs0_err_o                       (wbs_d_mc0_err_o),
698
      .wbs0_rty_o                       (wbs_d_mc0_rty_o),
699
 
700
      .wbs1_adr_i                       (wbs_d_eth0_adr_i),
701
      .wbs1_dat_i                       (wbs_d_eth0_dat_i),
702
      .wbs1_sel_i                       (wbs_d_eth0_sel_i),
703
      .wbs1_we_i                        (wbs_d_eth0_we_i),
704
      .wbs1_cyc_i                       (wbs_d_eth0_cyc_i),
705
      .wbs1_stb_i                       (wbs_d_eth0_stb_i),
706
      .wbs1_cti_i                       (wbs_d_eth0_cti_i),
707
      .wbs1_bte_i                       (wbs_d_eth0_bte_i),
708
      .wbs1_dat_o                       (wbs_d_eth0_dat_o),
709
      .wbs1_ack_o                       (wbs_d_eth0_ack_o),
710
      .wbs1_err_o                       (wbs_d_eth0_err_o),
711
      .wbs1_rty_o                       (wbs_d_eth0_rty_o),
712
 
713
      .wbs2_adr_i                       (wbm_b_d_adr_o),
714
      .wbs2_dat_i                       (wbm_b_d_dat_o),
715
      .wbs2_sel_i                       (wbm_b_d_sel_o),
716
      .wbs2_we_i                        (wbm_b_d_we_o),
717
      .wbs2_cyc_i                       (wbm_b_d_cyc_o),
718
      .wbs2_stb_i                       (wbm_b_d_stb_o),
719
      .wbs2_cti_i                       (wbm_b_d_cti_o),
720
      .wbs2_bte_i                       (wbm_b_d_bte_o),
721
      .wbs2_dat_o                       (wbm_b_d_dat_i),
722
      .wbs2_ack_o                       (wbm_b_d_ack_i),
723
      .wbs2_err_o                       (wbm_b_d_err_i),
724
      .wbs2_rty_o                       (wbm_b_d_rty_i),
725
 
726
      // Clock, reset inputs
727
      .wb_clk                   (wb_clk),
728
      .wb_rst                   (wb_rst));
729
 
730
   // These settings are from top level params file
731
   defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width;
732
   defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;
733
   defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr;
734
   defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;
735
 
736
   //
737
   // Wishbone byte-wide bus arbiter
738
   //   
739
 
740
   arbiter_bytebus arbiter_bytebus0
741
     (
742
 
743
      // Master 0
744
      // Inputs to arbiter from master
745
      .wbm0_adr_o                       (wbm_b_d_adr_o),
746
      .wbm0_dat_o                       (wbm_b_d_dat_o),
747
      .wbm0_sel_o                       (wbm_b_d_sel_o),
748
      .wbm0_we_o                        (wbm_b_d_we_o),
749
      .wbm0_cyc_o                       (wbm_b_d_cyc_o),
750
      .wbm0_stb_o                       (wbm_b_d_stb_o),
751
      .wbm0_cti_o                       (wbm_b_d_cti_o),
752
      .wbm0_bte_o                       (wbm_b_d_bte_o),
753
      // Outputs to master from arbiter
754
      .wbm0_dat_i                       (wbm_b_d_dat_i),
755
      .wbm0_ack_i                       (wbm_b_d_ack_i),
756
      .wbm0_err_i                       (wbm_b_d_err_i),
757
      .wbm0_rty_i                       (wbm_b_d_rty_i),
758
 
759
      // Byte bus slaves
760
 
761
      .wbs0_adr_i                       (wbs_d_uart0_adr_i),
762
      .wbs0_dat_i                       (wbs_d_uart0_dat_i),
763
      .wbs0_we_i                        (wbs_d_uart0_we_i),
764
      .wbs0_cyc_i                       (wbs_d_uart0_cyc_i),
765
      .wbs0_stb_i                       (wbs_d_uart0_stb_i),
766
      .wbs0_cti_i                       (wbs_d_uart0_cti_i),
767
      .wbs0_bte_i                       (wbs_d_uart0_bte_i),
768
      .wbs0_dat_o                       (wbs_d_uart0_dat_o),
769
      .wbs0_ack_o                       (wbs_d_uart0_ack_o),
770
      .wbs0_err_o                       (wbs_d_uart0_err_o),
771
      .wbs0_rty_o                       (wbs_d_uart0_rty_o),
772
 
773
      .wbs1_adr_i                       (wbs_d_gpio0_adr_i),
774
      .wbs1_dat_i                       (wbs_d_gpio0_dat_i),
775
      .wbs1_we_i                        (wbs_d_gpio0_we_i),
776
      .wbs1_cyc_i                       (wbs_d_gpio0_cyc_i),
777
      .wbs1_stb_i                       (wbs_d_gpio0_stb_i),
778
      .wbs1_cti_i                       (wbs_d_gpio0_cti_i),
779
      .wbs1_bte_i                       (wbs_d_gpio0_bte_i),
780
      .wbs1_dat_o                       (wbs_d_gpio0_dat_o),
781
      .wbs1_ack_o                       (wbs_d_gpio0_ack_o),
782
      .wbs1_err_o                       (wbs_d_gpio0_err_o),
783
      .wbs1_rty_o                       (wbs_d_gpio0_rty_o),
784
 
785
      .wbs2_adr_i                       (wbs_d_usb0_adr_i),
786
      .wbs2_dat_i                       (wbs_d_usb0_dat_i),
787
      .wbs2_we_i                        (wbs_d_usb0_we_i),
788
      .wbs2_cyc_i                       (wbs_d_usb0_cyc_i),
789
      .wbs2_stb_i                       (wbs_d_usb0_stb_i),
790
      .wbs2_cti_i                       (wbs_d_usb0_cti_i),
791
      .wbs2_bte_i                       (wbs_d_usb0_bte_i),
792
      .wbs2_dat_o                       (wbs_d_usb0_dat_o),
793
      .wbs2_ack_o                       (wbs_d_usb0_ack_o),
794
      .wbs2_err_o                       (wbs_d_usb0_err_o),
795
      .wbs2_rty_o                       (wbs_d_usb0_rty_o),
796
 
797
      .wbs3_adr_i                       (wbs_d_i2c0_adr_i),
798
      .wbs3_dat_i                       (wbs_d_i2c0_dat_i),
799
      .wbs3_we_i                        (wbs_d_i2c0_we_i),
800
      .wbs3_cyc_i                       (wbs_d_i2c0_cyc_i),
801
      .wbs3_stb_i                       (wbs_d_i2c0_stb_i),
802
      .wbs3_cti_i                       (wbs_d_i2c0_cti_i),
803
      .wbs3_bte_i                       (wbs_d_i2c0_bte_i),
804
      .wbs3_dat_o                       (wbs_d_i2c0_dat_o),
805
      .wbs3_ack_o                       (wbs_d_i2c0_ack_o),
806
      .wbs3_err_o                       (wbs_d_i2c0_err_o),
807
      .wbs3_rty_o                       (wbs_d_i2c0_rty_o),
808
 
809
      .wbs4_adr_i                       (wbs_d_i2c1_adr_i),
810
      .wbs4_dat_i                       (wbs_d_i2c1_dat_i),
811
      .wbs4_we_i                        (wbs_d_i2c1_we_i),
812
      .wbs4_cyc_i                       (wbs_d_i2c1_cyc_i),
813
      .wbs4_stb_i                       (wbs_d_i2c1_stb_i),
814
      .wbs4_cti_i                       (wbs_d_i2c1_cti_i),
815
      .wbs4_bte_i                       (wbs_d_i2c1_bte_i),
816
      .wbs4_dat_o                       (wbs_d_i2c1_dat_o),
817
      .wbs4_ack_o                       (wbs_d_i2c1_ack_o),
818
      .wbs4_err_o                       (wbs_d_i2c1_err_o),
819
      .wbs4_rty_o                       (wbs_d_i2c1_rty_o),
820
 
821
      .wbs5_adr_i                       (wbs_d_i2c2_adr_i),
822
      .wbs5_dat_i                       (wbs_d_i2c2_dat_i),
823
      .wbs5_we_i                        (wbs_d_i2c2_we_i),
824
      .wbs5_cyc_i                       (wbs_d_i2c2_cyc_i),
825
      .wbs5_stb_i                       (wbs_d_i2c2_stb_i),
826
      .wbs5_cti_i                       (wbs_d_i2c2_cti_i),
827
      .wbs5_bte_i                       (wbs_d_i2c2_bte_i),
828
      .wbs5_dat_o                       (wbs_d_i2c2_dat_o),
829
      .wbs5_ack_o                       (wbs_d_i2c2_ack_o),
830
      .wbs5_err_o                       (wbs_d_i2c2_err_o),
831
      .wbs5_rty_o                       (wbs_d_i2c2_rty_o),
832
 
833
      .wbs6_adr_i                       (wbs_d_i2c3_adr_i),
834
      .wbs6_dat_i                       (wbs_d_i2c3_dat_i),
835
      .wbs6_we_i                        (wbs_d_i2c3_we_i),
836
      .wbs6_cyc_i                       (wbs_d_i2c3_cyc_i),
837
      .wbs6_stb_i                       (wbs_d_i2c3_stb_i),
838
      .wbs6_cti_i                       (wbs_d_i2c3_cti_i),
839
      .wbs6_bte_i                       (wbs_d_i2c3_bte_i),
840
      .wbs6_dat_o                       (wbs_d_i2c3_dat_o),
841
      .wbs6_ack_o                       (wbs_d_i2c3_ack_o),
842
      .wbs6_err_o                       (wbs_d_i2c3_err_o),
843
      .wbs6_rty_o                       (wbs_d_i2c3_rty_o),
844
 
845
      .wbs7_adr_i                       (wbs_d_spi0_adr_i),
846
      .wbs7_dat_i                       (wbs_d_spi0_dat_i),
847
      .wbs7_we_i                        (wbs_d_spi0_we_i),
848
      .wbs7_cyc_i                       (wbs_d_spi0_cyc_i),
849
      .wbs7_stb_i                       (wbs_d_spi0_stb_i),
850
      .wbs7_cti_i                       (wbs_d_spi0_cti_i),
851
      .wbs7_bte_i                       (wbs_d_spi0_bte_i),
852
      .wbs7_dat_o                       (wbs_d_spi0_dat_o),
853
      .wbs7_ack_o                       (wbs_d_spi0_ack_o),
854
      .wbs7_err_o                       (wbs_d_spi0_err_o),
855
      .wbs7_rty_o                       (wbs_d_spi0_rty_o),
856
 
857
      .wbs8_adr_i                       (wbs_d_spi1_adr_i),
858
      .wbs8_dat_i                       (wbs_d_spi1_dat_i),
859
      .wbs8_we_i                        (wbs_d_spi1_we_i),
860
      .wbs8_cyc_i                       (wbs_d_spi1_cyc_i),
861
      .wbs8_stb_i                       (wbs_d_spi1_stb_i),
862
      .wbs8_cti_i                       (wbs_d_spi1_cti_i),
863
      .wbs8_bte_i                       (wbs_d_spi1_bte_i),
864
      .wbs8_dat_o                       (wbs_d_spi1_dat_o),
865
      .wbs8_ack_o                       (wbs_d_spi1_ack_o),
866
      .wbs8_err_o                       (wbs_d_spi1_err_o),
867
      .wbs8_rty_o                       (wbs_d_spi1_rty_o),
868
 
869
      .wbs9_adr_i                       (wbs_d_spi2_adr_i),
870
      .wbs9_dat_i                       (wbs_d_spi2_dat_i),
871
      .wbs9_we_i                        (wbs_d_spi2_we_i),
872
      .wbs9_cyc_i                       (wbs_d_spi2_cyc_i),
873
      .wbs9_stb_i                       (wbs_d_spi2_stb_i),
874
      .wbs9_cti_i                       (wbs_d_spi2_cti_i),
875
      .wbs9_bte_i                       (wbs_d_spi2_bte_i),
876
      .wbs9_dat_o                       (wbs_d_spi2_dat_o),
877
      .wbs9_ack_o                       (wbs_d_spi2_ack_o),
878
      .wbs9_err_o                       (wbs_d_spi2_err_o),
879
      .wbs9_rty_o                       (wbs_d_spi2_rty_o),
880
 
881
      .wbs10_adr_i                      (wbs_d_flashrom_adr_i),
882
      .wbs10_dat_i                      (wbs_d_flashrom_dat_i),
883
      .wbs10_we_i                       (wbs_d_flashrom_we_i),
884
      .wbs10_cyc_i                      (wbs_d_flashrom_cyc_i),
885
      .wbs10_stb_i                      (wbs_d_flashrom_stb_i),
886
      .wbs10_cti_i                      (wbs_d_flashrom_cti_i),
887
      .wbs10_bte_i                      (wbs_d_flashrom_bte_i),
888
      .wbs10_dat_o                      (wbs_d_flashrom_dat_o),
889
      .wbs10_ack_o                      (wbs_d_flashrom_ack_o),
890
      .wbs10_err_o                      (wbs_d_flashrom_err_o),
891
      .wbs10_rty_o                      (wbs_d_flashrom_rty_o),
892
 
893
      .wbs11_adr_i                      (wbs_d_usb1_adr_i),
894
      .wbs11_dat_i                      (wbs_d_usb1_dat_i),
895
      .wbs11_we_i                       (wbs_d_usb1_we_i),
896
      .wbs11_cyc_i                      (wbs_d_usb1_cyc_i),
897
      .wbs11_stb_i                      (wbs_d_usb1_stb_i),
898
      .wbs11_cti_i                      (wbs_d_usb1_cti_i),
899
      .wbs11_bte_i                      (wbs_d_usb1_bte_i),
900
      .wbs11_dat_o                      (wbs_d_usb1_dat_o),
901
      .wbs11_ack_o                      (wbs_d_usb1_ack_o),
902
      .wbs11_err_o                      (wbs_d_usb1_err_o),
903
      .wbs11_rty_o                      (wbs_d_usb1_rty_o),
904
 
905
      // Clock, reset inputs
906
      .wb_clk                   (wb_clk),
907
      .wb_rst                   (wb_rst));
908
 
909
   defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
910
   defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves;
911
 
912
   defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr;
913
   defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr;
914
   defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr;
915
   defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr;
916
   defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr;
917
   defparam arbiter_bytebus0.slave5_adr = bbus_arb_slave5_adr;
918
   defparam arbiter_bytebus0.slave6_adr = bbus_arb_slave6_adr;
919
   defparam arbiter_bytebus0.slave7_adr = bbus_arb_slave7_adr;
920
   defparam arbiter_bytebus0.slave8_adr = bbus_arb_slave8_adr;
921
   defparam arbiter_bytebus0.slave9_adr = bbus_arb_slave9_adr;
922
   defparam arbiter_bytebus0.slave10_adr = bbus_arb_slave10_adr;
923
   defparam arbiter_bytebus0.slave11_adr = bbus_arb_slave11_adr;
924
 
925
 
926
`ifdef JTAG_DEBUG
927
   ////////////////////////////////////////////////////////////////////////
928
   //
929
   // JTAG TAP
930
   // 
931
   ////////////////////////////////////////////////////////////////////////
932
 
933
   //
934
   // Wires
935
   //
936
   wire                                   dbg_if_select;
937
   wire                                   dbg_if_tdo;
938
   wire                                   jtag_tap_tdo;
939
   wire                                   jtag_tap_shift_dr, jtag_tap_pause_dr,
940
                                          jtag_tap_upate_dr, jtag_tap_capture_dr;
941
   //
942
   // Instantiation
943
   //
944
 
945
   jtag_tap jtag_tap0
946
     (
947
      // Ports to pads
948
      .tdo_pad_o                        (tdo_pad_o),
949
      .tms_pad_i                        (tms_pad_i),
950
      .tck_pad_i                        (dbg_tck),
951
      .trst_pad_i                       (async_rst),
952
      .tdi_pad_i                        (tdi_pad_i),
953
 
954
      .tdo_padoe_o                      (tdo_padoe_o),
955
 
956
      .tdo_o                            (jtag_tap_tdo),
957
 
958
      .shift_dr_o                       (jtag_tap_shift_dr),
959
      .pause_dr_o                       (jtag_tap_pause_dr),
960
      .update_dr_o                      (jtag_tap_update_dr),
961
      .capture_dr_o                     (jtag_tap_capture_dr),
962
 
963
      .extest_select_o                  (),
964
      .sample_preload_select_o          (),
965
      .mbist_select_o                   (),
966
      .debug_select_o                   (dbg_if_select),
967
 
968
 
969
      .bs_chain_tdi_i                   (1'b0),
970
      .mbist_tdi_i                      (1'b0),
971
      .debug_tdi_i                      (dbg_if_tdo)
972
 
973
      );
974
 
975
   ////////////////////////////////////////////////////////////////////////
976
`endif //  `ifdef JTAG_DEBUG
977
 
978
   ////////////////////////////////////////////////////////////////////////
979
   //
980
   // OpenRISC processor
981
   // 
982
   ////////////////////////////////////////////////////////////////////////
983
 
984
   // 
985
   // Wires
986
   // 
987
 
988
   wire [30:0]                             or1200_pic_ints;
989
 
990
   wire [31:0]                             or1200_dbg_dat_i;
991
   wire [31:0]                             or1200_dbg_adr_i;
992
   wire                                   or1200_dbg_we_i;
993
   wire                                   or1200_dbg_stb_i;
994
   wire                                   or1200_dbg_ack_o;
995
   wire [31:0]                             or1200_dbg_dat_o;
996
 
997
   wire                                   or1200_dbg_stall_i;
998
   wire                                   or1200_dbg_ewt_i;
999
   wire [3:0]                              or1200_dbg_lss_o;
1000
   wire [1:0]                              or1200_dbg_is_o;
1001
   wire [10:0]                             or1200_dbg_wp_o;
1002
   wire                                   or1200_dbg_bp_o;
1003
   wire                                   or1200_dbg_rst;
1004 485 julius
 
1005 408 julius
   wire                                   or1200_clk, or1200_rst;
1006
   wire                                   sig_tick;
1007
 
1008
   //
1009
   // Assigns
1010
   //
1011
   assign or1200_clk = wb_clk;
1012
   assign or1200_rst = wb_rst | or1200_dbg_rst;
1013
 
1014
   // 
1015
   // Instantiation
1016
   //    
1017
   or1200_top or1200_top0
1018
       (
1019
        // Instruction bus, clocks, reset
1020
        .iwb_clk_i                      (wb_clk),
1021
        .iwb_rst_i                      (wb_rst),
1022
        .iwb_ack_i                      (wbm_i_or12_ack_i),
1023
        .iwb_err_i                      (wbm_i_or12_err_i),
1024
        .iwb_rty_i                      (wbm_i_or12_rty_i),
1025
        .iwb_dat_i                      (wbm_i_or12_dat_i),
1026
 
1027
        .iwb_cyc_o                      (wbm_i_or12_cyc_o),
1028
        .iwb_adr_o                      (wbm_i_or12_adr_o),
1029
        .iwb_stb_o                      (wbm_i_or12_stb_o),
1030
        .iwb_we_o                               (wbm_i_or12_we_o),
1031
        .iwb_sel_o                      (wbm_i_or12_sel_o),
1032
        .iwb_dat_o                      (wbm_i_or12_dat_o),
1033
        .iwb_cti_o                      (wbm_i_or12_cti_o),
1034
        .iwb_bte_o                      (wbm_i_or12_bte_o),
1035
 
1036
        // Data bus, clocks, reset            
1037
        .dwb_clk_i                      (wb_clk),
1038
        .dwb_rst_i                      (wb_rst),
1039
        .dwb_ack_i                      (wbm_d_or12_ack_i),
1040
        .dwb_err_i                      (wbm_d_or12_err_i),
1041
        .dwb_rty_i                      (wbm_d_or12_rty_i),
1042
        .dwb_dat_i                      (wbm_d_or12_dat_i),
1043
 
1044
        .dwb_cyc_o                      (wbm_d_or12_cyc_o),
1045
        .dwb_adr_o                      (wbm_d_or12_adr_o),
1046
        .dwb_stb_o                      (wbm_d_or12_stb_o),
1047
        .dwb_we_o                               (wbm_d_or12_we_o),
1048
        .dwb_sel_o                      (wbm_d_or12_sel_o),
1049
        .dwb_dat_o                      (wbm_d_or12_dat_o),
1050
        .dwb_cti_o                      (wbm_d_or12_cti_o),
1051
        .dwb_bte_o                      (wbm_d_or12_bte_o),
1052
 
1053
        // Debug interface ports
1054
        .dbg_stall_i                    (or1200_dbg_stall_i),
1055
        //.dbg_ewt_i                    (or1200_dbg_ewt_i),
1056
        .dbg_ewt_i                      (1'b0),
1057
        .dbg_lss_o                      (or1200_dbg_lss_o),
1058
        .dbg_is_o                               (or1200_dbg_is_o),
1059
        .dbg_wp_o                               (or1200_dbg_wp_o),
1060
        .dbg_bp_o                               (or1200_dbg_bp_o),
1061
 
1062
        .dbg_adr_i                      (or1200_dbg_adr_i),
1063
        .dbg_we_i                               (or1200_dbg_we_i ),
1064
        .dbg_stb_i                      (or1200_dbg_stb_i),
1065
        .dbg_dat_i                      (or1200_dbg_dat_i),
1066
        .dbg_dat_o                      (or1200_dbg_dat_o),
1067
        .dbg_ack_o                      (or1200_dbg_ack_o),
1068
 
1069
        .pm_clksd_o                     (),
1070
        .pm_dc_gate_o                   (),
1071
        .pm_ic_gate_o                   (),
1072
        .pm_dmmu_gate_o                 (),
1073
        .pm_immu_gate_o                 (),
1074
        .pm_tt_gate_o                   (),
1075
        .pm_cpu_gate_o                  (),
1076
        .pm_wakeup_o                    (),
1077
        .pm_lvolt_o                     (),
1078
 
1079
        // Core clocks, resets
1080
        .clk_i                          (or1200_clk),
1081
        .rst_i                          (or1200_rst),
1082
 
1083
        .clmode_i                               (2'b00),
1084
        // Interrupts      
1085
        .pic_ints_i                     (or1200_pic_ints),
1086
        .sig_tick(sig_tick),
1087
        /*
1088
         .mbist_so_o                    (),
1089
         .mbist_si_i                    (0),
1090
         .mbist_ctrl_i                  (0),
1091
         */
1092
 
1093
        .pm_cpustall_i                  (1'b0)
1094
 
1095
        );
1096
 
1097
   ////////////////////////////////////////////////////////////////////////
1098
 
1099
 
1100
`ifdef JTAG_DEBUG
1101
   ////////////////////////////////////////////////////////////////////////
1102
         //
1103
   // OR1200 Debug Interface
1104
   // 
1105
   ////////////////////////////////////////////////////////////////////////
1106
 
1107
   dbg_if dbg_if0
1108
     (
1109
      // OR1200 interface
1110
      .cpu0_clk_i                       (or1200_clk),
1111
      .cpu0_rst_o                       (or1200_dbg_rst),
1112
      .cpu0_addr_o                      (or1200_dbg_adr_i),
1113
      .cpu0_data_o                      (or1200_dbg_dat_i),
1114
      .cpu0_stb_o                       (or1200_dbg_stb_i),
1115
      .cpu0_we_o                        (or1200_dbg_we_i),
1116
      .cpu0_data_i                      (or1200_dbg_dat_o),
1117
      .cpu0_ack_i                       (or1200_dbg_ack_o),
1118
 
1119
 
1120
      .cpu0_stall_o                     (or1200_dbg_stall_i),
1121
      .cpu0_bp_i                        (or1200_dbg_bp_o),
1122
 
1123
      // TAP interface
1124
      .tck_i                            (dbg_tck),
1125
      .tdi_i                            (jtag_tap_tdo),
1126
      .tdo_o                            (dbg_if_tdo),
1127
      .rst_i                            (wb_rst),
1128
      .shift_dr_i                       (jtag_tap_shift_dr),
1129
      .pause_dr_i                       (jtag_tap_pause_dr),
1130
      .update_dr_i                      (jtag_tap_update_dr),
1131
      .debug_select_i                   (dbg_if_select),
1132
 
1133
      // Wishbone debug master
1134
      .wb_clk_i                         (wb_clk),
1135
      .wb_dat_i                         (wbm_d_dbg_dat_i),
1136
      .wb_ack_i                         (wbm_d_dbg_ack_i),
1137
      .wb_err_i                         (wbm_d_dbg_err_i),
1138
      .wb_adr_o                         (wbm_d_dbg_adr_o),
1139
      .wb_dat_o                         (wbm_d_dbg_dat_o),
1140
      .wb_cyc_o                         (wbm_d_dbg_cyc_o),
1141
      .wb_stb_o                         (wbm_d_dbg_stb_o),
1142
      .wb_sel_o                         (wbm_d_dbg_sel_o),
1143
      .wb_we_o                          (wbm_d_dbg_we_o ),
1144
      .wb_cti_o                         (wbm_d_dbg_cti_o),
1145
      .wb_cab_o                         (/*   UNUSED  */),
1146
      .wb_bte_o                         (wbm_d_dbg_bte_o)
1147
      );
1148
 
1149
   ////////////////////////////////////////////////////////////////////////   
1150
`else // !`ifdef JTAG_DEBUG
1151
 
1152
   assign wbm_d_dbg_adr_o = 0;
1153
   assign wbm_d_dbg_dat_o = 0;
1154
   assign wbm_d_dbg_cyc_o = 0;
1155
   assign wbm_d_dbg_stb_o = 0;
1156
   assign wbm_d_dbg_sel_o = 0;
1157
   assign wbm_d_dbg_we_o  = 0;
1158
   assign wbm_d_dbg_cti_o = 0;
1159
   assign wbm_d_dbg_bte_o = 0;
1160
 
1161
   assign or1200_dbg_adr_i = 0;
1162
   assign or1200_dbg_dat_i = 0;
1163
   assign or1200_dbg_stb_i = 0;
1164
   assign or1200_dbg_we_i = 0;
1165
   assign or1200_dbg_stall_i = 0;
1166
 
1167
   ////////////////////////////////////////////////////////////////////////   
1168
`endif // !`ifdef JTAG_DEBUG
1169
 
1170
`ifdef VERSATILE_SDRAM
1171
   ////////////////////////////////////////////////////////////////////////
1172
   //
1173
   // Versatile Memory Controller (SDRAM configured)
1174
   // 
1175
   ////////////////////////////////////////////////////////////////////////
1176
 
1177
   //
1178
   // Wires
1179
   //
1180
 
1181
   wire [15:0]                             sdram_dq_i;
1182
   wire [15:0]                             sdram_dq_o;
1183
   wire                                   sdram_dq_oe;
1184
 
1185
   //
1186
   // Assigns
1187
   //
1188
 
1189
   assign sdram_dq_i = sdram_dq_pad_io;
1190
   assign sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz;
1191
 
1192
   versatile_mem_ctrl versatile_mem_ctrl0
1193
     (
1194
      // External SDRAM interface
1195
      .ba_pad_o                         (sdram_ba_pad_o[1:0]),
1196
      .a_pad_o                          (sdram_a_pad_o[12:0]),
1197
      .cs_n_pad_o                       (sdram_cs_n_pad_o),
1198
      .ras_pad_o                        (sdram_ras_pad_o),
1199
      .cas_pad_o                        (sdram_cas_pad_o),
1200
      .we_pad_o                         (sdram_we_pad_o),
1201
      .dq_i                             (sdram_dq_i[15:0]),
1202
      .dq_o                             (sdram_dq_o[15:0]),
1203
      .dqm_pad_o                        (sdram_dqm_pad_o[1:0]),
1204
      .dq_oe                            (sdram_dq_oe),
1205
      .cke_pad_o                        (sdram_cke_pad_o),
1206
      .sdram_clk                        (sdram_clk),
1207
      .sdram_rst                        (sdram_rst),
1208
 `ifdef ETH0
1209
      // Wishbone slave interface 0
1210
      .wb_dat_i_0                       ({{wbm_eth0_dat_o, wbm_eth0_sel_o},{wbs_d_mc0_dat_i, wbs_d_mc0_sel_i},{wbs_i_mc0_dat_i,wbs_i_mc0_sel_i}}),
1211
      .wb_adr_i_0                       ({{wbm_eth0_adr_o[31:2], wbm_eth0_we_o, wbm_eth0_bte_o, wbm_eth0_cti_o},
1212
                                          {wbs_d_mc0_adr_i[31:2], wbs_d_mc0_we_i, wbs_d_mc0_bte_i, wbs_d_mc0_cti_i},
1213
                                          {wbs_i_mc0_adr_i[31:2], wbs_i_mc0_we_i, wbs_i_mc0_bte_i, wbs_i_mc0_cti_i}}),
1214
      .wb_cyc_i_0                       ({wbm_eth0_cyc_o,wbs_d_mc0_cyc_i,wbs_i_mc0_cyc_i}),
1215
      .wb_stb_i_0                       ({wbm_eth0_stb_o,wbs_d_mc0_stb_i,wbs_i_mc0_stb_i}),
1216
      .wb_dat_o_0                       ({wbm_eth0_dat_i,wbs_d_mc0_dat_o,wbs_i_mc0_dat_o}),
1217
      .wb_ack_o_0                       ({wbm_eth0_ack_i,wbs_d_mc0_ack_o,wbs_i_mc0_ack_o}),
1218
 `else // !`ifdef ETH0
1219
      // Wishbone slave interface 0
1220
      .wb_dat_i_0                       ({{wbs_d_mc0_dat_i, wbs_d_mc0_sel_i},{wbs_i_mc0_dat_i,wbs_i_mc0_sel_i}}),
1221
      .wb_adr_i_0                       ({{wbs_d_mc0_adr_i[31:2], wbs_d_mc0_we_i, wbs_d_mc0_bte_i, wbs_d_mc0_cti_i},
1222
                                          {wbs_i_mc0_adr_i[31:2], wbs_i_mc0_we_i, wbs_i_mc0_bte_i, wbs_i_mc0_cti_i}}),
1223
      .wb_cyc_i_0                       ({wbs_d_mc0_cyc_i,wbs_i_mc0_cyc_i}),
1224
      .wb_stb_i_0                       ({wbs_d_mc0_stb_i,wbs_i_mc0_stb_i}),
1225
      .wb_dat_o_0                       ({wbs_d_mc0_dat_o,wbs_i_mc0_dat_o}),
1226
      .wb_ack_o_0                       ({wbs_d_mc0_ack_o,wbs_i_mc0_ack_o}),
1227
 `endif // !`ifdef ETH0
1228
 
1229
      // Wishbone slave interface 1
1230
      .wb_dat_i_1                       (2'd0),
1231
      .wb_adr_i_1                       (2'd0),
1232
      .wb_cyc_i_1                       (2'd0),
1233
      .wb_stb_i_1                       (2'd0),
1234
      .wb_dat_o_1                       (),
1235
      .wb_ack_o_1                       (),
1236
 
1237
      // Wishbone slave interface 2
1238
      .wb_dat_i_2                       (2'd0),
1239
      .wb_adr_i_2                       (2'd0),
1240
      .wb_cyc_i_2                       (2'd0),
1241
      .wb_stb_i_2                       (2'd0),
1242
      .wb_dat_o_2                       (),
1243
      .wb_ack_o_2                       (),
1244
 
1245
      // Wishbone slave interface 3
1246
      .wb_dat_i_3                       (2'd0),
1247
      .wb_adr_i_3                       (2'd0),
1248
      .wb_cyc_i_3                       (2'd0),
1249
      .wb_stb_i_3                       (2'd0),
1250
      .wb_dat_o_3                       (),
1251
      .wb_ack_o_3                       (),
1252
 
1253
      .wb_clk                           (wb_clk),
1254
      .wb_rst                           (wb_rst)
1255
      );
1256
 
1257
   // If not using gatelevel, define parameters
1258
   // Hard-set here to just 2 ports from the same domain
1259
 
1260
   defparam versatile_mem_ctrl0.nr_of_wb_clk_domains = 1;
1261
 `ifdef ETH0
1262
   defparam versatile_mem_ctrl0.nr_of_wb_ports_clk0  = 3;
1263
 `else
1264
   defparam versatile_mem_ctrl0.nr_of_wb_ports_clk0  = 2;
1265
 `endif
1266
   defparam versatile_mem_ctrl0.nr_of_wb_ports_clk1  = 0;
1267
   defparam versatile_mem_ctrl0.nr_of_wb_ports_clk2  = 0;
1268
   defparam versatile_mem_ctrl0.nr_of_wb_ports_clk3  = 0;
1269
 
1270
   assign wbs_i_mc0_err_o = 0;
1271
   assign wbs_i_mc0_rty_o = 0;
1272
 
1273
   assign wbs_d_mc0_err_o = 0;
1274
   assign wbs_d_mc0_rty_o = 0;
1275
 
1276
   assign wbm_eth0_err_i = 0;
1277
   assign wbm_eth0_rty_i = 0;
1278
 
1279
 
1280
   ////////////////////////////////////////////////////////////////////////
1281
`endif //  `ifdef VERSATILE_SDRAM
1282
 
1283
   ////////////////////////////////////////////////////////////////////////
1284
   //
1285
   // ROM
1286
   // 
1287
   ////////////////////////////////////////////////////////////////////////
1288
 
1289
   rom rom0
1290
     (
1291
      .wb_dat_o                         (wbs_i_rom0_dat_o),
1292
      .wb_ack_o                         (wbs_i_rom0_ack_o),
1293
      .wb_adr_i                         (wbs_i_rom0_adr_i[(wbs_i_rom0_addr_width+2)-1:2]),
1294
      .wb_stb_i                         (wbs_i_rom0_stb_i),
1295
      .wb_cyc_i                         (wbs_i_rom0_cyc_i),
1296
      .wb_cti_i                         (wbs_i_rom0_cti_i),
1297
      .wb_bte_i                         (wbs_i_rom0_bte_i),
1298
      .wb_clk                           (wb_clk),
1299
      .wb_rst                           (wb_rst));
1300
 
1301
   defparam rom0.addr_width = wbs_i_rom0_addr_width;
1302
 
1303
   assign wbs_i_rom0_err_o = 0;
1304
   assign wbs_i_rom0_rty_o = 0;
1305
 
1306
   ////////////////////////////////////////////////////////////////////////
1307
 
1308
 
1309
`ifdef ACTEL_UFR
1310
   ////////////////////////////////////////////////////////////////////////
1311
   //
1312
   // Flash ROM
1313
   // 
1314
   ////////////////////////////////////////////////////////////////////////
1315
   flashrom flashrom0
1316
     (
1317
      .wb_dat_o                         (wbs_d_flashrom_dat_o),
1318
      .wb_ack_o                         (wbs_d_flashrom_ack_o),
1319
      .wb_err_o                         (wbs_d_flashrom_err_o),
1320
      .wb_rty_o                         (wbs_d_flashrom_rty_o),
1321
      .wb_adr_i                         (wbs_d_flashrom_adr_i[flashrom_wb_adr_width-1:0]),
1322
      .wb_stb_i                         (wbs_d_flashrom_stb_i),
1323
      .wb_cyc_i                         (wbs_d_flashrom_cyc_i),
1324
      .wb_clk                           (wb_clk),
1325
      .wb_rst                           (wb_rst));
1326
`else // !`ifdef ACTEL_UFR0
1327
   assign wbs_d_flashrom_dat_o = 0;
1328
   assign wbs_d_flashrom_ack_o = wbs_d_flashrom_stb_i;
1329
`endif // !`ifdef ACTEL_UFR0
1330
 
1331
   assign wbs_i_rom0_err_o = 0;
1332
   assign wbs_i_rom0_rty_o = 0;
1333
 
1334
`ifdef RAM_WB
1335
   ////////////////////////////////////////////////////////////////////////
1336
   //
1337
   // Generic RAM
1338
   // 
1339
   ////////////////////////////////////////////////////////////////////////
1340
 
1341
   ram_wb ram_wb0
1342
     (
1343
      // Wishbone slave interface 0
1344
      .wbm0_dat_i                       (wbs_i_mc0_dat_i),
1345
      .wbm0_adr_i                       (wbs_i_mc0_adr_i),
1346
      .wbm0_sel_i                       (wbs_i_mc0_sel_i),
1347
      .wbm0_cti_i                       (wbs_i_mc0_cti_i),
1348
      .wbm0_bte_i                       (wbs_i_mc0_bte_i),
1349
      .wbm0_we_i                        (wbs_i_mc0_we_i ),
1350
      .wbm0_cyc_i                       (wbs_i_mc0_cyc_i),
1351
      .wbm0_stb_i                       (wbs_i_mc0_stb_i),
1352
      .wbm0_dat_o                       (wbs_i_mc0_dat_o),
1353
      .wbm0_ack_o                       (wbs_i_mc0_ack_o),
1354 439 julius
      .wbm0_err_o                       (wbs_i_mc0_err_o),
1355
      .wbm0_rty_o                       (wbs_i_mc0_rty_o),
1356 408 julius
      // Wishbone slave interface 1
1357
      .wbm1_dat_i                       (wbs_d_mc0_dat_i),
1358
      .wbm1_adr_i                       (wbs_d_mc0_adr_i),
1359
      .wbm1_sel_i                       (wbs_d_mc0_sel_i),
1360
      .wbm1_cti_i                       (wbs_d_mc0_cti_i),
1361
      .wbm1_bte_i                       (wbs_d_mc0_bte_i),
1362
      .wbm1_we_i                        (wbs_d_mc0_we_i ),
1363
      .wbm1_cyc_i                       (wbs_d_mc0_cyc_i),
1364
      .wbm1_stb_i                       (wbs_d_mc0_stb_i),
1365
      .wbm1_dat_o                       (wbs_d_mc0_dat_o),
1366
      .wbm1_ack_o                       (wbs_d_mc0_ack_o),
1367 439 julius
      .wbm1_err_o                       (wbs_d_mc0_err_o),
1368
      .wbm1_rty_o                       (wbs_d_mc0_rty_o),
1369
      // Wishbone slave interface 2
1370
      .wbm2_dat_i                       (wbm_eth0_dat_o),
1371
      .wbm2_adr_i                       (wbm_eth0_adr_o),
1372
      .wbm2_sel_i                       (wbm_eth0_sel_o),
1373
      .wbm2_cti_i                       (wbm_eth0_cti_o),
1374
      .wbm2_bte_i                       (wbm_eth0_bte_o),
1375
      .wbm2_we_i                        (wbm_eth0_we_o ),
1376
      .wbm2_cyc_i                       (wbm_eth0_cyc_o),
1377
      .wbm2_stb_i                       (wbm_eth0_stb_o),
1378
      .wbm2_dat_o                       (wbm_eth0_dat_i),
1379
      .wbm2_ack_o                       (wbm_eth0_ack_i),
1380
      .wbm2_err_o                       (wbm_eth0_err_i),
1381
      .wbm2_rty_o                       (wbm_eth0_rty_i),
1382 408 julius
      // Clock, reset
1383
      .wb_clk_i                         (wb_clk),
1384
      .wb_rst_i                         (wb_rst));
1385
 
1386
   defparam ram_wb0.aw = wb_aw;
1387
   defparam ram_wb0.dw = wb_dw;
1388 439 julius
   defparam ram_wb0.mem_size_bytes = internal_sram_mem_span;
1389
   defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span;
1390 408 julius
   ////////////////////////////////////////////////////////////////////////
1391
`endif //  `ifdef RAM_WB
1392
 
1393
 
1394
`ifdef ETH0
1395
 
1396
   //
1397
   // Wires
1398
   //
1399
   wire        eth0_irq;
1400
   wire [3:0]  eth0_mtxd;
1401
   wire        eth0_mtxen;
1402
   wire        eth0_mtxerr;
1403
   wire        eth0_mtx_clk;
1404
   wire        eth0_mrx_clk;
1405
   wire [3:0]  eth0_mrxd;
1406
   wire        eth0_mrxdv;
1407
   wire        eth0_mrxerr;
1408
   wire        eth0_mcoll;
1409
   wire        eth0_mcrs;
1410
   wire        eth0_speed;
1411
   wire        eth0_duplex;
1412
   wire        eth0_link;
1413
   // Management interface wires
1414
   wire        eth0_md_i;
1415
   wire        eth0_md_o;
1416
   wire        eth0_md_oe;
1417
 
1418
 
1419
   //
1420
   // assigns
1421
 `ifdef SMII0
1422
   smii smii0
1423
     (
1424
      // SMII pads
1425
      .eth_sync_pad_o                   (eth0_smii_sync_pad_o),
1426
      .eth_tx_pad_o                     (eth0_smii_tx_pad_o),
1427
      .eth_rx_pad_i                     (eth0_smii_rx_pad_i),
1428
 
1429
      // MII interface to MAC
1430
      // Transmit
1431
      .mtx_clk                          (eth0_mtx_clk),
1432
      .mtxd                             (eth0_mtxd[3:0]),
1433
      .mtxen                            (eth0_mtxen),
1434
      .mtxerr                           (eth0_mtxerr),
1435
      .mrxd                             (eth0_mrxd[3:0]),
1436
      // Receive
1437
      .mrxdv                            (eth0_mrxdv),
1438
      .mrxerr                           (eth0_mrxerr),
1439
      .mrx_clk                          (eth0_mrx_clk),
1440
      // Status signals
1441
      .mcoll                            (eth0_mcoll),
1442
      .mcrs                             (eth0_mcrs),
1443
      .speed                            (eth0_speed),
1444
      .duplex                           (eth0_duplex),
1445
      .link                             (eth0_link),
1446
 
1447
      // Inputs
1448
      .eth_clk                          (eth_smii_clk),
1449
      .eth_rst                          (eth_smii_rst)
1450
      );
1451
 
1452
`else // !`ifdef SMII0
1453
 
1454
   // Hook up MII wires
1455
   assign eth0_mtx_clk   = eth0_tx_clk;
1456
   assign eth0_tx_data   = eth0_mtxd[3:0];
1457
   assign eth0_tx_en     = eth0_mtxen;
1458
   assign eth0_tx_er     = eth0_mtxerr;
1459
   assign eth0_mrxd[3:0] = eth0_rx_data;
1460
   assign eth0_mrxdv     = eth0_dv;
1461
   assign eth0_mrxerr    = eth0_rx_er;
1462
   assign eth0_mrx_clk   = eth0_rx_clk;
1463
   assign eth0_mcoll     = eth0_col;
1464
   assign eth0_mcrs      = eth0_crs;
1465
 
1466
`endif // !`ifdef SMII0
1467
 
1468
`ifdef XILINX
1469
   // Xilinx primitive for MDIO tristate
1470
   IOBUF iobuf_phy_smi_data
1471
     (
1472
      // Outputs
1473
      .O                                 (eth0_md_i),
1474
      // Inouts
1475
      .IO                                (eth0_md_pad_io),
1476
      // Inputs
1477
      .I                                 (eth0_md_o),
1478
      .T                                 (!eth0_md_oe));
1479
`else // !`ifdef XILINX
1480
 
1481
   // Generic technology tristate control for management interface
1482
   assign eth0_md_pad_io = eth0_md_oe ? eth0_md_o : 1'bz;
1483
   assign eth0_md_i = eth0_md_pad_io;
1484
 
1485
`endif // !`ifdef XILINX
1486
 
1487
`ifdef ETH0_PHY_RST
1488
   assign eth0_rst_n_o = !wb_rst;
1489
`endif
1490
 
1491 409 julius
   ethmac ethmac0
1492 408 julius
     (
1493
      // Wishbone Slave interface
1494
      .wb_clk_i         (wb_clk),
1495
      .wb_rst_i         (wb_rst),
1496
      .wb_dat_i         (wbs_d_eth0_dat_i[31:0]),
1497
      .wb_adr_i         (wbs_d_eth0_adr_i[wbs_d_eth0_addr_width-1:2]),
1498
      .wb_sel_i         (wbs_d_eth0_sel_i[3:0]),
1499
      .wb_we_i          (wbs_d_eth0_we_i),
1500
      .wb_cyc_i         (wbs_d_eth0_cyc_i),
1501
      .wb_stb_i         (wbs_d_eth0_stb_i),
1502
      .wb_dat_o         (wbs_d_eth0_dat_o[31:0]),
1503
      .wb_err_o         (wbs_d_eth0_err_o),
1504
      .wb_ack_o         (wbs_d_eth0_ack_o),
1505
      // Wishbone Master Interface
1506
      .m_wb_adr_o       (wbm_eth0_adr_o[31:0]),
1507
      .m_wb_sel_o       (wbm_eth0_sel_o[3:0]),
1508
      .m_wb_we_o        (wbm_eth0_we_o),
1509
      .m_wb_dat_o       (wbm_eth0_dat_o[31:0]),
1510
      .m_wb_cyc_o       (wbm_eth0_cyc_o),
1511
      .m_wb_stb_o       (wbm_eth0_stb_o),
1512
      .m_wb_cti_o       (wbm_eth0_cti_o[2:0]),
1513
      .m_wb_bte_o       (wbm_eth0_bte_o[1:0]),
1514
      .m_wb_dat_i       (wbm_eth0_dat_i[31:0]),
1515
      .m_wb_ack_i       (wbm_eth0_ack_i),
1516
      .m_wb_err_i       (wbm_eth0_err_i),
1517
 
1518
      // Ethernet MII interface
1519
      // Transmit
1520
      .mtxd_pad_o       (eth0_mtxd[3:0]),
1521
      .mtxen_pad_o      (eth0_mtxen),
1522
      .mtxerr_pad_o     (eth0_mtxerr),
1523
      .mtx_clk_pad_i    (eth0_mtx_clk),
1524
      // Receive
1525
      .mrx_clk_pad_i    (eth0_mrx_clk),
1526
      .mrxd_pad_i       (eth0_mrxd[3:0]),
1527
      .mrxdv_pad_i      (eth0_mrxdv),
1528
      .mrxerr_pad_i     (eth0_mrxerr),
1529
      .mcoll_pad_i      (eth0_mcoll),
1530
      .mcrs_pad_i       (eth0_mcrs),
1531
      // Management interface
1532
      .md_pad_i         (eth0_md_i),
1533
      .mdc_pad_o        (eth0_mdc_pad_o),
1534
      .md_pad_o         (eth0_md_o),
1535
      .md_padoe_o       (eth0_md_oe),
1536
 
1537
      // Processor interrupt
1538
      .int_o            (eth0_irq)
1539
 
1540
      /*
1541
       .mbist_so_o                      (),
1542
       .mbist_si_i                      (),
1543
       .mbist_ctrl_i                    ()
1544
       */
1545
 
1546
      );
1547
 
1548
   assign wbs_d_eth0_rty_o = 0;
1549
 
1550
`else
1551
   assign wbs_d_eth0_dat_o = 0;
1552
   assign wbs_d_eth0_err_o = 0;
1553
   assign wbs_d_eth0_ack_o = 0;
1554
   assign wbs_d_eth0_rty_o = 0;
1555
   assign wbm_eth0_adr_o = 0;
1556
   assign wbm_eth0_sel_o = 0;
1557
   assign wbm_eth0_we_o = 0;
1558
   assign wbm_eth0_dat_o = 0;
1559
   assign wbm_eth0_cyc_o = 0;
1560
   assign wbm_eth0_stb_o = 0;
1561
   assign wbm_eth0_cti_o = 0;
1562
   assign wbm_eth0_bte_o = 0;
1563
`endif
1564
 
1565
`ifdef UART0
1566
   ////////////////////////////////////////////////////////////////////////
1567
   //
1568
   // UART0
1569
   // 
1570
   ////////////////////////////////////////////////////////////////////////
1571
 
1572
   //
1573
   // Wires
1574
   //
1575
   wire        uart0_irq;
1576
 
1577
   //
1578
   // Assigns
1579
   //
1580
   assign wbs_d_uart0_err_o = 0;
1581
   assign wbs_d_uart0_rty_o = 0;
1582
 
1583
   uart16550 uart16550_0
1584
     (
1585
      // Wishbone slave interface
1586
      .wb_clk_i                         (wb_clk),
1587
      .wb_rst_i                         (wb_rst),
1588
      .wb_adr_i                         (wbs_d_uart0_adr_i[uart0_addr_width-1:0]),
1589
      .wb_dat_i                         (wbs_d_uart0_dat_i),
1590
      .wb_we_i                          (wbs_d_uart0_we_i),
1591
      .wb_stb_i                         (wbs_d_uart0_stb_i),
1592
      .wb_cyc_i                         (wbs_d_uart0_cyc_i),
1593
      //.wb_sel_i                               (),
1594
      .wb_dat_o                         (wbs_d_uart0_dat_o),
1595
      .wb_ack_o                         (wbs_d_uart0_ack_o),
1596
 
1597
      .int_o                            (uart0_irq),
1598
      .stx_pad_o                        (uart0_stx_pad_o),
1599
      .rts_pad_o                        (),
1600
      .dtr_pad_o                        (),
1601
      //      .baud_o                           (),
1602
      // Inputs
1603
      .srx_pad_i                        (uart0_srx_pad_i),
1604
      .cts_pad_i                        (1'b0),
1605
      .dsr_pad_i                        (1'b0),
1606
      .ri_pad_i                         (1'b0),
1607
      .dcd_pad_i                        (1'b0));
1608
 
1609
   ////////////////////////////////////////////////////////////////////////          
1610
`else // !`ifdef UART0
1611
 
1612
   //
1613
   // Assigns
1614
   //
1615
   assign wbs_d_uart0_err_o = 0;
1616
   assign wbs_d_uart0_rty_o = 0;
1617
   assign wbs_d_uart0_ack_o = 0;
1618
   assign wbs_d_uart0_dat_o = 0;
1619
 
1620
   ////////////////////////////////////////////////////////////////////////       
1621
`endif // !`ifdef UART0
1622
 
1623
`ifdef SPI0
1624
   ////////////////////////////////////////////////////////////////////////
1625
   //
1626
   // SPI0 controller
1627
   // 
1628
   ////////////////////////////////////////////////////////////////////////
1629
 
1630
   //
1631
   // Wires
1632
   //
1633
   wire                              spi0_irq;
1634
 
1635
   //
1636
   // Assigns
1637
   //
1638
   assign wbs_d_spi0_err_o = 0;
1639
   assign wbs_d_spi0_rty_o = 0;
1640
   assign spi0_hold_n_o = 1;
1641
   assign spi0_w_n_o = 1;
1642
 
1643
 
1644
   simple_spi spi0
1645
     (
1646
      // Wishbone slave interface
1647
      .clk_i                            (wb_clk),
1648
      .rst_i                            (wb_rst),
1649
      .cyc_i                            (wbs_d_spi0_cyc_i),
1650
      .stb_i                            (wbs_d_spi0_stb_i),
1651
      .adr_i                            (wbs_d_spi0_adr_i[spi0_wb_adr_width-1:0]),
1652
      .we_i                             (wbs_d_spi0_we_i),
1653
      .dat_i                            (wbs_d_spi0_dat_i),
1654
      .dat_o                            (wbs_d_spi0_dat_o),
1655
      .ack_o                            (wbs_d_spi0_ack_o),
1656
      // SPI IRQ
1657
      .inta_o                           (spi0_irq),
1658
      // External SPI interface
1659
      .sck_o                            (spi0_sck_o),
1660
 `ifdef SPI0_SLAVE_SELECTS
1661
      .ss_o                             (spi0_ss_o),
1662
 `else
1663
      .ss_o                             (),
1664
 `endif
1665
      .mosi_o                           (spi0_mosi_o),
1666
      .miso_i                           (spi0_miso_i)
1667
      );
1668
 
1669
   defparam spi0.slave_select_width = spi0_ss_width;
1670
 
1671
   ////////////////////////////////////////////////////////////////////////   
1672
`else // !`ifdef SPI0
1673
 
1674
   //
1675
   // Assigns
1676
   //
1677
   assign wbs_d_spi0_dat_o = 0;
1678
   assign wbs_d_spi0_ack_o = 0;
1679
   assign wbs_d_spi0_err_o = 0;
1680
   assign wbs_d_spi0_rty_o = 0;
1681
 
1682
   ////////////////////////////////////////////////////////////////////////
1683
`endif // !`ifdef SPI0   
1684
 
1685
 
1686
`ifdef SPI1
1687
   ////////////////////////////////////////////////////////////////////////
1688
   //
1689
   // SPI1 controller
1690
   // 
1691
   ////////////////////////////////////////////////////////////////////////
1692
 
1693
   //
1694
   // Wires
1695
   //
1696
   wire                              spi1_irq;
1697
 
1698
   //
1699
   // Assigns
1700
   //
1701
   assign wbs_d_spi1_err_o = 0;
1702
   assign wbs_d_spi1_rty_o = 0;
1703
 
1704
   simple_spi spi1
1705
     (
1706
      // Wishbone slave interface
1707
      .clk_i                            (wb_clk),
1708
      .rst_i                            (wb_rst),
1709
      .cyc_i                            (wbs_d_spi1_cyc_i),
1710
      .stb_i                            (wbs_d_spi1_stb_i),
1711
      .adr_i                            (wbs_d_spi1_adr_i[spi1_wb_adr_width-1:0]),
1712
      .we_i                             (wbs_d_spi1_we_i),
1713
      .dat_i                            (wbs_d_spi1_dat_i),
1714
      .dat_o                            (wbs_d_spi1_dat_o),
1715
      .ack_o                            (wbs_d_spi1_ack_o),
1716
      // SPI IRQ
1717
      .inta_o                           (spi1_irq),
1718
      // External SPI interface
1719
      .sck_o                            (spi1_sck_o),
1720
`ifdef SPI1_SLAVE_SELECTS
1721
      .ss_o                             (spi1_ss_o),
1722
`else
1723
      .ss_o                             (),
1724
`endif
1725
      .mosi_o                           (spi1_mosi_o),
1726
      .miso_i                           (spi1_miso_i)
1727
      );
1728
 
1729
   defparam spi1.slave_select_width = spi1_ss_width;
1730
 
1731
   ////////////////////////////////////////////////////////////////////////   
1732
`else // !`ifdef SPI1
1733
 
1734
   //
1735
   // Assigns
1736
   //
1737
   assign wbs_d_spi1_dat_o = 0;
1738
   assign wbs_d_spi1_ack_o = 0;
1739
   assign wbs_d_spi1_err_o = 0;
1740
   assign wbs_d_spi1_rty_o = 0;
1741
 
1742
   ////////////////////////////////////////////////////////////////////////
1743
`endif // !`ifdef SPI1
1744
 
1745
 
1746
`ifdef SPI2
1747
   ////////////////////////////////////////////////////////////////////////
1748
   //
1749
   // SPI2 controller
1750
   // 
1751
   ////////////////////////////////////////////////////////////////////////
1752
 
1753
   //
1754
   // Wires
1755
   //
1756
   wire                              spi2_irq;
1757
 
1758
   //
1759
   // Assigns
1760
   //
1761
   assign wbs_d_spi2_err_o = 0;
1762
   assign wbs_d_spi2_rty_o = 0;
1763
 
1764
   simple_spi spi2
1765
     (
1766
      // Wishbone slave interface
1767
      .clk_i                            (wb_clk),
1768
      .rst_i                            (wb_rst),
1769
      .cyc_i                            (wbs_d_spi2_cyc_i),
1770
      .stb_i                            (wbs_d_spi2_stb_i),
1771
      .adr_i                            (wbs_d_spi2_adr_i[spi2_wb_adr_width-1:0]),
1772
      .we_i                             (wbs_d_spi2_we_i),
1773
      .dat_i                            (wbs_d_spi2_dat_i),
1774
      .dat_o                            (wbs_d_spi2_dat_o),
1775
      .ack_o                            (wbs_d_spi2_ack_o),
1776
      // SPI IRQ
1777
      .inta_o                           (spi2_irq),
1778
      // External SPI interface
1779
      .sck_o                            (spi2_sck_o),
1780
`ifdef SPI2_SLAVE_SELECTS
1781
      .ss_o                             (spi2_ss_o),
1782
`else
1783
      .ss_o                             (),
1784
`endif
1785
      .mosi_o                           (spi2_mosi_o),
1786
      .miso_i                           (spi2_miso_i)
1787
      );
1788
 
1789
   defparam spi2.slave_select_width = spi2_ss_width;
1790
 
1791
   ////////////////////////////////////////////////////////////////////////   
1792
`else // !`ifdef SPI2
1793
 
1794
   //
1795
   // Assigns
1796
   //
1797
   assign wbs_d_spi2_dat_o = 0;
1798
   assign wbs_d_spi2_ack_o = 0;
1799
   assign wbs_d_spi2_err_o = 0;
1800
   assign wbs_d_spi2_rty_o = 0;
1801
 
1802
   ////////////////////////////////////////////////////////////////////////
1803
`endif // !`ifdef SPI2   
1804
 
1805
 
1806
`ifdef I2C0
1807
   ////////////////////////////////////////////////////////////////////////
1808
   //
1809
   // i2c controller 0
1810
   // 
1811
   ////////////////////////////////////////////////////////////////////////
1812
 
1813
   //
1814
   // Wires
1815
   //
1816
   wire                              i2c0_irq;
1817
   wire                              scl0_pad_o;
1818
   wire                              scl0_padoen_o;
1819
   wire                              sda0_pad_o;
1820
   wire                              sda0_padoen_o;
1821
 
1822
  i2c_master_slave
1823
    #
1824
    (
1825
     .DEFAULT_SLAVE_ADDR(HV0_SADR)
1826
    )
1827
  i2c_master_slave0
1828
    (
1829
     .wb_clk_i                       (wb_clk),
1830
     .wb_rst_i                       (wb_rst),
1831
     .arst_i                         (wb_rst),
1832
     .wb_adr_i                       (wbs_d_i2c0_adr_i[i2c_0_wb_adr_width-1:0]),
1833
     .wb_dat_i                       (wbs_d_i2c0_dat_i),
1834
     .wb_we_i                        (wbs_d_i2c0_we_i ),
1835
     .wb_cyc_i                       (wbs_d_i2c0_cyc_i),
1836
     .wb_stb_i                       (wbs_d_i2c0_stb_i),
1837
     .wb_dat_o                       (wbs_d_i2c0_dat_o),
1838
     .wb_ack_o                       (wbs_d_i2c0_ack_o),
1839
     .scl_pad_i                      (i2c0_scl_io     ),
1840
     .scl_pad_o                      (scl0_pad_o         ),
1841
     .scl_padoen_o                   (scl0_padoen_o      ),
1842
     .sda_pad_i                      (i2c0_sda_io        ),
1843
     .sda_pad_o                      (sda0_pad_o         ),
1844
     .sda_padoen_o                   (sda0_padoen_o      ),
1845
 
1846
      // Interrupt
1847
     .wb_inta_o                      (i2c0_irq)
1848
 
1849
      );
1850
 
1851
   assign wbs_d_i2c0_err_o = 0;
1852
   assign wbs_d_i2c0_rty_o = 0;
1853
 
1854
   // i2c phy lines
1855
   assign i2c0_scl_io = scl0_padoen_o ? 1'bz : scl0_pad_o;
1856
   assign i2c0_sda_io = sda0_padoen_o ? 1'bz : sda0_pad_o;
1857
 
1858
 
1859
   ////////////////////////////////////////////////////////////////////////
1860
`else // !`ifdef I2C0
1861
 
1862
   assign wbs_d_i2c0_dat_o = 0;
1863
   assign wbs_d_i2c0_ack_o = 0;
1864
   assign wbs_d_i2c0_err_o = 0;
1865
   assign wbs_d_i2c0_rty_o = 0;
1866
 
1867
   ////////////////////////////////////////////////////////////////////////
1868
`endif // !`ifdef I2C0   
1869
 
1870
`ifdef I2C1
1871
   ////////////////////////////////////////////////////////////////////////
1872
   //
1873
   // i2c controller 1
1874
   // 
1875
   ////////////////////////////////////////////////////////////////////////
1876
 
1877
   //
1878
   // Wires
1879
   //
1880
   wire                              i2c1_irq;
1881
   wire                              scl1_pad_o;
1882
   wire                              scl1_padoen_o;
1883
   wire                              sda1_pad_o;
1884
   wire                              sda1_padoen_o;
1885
 
1886
   i2c_master_slave
1887
    #
1888
    (
1889
     .DEFAULT_SLAVE_ADDR(HV1_SADR)
1890
    )
1891
   i2c_master_slave1
1892
     (
1893
      .wb_clk_i                      (wb_clk),
1894
      .wb_rst_i                      (wb_rst),
1895
      .arst_i                        (wb_rst),
1896
      .wb_adr_i                      (wbs_d_i2c1_adr_i[i2c_1_wb_adr_width-1:0]),
1897
      .wb_dat_i                      (wbs_d_i2c1_dat_i),
1898
      .wb_we_i                       (wbs_d_i2c1_we_i ),
1899
      .wb_cyc_i                      (wbs_d_i2c1_cyc_i),
1900
      .wb_stb_i                      (wbs_d_i2c1_stb_i),
1901
      .wb_dat_o                      (wbs_d_i2c1_dat_o),
1902
      .wb_ack_o                      (wbs_d_i2c1_ack_o),
1903
      .scl_pad_i                     (i2c1_scl_io     ),
1904
      .scl_pad_o                     (scl1_pad_o         ),
1905
      .scl_padoen_o                  (scl1_padoen_o      ),
1906
      .sda_pad_i                     (i2c1_sda_io        ),
1907
      .sda_pad_o                     (sda1_pad_o         ),
1908
      .sda_padoen_o                  (sda1_padoen_o      ),
1909
 
1910
      // Interrupt
1911
      .wb_inta_o                     (i2c1_irq)
1912
 
1913
      );
1914
 
1915
   assign wbs_d_i2c1_err_o = 0;
1916
   assign wbs_d_i2c1_rty_o = 0;
1917
 
1918
   // i2c phy lines
1919
   assign i2c1_scl_io = scl1_padoen_o ? 1'bz : scl1_pad_o;
1920
   assign i2c1_sda_io = sda1_padoen_o ? 1'bz : sda1_pad_o;
1921
 
1922
   ////////////////////////////////////////////////////////////////////////
1923
`else // !`ifdef I2C1   
1924
 
1925
   assign wbs_d_i2c1_dat_o = 0;
1926
   assign wbs_d_i2c1_ack_o = 0;
1927
   assign wbs_d_i2c1_err_o = 0;
1928
   assign wbs_d_i2c1_rty_o = 0;
1929
 
1930
   ////////////////////////////////////////////////////////////////////////
1931
`endif // !`ifdef I2C1   
1932
 
1933
`ifdef I2C2
1934
   ////////////////////////////////////////////////////////////////////////
1935
   //
1936
   // i2c controller 2
1937
   // 
1938
   ////////////////////////////////////////////////////////////////////////
1939
 
1940
   //
1941
   // Wires
1942
   //
1943
   wire                              i2c2_irq;
1944
   wire                              scl2_pad_o;
1945
   wire                              scl2_padoen_o;
1946
   wire                              sda2_pad_o;
1947
   wire                              sda2_padoen_o;
1948
 
1949
   i2c_master_slave
1950
    #
1951
     (
1952
     .DEFAULT_SLAVE_ADDR(HV2_SADR)
1953
      )
1954
   hv_i2c_master_slave2
1955
     (
1956
      .wb_clk_i                         (wb_clk),
1957
      .wb_rst_i                         (wb_rst),
1958
      .arst_i                           (wb_rst),
1959
      .wb_adr_i                         (wbs_d_i2c2_adr_i[i2c_2_wb_adr_width-1:0]),
1960
      .wb_dat_i                         (wbs_d_i2c2_dat_i),
1961
      .wb_we_i                          (wbs_d_i2c2_we_i ),
1962
      .wb_cyc_i                         (wbs_d_i2c2_cyc_i),
1963
      .wb_stb_i                         (wbs_d_i2c2_stb_i),
1964
      .wb_dat_o                         (wbs_d_i2c2_dat_o),
1965
      .wb_ack_o                         (wbs_d_i2c2_ack_o),
1966
      .scl_pad_i                        (i2c2_scl_io     ),
1967
      .scl_pad_o                        (scl2_pad_o      ),
1968
      .scl_padoen_o                     (scl2_padoen_o   ),
1969
      .sda_pad_i                        (i2c2_sda_io     ),
1970
      .sda_pad_o                        (sda2_pad_o      ),
1971
      .sda_padoen_o                     (sda2_padoen_o   ),
1972
 
1973
      // Interrupt
1974
      .wb_inta_o                        (i2c2_irq)
1975
 
1976
      );
1977
 
1978
   assign wbs_d_i2c2_err_o = 0;
1979
   assign wbs_d_i2c2_rty_o = 0;
1980
 
1981
   // i2c phy lines
1982
   assign i2c2_sda_io = scl2_padoen_o ? 1'bz : scl2_pad_o;
1983
   assign i2c2_scl_io = sda2_padoen_o ? 1'bz : sda2_pad_o;
1984
 
1985
   ////////////////////////////////////////////////////////////////////////   
1986
 
1987
`else // !`ifdef I2C2   
1988
 
1989
   assign wbs_d_i2c2_dat_o = 0;
1990
   assign wbs_d_i2c2_ack_o = 0;
1991
   assign wbs_d_i2c2_err_o = 0;
1992
   assign wbs_d_i2c2_rty_o = 0;
1993
 
1994
   ////////////////////////////////////////////////////////////////////////
1995
 
1996
`endif // !`ifdef I2C2   
1997
 
1998
`ifdef I2C3
1999
   ////////////////////////////////////////////////////////////////////////
2000
   //
2001
   // i2c controller 3
2002
   // 
2003
   ////////////////////////////////////////////////////////////////////////
2004
 
2005
   //
2006
   // Wires
2007
   //
2008
   wire                              i2c3_irq;
2009
   wire                              scl3_pad_o;
2010
   wire                              scl3_padoen_o;
2011
   wire                              sda3_pad_o;
2012
   wire                              sda3_padoen_o;
2013
 
2014
   hv_i2c_master_slave
2015
         #
2016
     (
2017
     .DEFAULT_SLAVE_ADDR(HV3_SADR)
2018
      )
2019
     hv_i2c_master_slave3
2020
     (
2021
      .wb_clk_i                         (wb_clk),
2022
      .wb_rst_i                         (wb_rst),
2023
      .arst_i                           (wb_rst),
2024
      .wb_adr_i                         (wbs_d_i2c3_adr_i[i2c_3_wb_adr_width-1:0]),
2025
      .wb_dat_i                         (wbs_d_i2c3_dat_i),
2026
      .wb_we_i                          (wbs_d_i2c3_we_i ),
2027
      .wb_cyc_i                         (wbs_d_i2c3_cyc_i),
2028
      .wb_stb_i                         (wbs_d_i2c3_stb_i),
2029
      .wb_dat_o                         (wbs_d_i2c3_dat_o),
2030
      .wb_ack_o                         (wbs_d_i2c3_ack_o),
2031
      .scl_pad_i                        (i2c3_scl_io     ),
2032
      .scl_pad_o                        (scl3_pad_o      ),
2033
      .scl_padoen_o                     (scl3_padoen_o   ),
2034
      .sda_pad_i                        (i2c3_sda_io     ),
2035
      .sda_pad_o                        (sda3_pad_o      ),
2036
      .sda_padoen_o                     (sda3_padoen_o   ),
2037
 
2038
      // Interrupt
2039
      .wb_inta_o                        (i2c3_irq)
2040
 
2041
      );
2042
 
2043
   assign wbs_d_i2c3_err_o = 0;
2044
   assign wbs_d_i2c3_rty_o = 0;
2045
 
2046
   // i2c phy lines  
2047
   assign i2c3_sda_io = scl3_padoen_o ? 1'bz : scl3_pad_o;
2048
   assign i2c3_scl_io = sda3_padoen_o ? 1'bz : sda3_pad_o;
2049
 
2050
   ////////////////////////////////////////////////////////////////////////
2051
`else // !`ifdef I2C3
2052
 
2053
   assign wbs_d_i2c3_dat_o = 0;
2054
   assign wbs_d_i2c3_ack_o = 0;
2055
   assign wbs_d_i2c3_err_o = 0;
2056
   assign wbs_d_i2c3_rty_o = 0;
2057
 
2058
   ////////////////////////////////////////////////////////////////////////
2059
`endif // !`ifdef I2C3
2060
 
2061
`ifdef USB0
2062
   ////////////////////////////////////////////////////////////////////////
2063
   //
2064
   // USB Host/Slave controller 0
2065
   // 
2066
   ////////////////////////////////////////////////////////////////////////
2067
 
2068
   //
2069
   // Wires
2070
   //
2071
   wire                              usb0_slavesofrxed_irq;
2072
   wire                              usb0_slaveresetevent_irq;
2073
   wire                              usb0_slaveresume_irq;
2074
   wire                              usb0_slavetransdone_irq;
2075
   wire                              usb0_slavenaksent_irq;
2076
   wire                              usb0_slavevbusdet_irq;
2077
   wire                              usb0_hostSOFSentIntOut;
2078
   wire                              usb0_hostConnEventIntOut;
2079
   wire                              usb0_hostResumeIntOut;
2080
   wire                              usb0_hostTransDoneIntOut;
2081
   wire                              usb0_host_irq, usb0_slave_irq;
2082
   wire                              usb0_oe;
2083
   wire [1:0]                         usb0dat_o_int;
2084
 
2085
 
2086
   //
2087
   // Registers
2088
   //
2089
   reg [1:0]                          usb0_rx_data  /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
2090
   reg [1:0]                          usb0_tx_data /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
2091
   reg                               usb0_oe_n  /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
2092
 
2093
   always @(posedge usb_clk) usb0_rx_data <= usb0dat_pad_i;
2094
   always @(posedge usb_clk) usb0_tx_data <= usb0dat_o_int;
2095
   always @(posedge usb_clk) usb0_oe_n <= ~usb0_oe;
2096
 
2097
 
2098
   //
2099
   // Assigns
2100
   //
2101
   assign usb0dat_pad_o = usb0_tx_data;
2102
   assign usb0ctrl_pad_o = usb0_oe_n; // Actual oe to transciever
2103
   assign usb0_host_irq = usb0_hostSOFSentIntOut | usb0_hostConnEventIntOut |
2104
                         usb0_hostResumeIntOut | usb0_hostTransDoneIntOut;
2105
   assign usb0_slave_irq = usb0_slavesofrxed_irq | usb0_slaveresetevent_irq |
2106
                          usb0_slaveresume_irq | usb0_slavetransdone_irq |
2107
                          usb0_slavenaksent_irq/* | usb0_slavevbusdet_irq */;
2108
 
2109
`ifdef USB0_ONLY_HOST
2110
   usbhost usbhost0
2111
`else
2112
     usbhostslave usbhostslave0
2113
`endif
2114
 
2115
     (
2116
      // USB PHY lines
2117
      // In
2118
      .usbClk                           (usb_clk), // logic clock,48MHz +/-0.25%
2119
      .USBWireDataIn                    (usb0_rx_data), // Diff. data in
2120
      // Out
2121
      .USBWireDataOut                   (usb0dat_o_int), // Diff. dat out
2122
      .USBWireCtrlOut                   (usb0_oe),     // OE
2123
      .USBFullSpeed                     (usb0fullspeed_pad_o),// Full speed en.
2124
      //Debug   
2125
      .USBWireDataOutTick               (), // Debug output
2126
      .USBWireDataInTick                (),  // Debug ouptut
2127
 
2128
      // Interrupt lines
2129
      // Slave
2130
`ifndef USB0_ONLY_HOST
2131
      .slaveSOFRxedIntOut               (usb0_slavesofrxed_irq),
2132
      .slaveResetEventIntOut            (usb0_slaveresetevent_irq),
2133
      .slaveResumeIntOut                (usb0_slaveresume_irq),
2134
      .slaveTransDoneIntOut             (usb0_slavetransdone_irq),
2135
      .slaveNAKSentIntOut               (usb0_slavenaksent_irq),
2136
      .USBDPlusPullup                   (),
2137
      .USBDMinusPullup                  (),
2138
      .vBusDetect                       (1'b1), // bus detect from phy
2139
`endif
2140
 
2141
      // Host
2142
      .hostSOFSentIntOut                (usb0_hostSOFSentIntOut),
2143
      .hostConnEventIntOut              (usb0_hostConnEventIntOut),
2144
      .hostResumeIntOut                 (usb0_hostResumeIntOut),
2145
      .hostTransDoneIntOut              (usb0_hostTransDoneIntOut),
2146
      // Wishbone slave interface
2147
      .address_i                        (wbs_d_usb0_adr_i[wbs_d_usb0_adr_width-1:0]),
2148
      .data_i                           (wbs_d_usb0_dat_i),
2149
      .we_i                             (wbs_d_usb0_we_i),
2150
      .strobe_i                         (wbs_d_usb0_stb_i),
2151
      .data_o                           (wbs_d_usb0_dat_o),
2152
      .ack_o                            (wbs_d_usb0_ack_o),
2153
      .clk_i                            (wb_clk),
2154
      .rst_i                            (wb_rst)
2155
 
2156
      );
2157
 
2158
   assign wbs_d_usb0_err_o = 0;
2159
   assign wbs_d_usb0_rty_o = 0;
2160
 
2161
`ifdef USB0_ONLY_HOST
2162
   // Tie off unused IRQs if we're only a host
2163
   assign usb0_slavesofrxed_irq = 0;
2164
   assign usb0_slaveresetevent_irq = 0;
2165
   assign usb0_slaveresume_irq = 0;
2166
   assign usb0_slavetransdone_irq = 0;
2167
   assign usb0_slavenaksent_irq = 0;
2168
   assign usb0_slavevbusdet_irq = 0;
2169
`endif
2170
 
2171
`else
2172
 
2173
   assign wbs_d_usb0_dat_o = 0;
2174
   assign wbs_d_usb0_ack_o = 0;
2175
   assign wbs_d_usb0_err_o = 0;
2176
   assign wbs_d_usb0_rty_o = 0;
2177
 
2178
`endif // !`ifdef USB0
2179
 
2180
`ifdef USB1
2181
   ////////////////////////////////////////////////////////////////////////
2182
   //
2183
   // USB Host/Slave controller 1
2184
   // 
2185
   ////////////////////////////////////////////////////////////////////////
2186
 
2187
   //
2188
   // Wires
2189
   //
2190
   wire                              usb1_slavesofrxed_irq;
2191
   wire                              usb1_slaveresetevent_irq;
2192
   wire                              usb1_slaveresume_irq;
2193
   wire                              usb1_slavetransdone_irq;
2194
   wire                              usb1_slavenaksent_irq;
2195
   wire                              usb1_slavevbusdet_irq;
2196
   wire                              usb1_hostSOFSentIntOut;
2197
   wire                              usb1_hostConnEventIntOut;
2198
   wire                              usb1_hostResumeIntOut;
2199
   wire                              usb1_hostTransDoneIntOut;
2200
   wire                              usb1_host_irq, usb1_slave_irq;
2201
   wire                              usb1_oe;
2202
   wire [1:0]                         usb1dat_o_int;
2203
 
2204
 
2205
   //
2206
   // Registers
2207
   //
2208
   reg [1:0]                          usb1_rx_data  /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
2209
   reg [1:0]                          usb1_tx_data /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
2210
   reg                               usb1_oe_n  /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
2211
 
2212
   always @(posedge usb_clk) usb1_rx_data <= usb1dat_pad_i;
2213
   always @(posedge usb_clk) usb1_tx_data <= usb1dat_o_int;
2214
   always @(posedge usb_clk) usb1_oe_n <= ~usb1_oe;
2215
 
2216
 
2217
   //
2218
   // Assigns
2219
   //
2220
   assign usb1dat_pad_o = usb1_tx_data;
2221
   assign usb1ctrl_pad_o = usb1_oe_n; // Actual oe to transciever
2222
   assign usb1_host_irq = usb1_hostSOFSentIntOut | usb1_hostConnEventIntOut |
2223
                         usb1_hostResumeIntOut | usb1_hostTransDoneIntOut;
2224
   assign usb1_slave_irq = usb1_slavesofrxed_irq | usb1_slaveresetevent_irq |
2225
                          usb1_slaveresume_irq | usb1_slavetransdone_irq |
2226
                          usb1_slavenaksent_irq /*| usb1_slavevbusdet_irq*/ ;
2227
 
2228
`ifdef USB1_ONLY_HOST
2229
   usbhost usbhost1
2230
`else
2231
 `ifdef USB1_ONLY_SLAVE
2232
   usbslave usbslave1
2233
 `else
2234
   usbhostslave usbhostslave1
2235
 `endif
2236
`endif
2237
     (
2238
      // USB PHY lines
2239
      // In
2240
      .usbClk                           (usb_clk), // logic clock,48MHz +/-0.25%
2241
      .USBWireDataIn                    (usb1_rx_data), // Diff. data in
2242
      // Out
2243
      .USBWireDataOut                   (usb1dat_o_int), // Diff. dat out
2244
      .USBWireCtrlOut                   (usb1_oe),     // OE
2245
      .USBFullSpeed                     (usb1fullspeed_pad_o),// Full speed en.
2246
      //Debug   
2247
      .USBWireDataOutTick               (), // Debug output
2248
      .USBWireDataInTick                (),  // Debug ouptut    
2249
 
2250
      // Interrupt lines
2251
      // Slave
2252
`ifndef USB1_ONLY_HOST
2253
      .slaveSOFRxedIntOut               (usb1_slavesofrxed_irq),
2254
      .slaveResetEventIntOut            (usb1_slaveresetevent_irq),
2255
      .slaveResumeIntOut                (usb1_slaveresume_irq),
2256
      .slaveTransDoneIntOut             (usb1_slavetransdone_irq),
2257
      .slaveNAKSentIntOut               (usb1_slavenaksent_irq),
2258
      .slaveVBusDetIntOut               (usb1_slavevbusdet_irq),
2259
      .USBDPlusPullup                   (),
2260
      .USBDMinusPullup                  (),
2261
      .vBusDetect                       (1'b1), // bus detect from phy
2262
`endif
2263
`ifndef USB1_ONLY_SLAVE
2264
      // Host
2265
      .hostSOFSentIntOut                (usb1_hostSOFSentIntOut),
2266
      .hostConnEventIntOut              (usb1_hostConnEventIntOut),
2267
      .hostResumeIntOut                 (usb1_hostResumeIntOut),
2268
      .hostTransDoneIntOut              (usb1_hostTransDoneIntOut),
2269
`endif
2270
      // Wishbone slave interface
2271
      .address_i                        (wbs_d_usb1_adr_i[wbs_d_usb1_adr_width-1:0]),
2272
      .data_i                           (wbs_d_usb1_dat_i),
2273
      .we_i                             (wbs_d_usb1_we_i),
2274
      .strobe_i                         (wbs_d_usb1_stb_i),
2275
      .data_o                           (wbs_d_usb1_dat_o),
2276
      .ack_o                            (wbs_d_usb1_ack_o),
2277
      .clk_i                            (wb_clk),
2278
      .rst_i                            (wb_rst)
2279
 
2280
      );
2281
 
2282
   assign wbs_d_usb1_err_o = 0;
2283
   assign wbs_d_usb1_rty_o = 0;
2284
 
2285
`ifdef USB1_ONLY_HOST
2286
   // Tie off unused IRQs if we're only a host
2287
   assign usb1_slavesofrxed_irq = 0;
2288
   assign usb1_slaveresetevent_irq = 0;
2289
   assign usb1_slaveresume_irq = 0;
2290
   assign usb1_slavetransdone_irq = 0;
2291
   assign usb1_slavenaksent_irq = 0;
2292
   assign usb1_slavevbusdet_irq = 0;
2293
`endif
2294
`ifdef USB1_ONLY_SLAVE
2295
   assign usb1_hostSOFSentIntOut  = 0;
2296
   assign usb1_hostConnEventIntOut = 0;
2297
   assign usb1_hostResumeIntOut = 0;
2298
   assign usb1_hostTransDoneIntOut = 0;
2299
`endif
2300
 
2301
`else
2302
 
2303
   assign wbs_d_usb1_dat_o = 0;
2304
   assign wbs_d_usb1_ack_o = 0;
2305
   assign wbs_d_usb1_err_o = 0;
2306
   assign wbs_d_usb1_rty_o = 0;
2307
 
2308
`endif // !`ifdef USB1
2309
 
2310
`ifdef GPIO0
2311
   ////////////////////////////////////////////////////////////////////////
2312
   //
2313
   // GPIO 0
2314
   // 
2315
   ////////////////////////////////////////////////////////////////////////
2316
 
2317
   gpio gpio0
2318
     (
2319
      // GPIO bus
2320
      .gpio_io                          (gpio0_io[gpio0_io_width-1:0]),
2321
      // Wishbone slave interface
2322
      .wb_adr_i                         (wbs_d_gpio0_adr_i[gpio0_wb_adr_width-1:0]),
2323
      .wb_dat_i                         (wbs_d_gpio0_dat_i),
2324
      .wb_we_i                          (wbs_d_gpio0_we_i),
2325
      .wb_cyc_i                         (wbs_d_gpio0_cyc_i),
2326
      .wb_stb_i                         (wbs_d_gpio0_stb_i),
2327
      .wb_cti_i                         (wbs_d_gpio0_cti_i),
2328
      .wb_bte_i                         (wbs_d_gpio0_bte_i),
2329
      .wb_dat_o                         (wbs_d_gpio0_dat_o),
2330
      .wb_ack_o                         (wbs_d_gpio0_ack_o),
2331
      .wb_err_o                         (wbs_d_gpio0_err_o),
2332
      .wb_rty_o                         (wbs_d_gpio0_rty_o),
2333
 
2334
      .wb_clk                           (wb_clk),
2335
      .wb_rst                           (wb_rst)
2336
      );
2337
 
2338
   defparam gpio0.gpio_io_width = gpio0_io_width;
2339
   defparam gpio0.gpio_dir_reset_val = gpio0_dir_reset_val;
2340
   defparam gpio0.gpio_o_reset_val = gpio0_o_reset_val;
2341
 
2342
   ////////////////////////////////////////////////////////////////////////
2343
`else // !`ifdef GPIO0
2344
   assign wbs_d_gpio0_dat_o = 0;
2345
   assign wbs_d_gpio0_ack_o = 0;
2346
   assign wbs_d_gpio0_err_o = 0;
2347
   assign wbs_d_gpio0_rty_o = 0;
2348
   ////////////////////////////////////////////////////////////////////////
2349
`endif // !`ifdef GPIO0
2350
 
2351
   ////////////////////////////////////////////////////////////////////////
2352
   //
2353
   // OR1200 Interrupt assignment
2354
   // 
2355
   ////////////////////////////////////////////////////////////////////////
2356
 
2357
   assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200
2358
   assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200
2359
`ifdef UART0
2360
   assign or1200_pic_ints[2] = uart0_irq;
2361
`else
2362
   assign or1200_pic_ints[2] = 0;
2363
`endif
2364
`ifdef UART1
2365
   assign or1200_pic_ints[3] = uart1_irq;
2366
`else
2367
   assign or1200_pic_ints[3] = 0;
2368
`endif
2369
`ifdef ETH0
2370
   assign or1200_pic_ints[4] = eth0_irq;
2371
`else
2372
   assign or1200_pic_ints[4] = 0;
2373
`endif
2374
`ifdef UART2
2375
   assign or1200_pic_ints[5] = uart2_irq;
2376
`else
2377
   assign or1200_pic_ints[5] = 0;
2378
`endif
2379
`ifdef SPI0
2380
   assign or1200_pic_ints[6] = spi0_irq;
2381
`else
2382
   assign or1200_pic_ints[6] = 0;
2383
`endif
2384
`ifdef SPI1
2385
   assign or1200_pic_ints[7] = spi1_irq;
2386
`else
2387
   assign or1200_pic_ints[7] = 0;
2388
`endif
2389
`ifdef SPI2
2390
   assign or1200_pic_ints[8] = spi2_irq;
2391
`else
2392
   assign or1200_pic_ints[8] = 0;
2393
`endif
2394
   assign or1200_pic_ints[9] = 0;
2395
`ifdef I2C0
2396
   assign or1200_pic_ints[10] = i2c0_irq;
2397
`else
2398
   assign or1200_pic_ints[10] = 0;
2399
`endif
2400
`ifdef I2C1
2401
   assign or1200_pic_ints[11] = i2c1_irq;
2402
`else
2403
   assign or1200_pic_ints[11] = 0;
2404
`endif
2405
`ifdef I2C2
2406
   assign or1200_pic_ints[12] = i2c2_irq;
2407
`else
2408
   assign or1200_pic_ints[12] = 0;
2409
`endif
2410
`ifdef I2C3
2411
   assign or1200_pic_ints[13] = i2c3_irq;
2412
`else
2413
   assign or1200_pic_ints[13] = 0;
2414
`endif
2415
   assign or1200_pic_ints[14] = 0;
2416
   assign or1200_pic_ints[15] = 0;
2417
   assign or1200_pic_ints[16] = 0;
2418
   assign or1200_pic_ints[17] = 0;
2419
   assign or1200_pic_ints[18] = 0;
2420
   assign or1200_pic_ints[19] = 0;
2421
`ifdef USB0
2422
   assign or1200_pic_ints[20] = usb0_host_irq;
2423
   assign or1200_pic_ints[21] = usb0_slave_irq;
2424
`else
2425
   assign or1200_pic_ints[20] = 0;
2426
   assign or1200_pic_ints[21] = 0;
2427
`endif
2428
`ifdef USB1
2429
   assign or1200_pic_ints[22] = usb1_host_irq;
2430
   assign or1200_pic_ints[23] = usb1_slave_irq;
2431
`else
2432
   assign or1200_pic_ints[22] = 0;
2433
   assign or1200_pic_ints[23] = 0;
2434
`endif
2435
   assign or1200_pic_ints[24] = 0;
2436
   assign or1200_pic_ints[25] = 0;
2437
   assign or1200_pic_ints[26] = 0;
2438
   assign or1200_pic_ints[27] = 0;
2439
   assign or1200_pic_ints[28] = 0;
2440
   assign or1200_pic_ints[29] = 0;
2441
   assign or1200_pic_ints[30] = 0;
2442
 
2443
endmodule // orpsoc_top
2444
 
2445
 

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