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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [dcm_pll.v] - Blame information for rev 408

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1 408 julius 
`include "versatile_mem_ctrl_defines.v"
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module dcm_pll
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  (
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   input  rst,          // reset
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   input  clk_in,       // clock in
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   input  clkfb_in,     // feedback clock in
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   output clk0_out,     // clock out
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   output clk90_out,    // clock out, 90 degree phase shift
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   output clk180_out,   // clock out, 180 degree phase shift
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   output clk270_out,   // clock out, 270 degree phase shift
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   output clkfb_out     // feedback clock out
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   );
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`ifdef XILINX
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   wire clk_in_ibufg;
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   wire clk0_bufg, clk90_bufg, clk180_bufg, clk270_bufg;
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   // DCM with internal feedback
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   DCM #(
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      .CLKDV_DIVIDE(2.0),
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      .CLKFX_DIVIDE(1),
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      .CLKFX_MULTIPLY(4),
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      .CLKIN_DIVIDE_BY_2("FALSE"),
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      .CLKIN_PERIOD(8.0),
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      .CLKOUT_PHASE_SHIFT("NONE"),
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      .CLK_FEEDBACK("1X"),
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      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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      .DLL_FREQUENCY_MODE("LOW"),
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      .DUTY_CYCLE_CORRECTION("TRUE"),
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      .PHASE_SHIFT(0),
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      .STARTUP_WAIT("FALSE"))
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   DCM_internal (
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      .CLK0(clk0_bufg),
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      .CLK180(clk180_bufg),
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      .CLK270(clk270_bufg),
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      .CLK2X(),
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      .CLK2X180(),
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      .CLK90(clk90_bufg),
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      .CLKDV(),
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      .CLKFX(),
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      .CLKFX180(),
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      .LOCKED(),
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      .PSDONE(),
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      .STATUS(),
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      .CLKFB(clk0_out),
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      .CLKIN(clk_in_ibufg),
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      .DSSEN(),
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      .PSCLK(),
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      .PSEN(),
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      .PSINCDEC(),
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      .RST(rst)
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   );
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   // DCM with external feedback
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   DCM #(
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      .CLKDV_DIVIDE(2.0),
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      .CLKFX_DIVIDE(1),
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      .CLKFX_MULTIPLY(4),
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      .CLKIN_DIVIDE_BY_2("FALSE"),
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      .CLKIN_PERIOD(8.0),
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      .CLKOUT_PHASE_SHIFT("NONE"),
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      .CLK_FEEDBACK("1X"),
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      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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      .DLL_FREQUENCY_MODE("LOW"),
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      .DUTY_CYCLE_CORRECTION("TRUE"),
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      .PHASE_SHIFT(0),
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      .STARTUP_WAIT("FALSE"))
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   DCM_external (
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      .CLK0(clkfb_bufg),
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      .CLK180(),
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      .CLK270(),
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      .CLK2X(),
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      .CLK2X180(),
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      .CLK90(),
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      .CLKDV(),
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      .CLKFX(),
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      .CLKFX180(),
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      .LOCKED(),
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      .PSDONE(),
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      .STATUS(),
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      .CLKFB(clkfb_ibufg),
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      .CLKIN(clk_in_ibufg),
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      .DSSEN(),
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      .PSCLK(),
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      .PSEN(),
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      .PSINCDEC(),
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      .RST(rst)
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   );
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   // Input buffer on DCM clock source
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   IBUFG IBUFG_clk (
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     .I(clk_in),
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     .O(clk_in_ibufg));
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   // Global buffers on DCM generated clocks
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   BUFG BUFG_0 (
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     .I(clk0_bufg),
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     .O(clk0_out));
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   BUFG BUFG_90 (
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     .I(clk90_bufg),
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     .O(clk90_out));
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   BUFG BUFG_180 (
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     .I(clk180_bufg),
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     .O(clk180_out));
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   BUFG BUFG_270 (
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     .I(clk270_bufg),
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     .O(clk270_out));
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   // External feedback to DCM
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   IBUFG IBUFG_clkfb (
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     .I(clkfb_in),
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     .O(clkfb_ibufg));
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   OBUF OBUF_clkfb (
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     .I(clkfb_bufg),
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     .O(clkfb_out));
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`endif   // XILINX
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`ifdef ALTERA
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   wire [9:0] sub_wire0;
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   wire [0:0] sub_wire8 = 1'h0;
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   wire [3:3] sub_wire4 = sub_wire0[3:3];
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   wire [2:2] sub_wire3 = sub_wire0[2:2];
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   wire [1:1] sub_wire2 = sub_wire0[1:1];
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   wire [0:0] sub_wire1 = sub_wire0[0:0];
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   wire       sub_wire6 = clk_in;
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   wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
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   assign clk0_out   = sub_wire1;
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   assign clk90_out  = sub_wire2;
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   assign clk180_out = sub_wire3;
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   assign clk270_out = sub_wire4;
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   // PLL with external feedback
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   altpll #(
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     .bandwidth_type("AUTO"),
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     .clk0_divide_by(1),
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     .clk0_duty_cycle(50),
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     .clk0_multiply_by(1),
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     .clk0_phase_shift("0"),
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     .clk1_divide_by(1),
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     .clk1_duty_cycle(50),
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     .clk1_multiply_by(1),
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     .clk1_phase_shift("1250"),
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     .clk2_divide_by(1),
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     .clk2_duty_cycle(50),
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     .clk2_multiply_by(1),
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     .clk2_phase_shift("2500"),
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     .clk3_divide_by(1),
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     .clk3_duty_cycle(50),
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     .clk3_multiply_by(1),
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     .clk3_phase_shift("3750"),
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     .compensate_clock("CLK0"),
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     .inclk0_input_frequency(5000),
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     .intended_device_family("Stratix III"),
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     .lpm_hint("UNUSED"),
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     .lpm_type("altpll"),
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     .operation_mode("NORMAL"),
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//   .operation_mode("SOURCE_SYNCHRONOUS"),
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     .pll_type("AUTO"),
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     .port_activeclock("PORT_UNUSED"),
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     .port_areset("PORT_USED"),
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     .port_clkbad0("PORT_UNUSED"),
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     .port_clkbad1("PORT_UNUSED"),
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     .port_clkloss("PORT_UNUSED"),
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     .port_clkswitch("PORT_UNUSED"),
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     .port_configupdate("PORT_UNUSED"),
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     .port_fbin("PORT_USED"),
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     .port_fbout("PORT_USED"),
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     .port_inclk0("PORT_USED"),
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     .port_inclk1("PORT_UNUSED"),
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     .port_locked("PORT_UNUSED"),
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     .port_pfdena("PORT_UNUSED"),
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     .port_phasecounterselect("PORT_UNUSED"),
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     .port_phasedone("PORT_UNUSED"),
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     .port_phasestep("PORT_UNUSED"),
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     .port_phaseupdown("PORT_UNUSED"),
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     .port_pllena("PORT_UNUSED"),
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     .port_scanaclr("PORT_UNUSED"),
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     .port_scanclk("PORT_UNUSED"),
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     .port_scanclkena("PORT_UNUSED"),
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     .port_scandata("PORT_UNUSED"),
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     .port_scandataout("PORT_UNUSED"),
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     .port_scandone("PORT_UNUSED"),
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     .port_scanread("PORT_UNUSED"),
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     .port_scanwrite("PORT_UNUSED"),
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     .port_clk0("PORT_USED"),
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     .port_clk1("PORT_USED"),
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     .port_clk2("PORT_USED"),
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     .port_clk3("PORT_USED"),
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     .port_clk4("PORT_UNUSED"),
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     .port_clk5("PORT_UNUSED"),
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     .port_clk6("PORT_UNUSED"),
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     .port_clk7("PORT_UNUSED"),
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     .port_clk8("PORT_UNUSED"),
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     .port_clk9("PORT_UNUSED"),
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     .port_clkena0("PORT_UNUSED"),
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     .port_clkena1("PORT_UNUSED"),
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     .port_clkena2("PORT_UNUSED"),
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     .port_clkena3("PORT_UNUSED"),
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     .port_clkena4("PORT_UNUSED"),
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     .port_clkena5("PORT_UNUSED"),
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     .using_fbmimicbidir_port("OFF"),
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     .width_clock(10))
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   altpll_internal (
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     .fbin (),//(clkfb_in),
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     .inclk (sub_wire7),
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     .areset (rst),
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     .clk (sub_wire0),
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     .fbout (),//(clkfb_out),
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     .activeclock (),
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     .clkbad (),
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     .clkena ({6{1'b1}}),
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     .clkloss (),
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     .clkswitch (1'b0),
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     .configupdate (1'b0),
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     .enable0 (),
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     .enable1 (),
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     .extclk (),
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     .extclkena ({4{1'b1}}),
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     .fbmimicbidir (),
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     .locked (),
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     .pfdena (1'b1),
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     .phasecounterselect ({4{1'b1}}),
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     .phasedone (),
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     .phasestep (1'b1),
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     .phaseupdown (1'b1),
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     .pllena (1'b1),
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     .scanaclr (1'b0),
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     .scanclk (1'b0),
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     .scanclkena (1'b1),
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     .scandata (1'b0),
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     .scandataout (),
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     .scandone (),
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     .scanread (1'b0),
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     .scanwrite (1'b0),
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     .sclkout0 (),
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     .sclkout1 (),
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     .vcooverrange (),
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     .vcounderrange ()
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   );
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`endif   // ALTERA
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//`ifdef GENERIC_PRIMITIVES
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//`endif   // GENERIC_PRIMITIVES
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endmodule   // dcm_pll
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