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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [fifo.v] - Blame information for rev 408

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`include "versatile_mem_ctrl_defines.v"
 
module fifo
  (
   // A side
   input [35:0]  a_dat_i,
   input         a_we_i,
   input  [2:0]  a_fifo_sel_i,
   output [7:0]  a_fifo_full_o,
   input         a_clk,
   // B side
   output [35:0] b_dat_o,
   input         b_re_i,
   input [2:0]   b_fifo_sel_i,
   output [7:0]  b_fifo_empty_o,
   input         b_clk,
   // Common
   input         rst
   );
 
   wire [4:0]     wadr0, radr0;
   wire [4:0]     wadr1, radr1;
   wire [4:0]     wadr2, radr2;
   wire [4:0]     wadr3, radr3;
   wire [4:0]     wadr4, radr4;
   wire [4:0]     wadr5, radr5;
   wire [4:0]     wadr6, radr6;
   wire [4:0]     wadr7, radr7;
 
`ifdef PORT0
   wire [4:0]     wptr0, rptr0;
`endif
`ifdef PORT1
   wire [4:0]     wptr1, rptr1;
`endif
`ifdef PORT2
   wire [4:0]     wptr2, rptr2;
`endif
`ifdef PORT3
   wire [4:0]     wptr3, rptr3;
`endif
`ifdef PORT4
   wire [4:0]     wptr4, rptr4;
`endif
`ifdef PORT5
   wire [4:0]     wptr5, rptr5;
`endif
`ifdef PORT6
   wire [4:0]     wptr6, rptr6;
`endif
`ifdef PORT7
   wire [4:0]     wptr7, rptr7;
`endif
 
   wire [7:0]     dpram_a_a, dpram_a_b;
 
   // WB#0
`ifdef PORT0
   fifo_adr_counter wptr0_cnt
     (
      .q(wptr0),
      .q_bin(wadr0),
      .cke(a_we_i & (a_fifo_sel_i==3'h0)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr0_cnt
     (
      .q(rptr0),
      .q_bin(radr0),
      .cke(b_re_i & (b_fifo_sel_i==3'h0)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp0
    (
      .wptr(wptr0),
      .rptr(rptr0),
      .fifo_empty(b_fifo_empty_o[0]),
      .fifo_full(a_fifo_full_o[0]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT0
   assign wptr0 = 5'h0;
   assign wadr0 = 5'h0;
   assign rptr0 = 5'h0;
   assign radr0 = 5'h0;
   assign a_fifo_full_o[0] = 1'b0;
   assign b_fifo_empty_o[0] = 1'b1;
`endif // !`ifdef PORT0
 
   // WB#1
`ifdef PORT1
   fifo_adr_counter wptr1_cnt
     (
      .q(wptr1),
      .q_bin(wadr1),
      .cke(a_we_i & (a_fifo_sel_i==3'h1)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr1_cnt
     (
      .q(rptr1),
      .q_bin(radr1),
      .cke(b_re_i & (b_fifo_sel_i==3'h1)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp1
    (
      .wptr(wptr1),
      .rptr(rptr1),
      .fifo_empty(b_fifo_empty_o[1]),
      .fifo_full(a_fifo_full_o[1]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT1
   assign wptr1 = 5'h0;
   assign wadr1 = 5'h0;
   assign rptr1 = 5'h0;
   assign radr1 = 5'h0;
   assign a_fifo_full_o[1] = 1'b0;
   assign b_fifo_empty_o[1] = 1'b1;
`endif // !`ifdef PORT1
 
   // WB#2
`ifdef PORT2
   fifo_adr_counter wptr2_cnt
     (
      .q(wptr2),
      .q_bin(wadr2),
      .cke(a_we_i & (a_fifo_sel_i==3'h2)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr2_cnt
     (
      .q(rptr2),
      .q_bin(radr2),
      .cke(b_re_i & (b_fifo_sel_i==3'h2)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp2
    (
      .wptr(wptr2),
      .rptr(rptr2),
      .fifo_empty(b_fifo_empty_o[2]),
      .fifo_full(a_fifo_full_o[2]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT2
   assign wptr2 = 5'h0;
   assign wadr2 = 5'h0;
   assign rptr2 = 5'h0;
   assign radr2 = 5'h0;
   assign a_fifo_full_o[2] = 1'b0;
   assign b_fifo_empty_o[2] = 1'b1;
`endif // !`ifdef PORT2
 
   // WB#3
`ifdef PORT3
   fifo_adr_counter wptr3_cnt
     (
      .q(wptr3),
      .q_bin(wadr3),
      .cke(a_we_i & (a_fifo_sel_i==3'h3)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr3_cnt
     (
      .q(rptr3),
      .q_bin(radr3),
      .cke(b_re_i & (b_fifo_sel_i==3'h3)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp3
    (
      .wptr(wptr3),
      .rptr(rptr3),
      .fifo_empty(b_fifo_empty_o[3]),
      .fifo_full(a_fifo_full_o[3]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT3
   assign wptr3 = 5'h0;
   assign wadr3 = 5'h0;
   assign rptr3 = 5'h0;
   assign radr3 = 5'h0;
   assign a_fifo_full_o[3] = 1'b0;
   assign b_fifo_empty_o[3] = 1'b1;
`endif // !`ifdef PORT3
 
   // WB#4
`ifdef PORT4
   fifo_adr_counter wptr4_cnt
     (
      .q(wptr4),
      .q_bin(wadr4),
      .cke(a_we_i & (a_fifo_sel_i==3'h4)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr4_cnt
     (
      .q(rptr4),
      .q_bin(radr4),
      .cke(b_re_i & (b_fifo_sel_i==3'h4)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp4
    (
      .wptr(wptr4),
      .rptr(rptr4),
      .fifo_empty(b_fifo_empty_o[4]),
      .fifo_full(a_fifo_full_o[4]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT4
   assign wptr4 = 5'h0;
   assign wadr4 = 5'h0;
   assign rptr4 = 5'h0;
   assign radr4 = 5'h0;
   assign a_fifo_full_o[4] = 1'b0;
   assign b_fifo_empty_o[4] = 1'b1;
`endif // !`ifdef PORT4
 
   // WB#5
`ifdef PORT5
   fifo_adr_counter wptr5_cnt
     (
      .q(wptr5),
      .q_bin(wadr5),
      .cke(a_we_i & (a_fifo_sel_i==3'h5)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr5_cnt
     (
      .q(rptr5),
      .q_bin(radr5),
      .cke(b_re_i & (b_fifo_sel_i==3'h5)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp5
    (
      .wptr(wptr5),
      .rptr(rptr5),
      .fifo_empty(b_fifo_empty_o[5]),
      .fifo_full(a_fifo_full_o[5]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT5
   assign wptr5 = 5'h0;
   assign wadr5 = 5'h0;
   assign rptr5 = 5'h0;
   assign radr5 = 5'h0;
   assign a_fifo_full_o[5] = 1'b0;
   assign b_fifo_empty_o[5] = 1'b1;
`endif // !`ifdef PORT5
 
   // WB#6
`ifdef PORT6
   fifo_adr_counter wptr6_cnt
     (
      .q(wptr6),
      .q_bin(wadr6),
      .cke(a_we_i & (a_fifo_sel_i==3'h6)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr6_cnt
     (
      .q(rptr6),
      .q_bin(radr6),
      .cke(b_re_i & (b_fifo_sel_i==3'h6)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp6
    (
      .wptr(wptr6),
      .rptr(rptr6),
      .fifo_empty(b_fifo_empty_o[6]),
      .fifo_full(a_fifo_full_o[6]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT6
   assign wptr6 = 5'h0;
   assign wadr6 = 5'h0;
   assign rptr6 = 5'h0;
   assign radr6 = 5'h0;
   assign a_fifo_full_o[6] = 1'b0;
   assign b_fifo_empty_o[6] = 1'b1;
`endif // !`ifdef PORT6
 
   // WB#7
`ifdef PORT7
   fifo_adr_counter wptr7_cnt
     (
      .q(wptr7),
      .q_bin(wadr7),
      .cke(a_we_i & (a_fifo_sel_i==3'h7)),
      .clk(a_clk),
      .rst(rst)
      );
 
   fifo_adr_counter rptr7_cnt
     (
      .q(rptr7),
      .q_bin(radr7),
      .cke(b_re_i & (b_fifo_sel_i==3'h7)),
      .clk(b_clk),
      .rst(rst)
      );
 
  versatile_fifo_async_cmp
    #
    (
     .ADDR_WIDTH(5)
     )
    cmp7
    (
      .wptr(wptr7),
      .rptr(rptr7),
      .fifo_empty(b_fifo_empty_o[7]),
      .fifo_full(a_fifo_full_o[7]),
      .wclk(a_clk),
      .rclk(b_clk),
      .rst(rst)
      );
`else // !`ifdef PORT7
   assign wptr7 = 5'h0;
   assign wadr7 = 5'h0;
   assign rptr7 = 5'h0;
   assign radr7 = 5'h0;
   assign a_fifo_full_o[7] = 1'b0;
   assign b_fifo_empty_o[7] = 1'b1;
`endif // !`ifdef PORT7
 
   assign dpram_a_a = (a_fifo_sel_i==3'd0) ? {a_fifo_sel_i,wadr0} :
                      (a_fifo_sel_i==3'd1) ? {a_fifo_sel_i,wadr1} :
                      (a_fifo_sel_i==3'd2) ? {a_fifo_sel_i,wadr2} :
                      (a_fifo_sel_i==3'd3) ? {a_fifo_sel_i,wadr3} :
                      (a_fifo_sel_i==3'd4) ? {a_fifo_sel_i,wadr4} :
                      (a_fifo_sel_i==3'd5) ? {a_fifo_sel_i,wadr5} :
                      (a_fifo_sel_i==3'd6) ? {a_fifo_sel_i,wadr6} :
                                             {a_fifo_sel_i,wadr7} ;
 
   assign dpram_a_b = (b_fifo_sel_i==3'd0) ? {b_fifo_sel_i,radr0} :
                      (b_fifo_sel_i==3'd1) ? {b_fifo_sel_i,radr1} :
                      (b_fifo_sel_i==3'd2) ? {b_fifo_sel_i,radr2} :
                      (b_fifo_sel_i==3'd3) ? {b_fifo_sel_i,radr3} :
                      (b_fifo_sel_i==3'd4) ? {b_fifo_sel_i,radr4} :
                      (b_fifo_sel_i==3'd5) ? {b_fifo_sel_i,radr5} :
                      (b_fifo_sel_i==3'd6) ? {b_fifo_sel_i,radr6} :
                                             {b_fifo_sel_i,radr7} ;
 
 
`ifdef ACTEL
   TwoPortRAM_256x36 dpram
     (
      .WD(a_dat_i),
      .RD(b_dat_o),
      .WEN(a_we_i),
      //.REN(b_re_i),
      .REN(1'b1),
      .WADDR(dpram_a_a),
      .RADDR(dpram_a_b),
      .WCLK(a_clk),
      .RCLK(b_clk)
      );
`else
   vfifo_dual_port_ram_dc_dw
/*     #
     (
      .ADDR_WIDTH(8),
      .DATA_WIDTH(36)
      )*/
     dpram
     (
      .d_a(a_dat_i),
      .q_a(),
      .adr_a(dpram_a_a),
      .we_a(a_we_i),
      .clk_a(a_clk),
      .q_b(b_dat_o),
      .adr_b(dpram_a_b),
      .d_b(36'h0),
      .we_b(1'b0),
      .clk_b(b_clk)
      );
`endif
endmodule // sd_fifo

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [fifo.v] - Blame information for rev 408

Line No.	Rev	Author	Line
1	408	julius	`include "versatile_mem_ctrl_defines.v"
2
3			`module fifo`
4			`(`
5			`// A side`
6			`input [35:0] a_dat_i,`
7			`input a_we_i,`
8			`input [2:0] a_fifo_sel_i,`
9			`output [7:0] a_fifo_full_o,`
10			`input a_clk,`
11			`// B side`
12			`output [35:0] b_dat_o,`
13			`input b_re_i,`
14			`input [2:0] b_fifo_sel_i,`
15			`output [7:0] b_fifo_empty_o,`
16			`input b_clk,`
17			`// Common`
18			`input rst`
19			`);`
20
21			`wire [4:0] wadr0, radr0;`
22			`wire [4:0] wadr1, radr1;`
23			`wire [4:0] wadr2, radr2;`
24			`wire [4:0] wadr3, radr3;`
25			`wire [4:0] wadr4, radr4;`
26			`wire [4:0] wadr5, radr5;`
27			`wire [4:0] wadr6, radr6;`
28			`wire [4:0] wadr7, radr7;`
29
30			`ifdef PORT0
31			`wire [4:0] wptr0, rptr0;`
32			`endif
33			`ifdef PORT1
34			`wire [4:0] wptr1, rptr1;`
35			`endif
36			`ifdef PORT2
37			`wire [4:0] wptr2, rptr2;`
38			`endif
39			`ifdef PORT3
40			`wire [4:0] wptr3, rptr3;`
41			`endif
42			`ifdef PORT4
43			`wire [4:0] wptr4, rptr4;`
44			`endif
45			`ifdef PORT5
46			`wire [4:0] wptr5, rptr5;`
47			`endif
48			`ifdef PORT6
49			`wire [4:0] wptr6, rptr6;`
50			`endif
51			`ifdef PORT7
52			`wire [4:0] wptr7, rptr7;`
53			`endif
54
55			`wire [7:0] dpram_a_a, dpram_a_b;`
56
57			`// WB#0`
58			`ifdef PORT0
59			`fifo_adr_counter wptr0_cnt`
60			`(`
61			`.q(wptr0),`
62			`.q_bin(wadr0),`
63			`.cke(a_we_i & (a_fifo_sel_i==3'h0)),`
64			`.clk(a_clk),`
65			`.rst(rst)`
66			`);`
67
68			`fifo_adr_counter rptr0_cnt`
69			`(`
70			`.q(rptr0),`
71			`.q_bin(radr0),`
72			`.cke(b_re_i & (b_fifo_sel_i==3'h0)),`
73			`.clk(b_clk),`
74			`.rst(rst)`
75			`);`
76
77			`versatile_fifo_async_cmp`
78			`#`
79			`(`
80			`.ADDR_WIDTH(5)`
81			`)`
82			`cmp0`
83			`(`
84			`.wptr(wptr0),`
85			`.rptr(rptr0),`
86			`.fifo_empty(b_fifo_empty_o[0]),`
87			`.fifo_full(a_fifo_full_o[0]),`
88			`.wclk(a_clk),`
89			`.rclk(b_clk),`
90			`.rst(rst)`
91			`);`
92			`else // !`ifdef PORT0
93			`assign wptr0 = 5'h0;`
94			`assign wadr0 = 5'h0;`
95			`assign rptr0 = 5'h0;`
96			`assign radr0 = 5'h0;`
97			`assign a_fifo_full_o[0] = 1'b0;`
98			`assign b_fifo_empty_o[0] = 1'b1;`
99			`endif // !`ifdef PORT0
100
101			`// WB#1`
102			`ifdef PORT1
103			`fifo_adr_counter wptr1_cnt`
104			`(`
105			`.q(wptr1),`
106			`.q_bin(wadr1),`
107			`.cke(a_we_i & (a_fifo_sel_i==3'h1)),`
108			`.clk(a_clk),`
109			`.rst(rst)`
110			`);`
111
112			`fifo_adr_counter rptr1_cnt`
113			`(`
114			`.q(rptr1),`
115			`.q_bin(radr1),`
116			`.cke(b_re_i & (b_fifo_sel_i==3'h1)),`
117			`.clk(b_clk),`
118			`.rst(rst)`
119			`);`
120
121			`versatile_fifo_async_cmp`
122			`#`
123			`(`
124			`.ADDR_WIDTH(5)`
125			`)`
126			`cmp1`
127			`(`
128			`.wptr(wptr1),`
129			`.rptr(rptr1),`
130			`.fifo_empty(b_fifo_empty_o[1]),`
131			`.fifo_full(a_fifo_full_o[1]),`
132			`.wclk(a_clk),`
133			`.rclk(b_clk),`
134			`.rst(rst)`
135			`);`
136			`else // !`ifdef PORT1
137			`assign wptr1 = 5'h0;`
138			`assign wadr1 = 5'h0;`
139			`assign rptr1 = 5'h0;`
140			`assign radr1 = 5'h0;`
141			`assign a_fifo_full_o[1] = 1'b0;`
142			`assign b_fifo_empty_o[1] = 1'b1;`
143			`endif // !`ifdef PORT1
144
145			`// WB#2`
146			`ifdef PORT2
147			`fifo_adr_counter wptr2_cnt`
148			`(`
149			`.q(wptr2),`
150			`.q_bin(wadr2),`
151			`.cke(a_we_i & (a_fifo_sel_i==3'h2)),`
152			`.clk(a_clk),`
153			`.rst(rst)`
154			`);`
155
156			`fifo_adr_counter rptr2_cnt`
157			`(`
158			`.q(rptr2),`
159			`.q_bin(radr2),`
160			`.cke(b_re_i & (b_fifo_sel_i==3'h2)),`
161			`.clk(b_clk),`
162			`.rst(rst)`
163			`);`
164
165			`versatile_fifo_async_cmp`
166			`#`
167			`(`
168			`.ADDR_WIDTH(5)`
169			`)`
170			`cmp2`
171			`(`
172			`.wptr(wptr2),`
173			`.rptr(rptr2),`
174			`.fifo_empty(b_fifo_empty_o[2]),`
175			`.fifo_full(a_fifo_full_o[2]),`
176			`.wclk(a_clk),`
177			`.rclk(b_clk),`
178			`.rst(rst)`
179			`);`
180			`else // !`ifdef PORT2
181			`assign wptr2 = 5'h0;`
182			`assign wadr2 = 5'h0;`
183			`assign rptr2 = 5'h0;`
184			`assign radr2 = 5'h0;`
185			`assign a_fifo_full_o[2] = 1'b0;`
186			`assign b_fifo_empty_o[2] = 1'b1;`
187			`endif // !`ifdef PORT2
188
189			`// WB#3`
190			`ifdef PORT3
191			`fifo_adr_counter wptr3_cnt`
192			`(`
193			`.q(wptr3),`
194			`.q_bin(wadr3),`
195			`.cke(a_we_i & (a_fifo_sel_i==3'h3)),`
196			`.clk(a_clk),`
197			`.rst(rst)`
198			`);`
199
200			`fifo_adr_counter rptr3_cnt`
201			`(`
202			`.q(rptr3),`
203			`.q_bin(radr3),`
204			`.cke(b_re_i & (b_fifo_sel_i==3'h3)),`
205			`.clk(b_clk),`
206			`.rst(rst)`
207			`);`
208
209			`versatile_fifo_async_cmp`
210			`#`
211			`(`
212			`.ADDR_WIDTH(5)`
213			`)`
214			`cmp3`
215			`(`
216			`.wptr(wptr3),`
217			`.rptr(rptr3),`
218			`.fifo_empty(b_fifo_empty_o[3]),`
219			`.fifo_full(a_fifo_full_o[3]),`
220			`.wclk(a_clk),`
221			`.rclk(b_clk),`
222			`.rst(rst)`
223			`);`
224			`else // !`ifdef PORT3
225			`assign wptr3 = 5'h0;`
226			`assign wadr3 = 5'h0;`
227			`assign rptr3 = 5'h0;`
228			`assign radr3 = 5'h0;`
229			`assign a_fifo_full_o[3] = 1'b0;`
230			`assign b_fifo_empty_o[3] = 1'b1;`
231			`endif // !`ifdef PORT3
232
233			`// WB#4`
234			`ifdef PORT4
235			`fifo_adr_counter wptr4_cnt`
236			`(`
237			`.q(wptr4),`
238			`.q_bin(wadr4),`
239			`.cke(a_we_i & (a_fifo_sel_i==3'h4)),`
240			`.clk(a_clk),`
241			`.rst(rst)`
242			`);`
243
244			`fifo_adr_counter rptr4_cnt`
245			`(`
246			`.q(rptr4),`
247			`.q_bin(radr4),`
248			`.cke(b_re_i & (b_fifo_sel_i==3'h4)),`
249			`.clk(b_clk),`
250			`.rst(rst)`
251			`);`
252
253			`versatile_fifo_async_cmp`
254			`#`
255			`(`
256			`.ADDR_WIDTH(5)`
257			`)`
258			`cmp4`
259			`(`
260			`.wptr(wptr4),`
261			`.rptr(rptr4),`
262			`.fifo_empty(b_fifo_empty_o[4]),`
263			`.fifo_full(a_fifo_full_o[4]),`
264			`.wclk(a_clk),`
265			`.rclk(b_clk),`
266			`.rst(rst)`
267			`);`
268			`else // !`ifdef PORT4
269			`assign wptr4 = 5'h0;`
270			`assign wadr4 = 5'h0;`
271			`assign rptr4 = 5'h0;`
272			`assign radr4 = 5'h0;`
273			`assign a_fifo_full_o[4] = 1'b0;`
274			`assign b_fifo_empty_o[4] = 1'b1;`
275			`endif // !`ifdef PORT4
276
277			`// WB#5`
278			`ifdef PORT5
279			`fifo_adr_counter wptr5_cnt`
280			`(`
281			`.q(wptr5),`
282			`.q_bin(wadr5),`
283			`.cke(a_we_i & (a_fifo_sel_i==3'h5)),`
284			`.clk(a_clk),`
285			`.rst(rst)`
286			`);`
287
288			`fifo_adr_counter rptr5_cnt`
289			`(`
290			`.q(rptr5),`
291			`.q_bin(radr5),`
292			`.cke(b_re_i & (b_fifo_sel_i==3'h5)),`
293			`.clk(b_clk),`
294			`.rst(rst)`
295			`);`
296
297			`versatile_fifo_async_cmp`
298			`#`
299			`(`
300			`.ADDR_WIDTH(5)`
301			`)`
302			`cmp5`
303			`(`
304			`.wptr(wptr5),`
305			`.rptr(rptr5),`
306			`.fifo_empty(b_fifo_empty_o[5]),`
307			`.fifo_full(a_fifo_full_o[5]),`
308			`.wclk(a_clk),`
309			`.rclk(b_clk),`
310			`.rst(rst)`
311			`);`
312			`else // !`ifdef PORT5
313			`assign wptr5 = 5'h0;`
314			`assign wadr5 = 5'h0;`
315			`assign rptr5 = 5'h0;`
316			`assign radr5 = 5'h0;`
317			`assign a_fifo_full_o[5] = 1'b0;`
318			`assign b_fifo_empty_o[5] = 1'b1;`
319			`endif // !`ifdef PORT5
320
321			`// WB#6`
322			`ifdef PORT6
323			`fifo_adr_counter wptr6_cnt`
324			`(`
325			`.q(wptr6),`
326			`.q_bin(wadr6),`
327			`.cke(a_we_i & (a_fifo_sel_i==3'h6)),`
328			`.clk(a_clk),`
329			`.rst(rst)`
330			`);`
331
332			`fifo_adr_counter rptr6_cnt`
333			`(`
334			`.q(rptr6),`
335			`.q_bin(radr6),`
336			`.cke(b_re_i & (b_fifo_sel_i==3'h6)),`
337			`.clk(b_clk),`
338			`.rst(rst)`
339			`);`
340
341			`versatile_fifo_async_cmp`
342			`#`
343			`(`
344			`.ADDR_WIDTH(5)`
345			`)`
346			`cmp6`
347			`(`
348			`.wptr(wptr6),`
349			`.rptr(rptr6),`
350			`.fifo_empty(b_fifo_empty_o[6]),`
351			`.fifo_full(a_fifo_full_o[6]),`
352			`.wclk(a_clk),`
353			`.rclk(b_clk),`
354			`.rst(rst)`
355			`);`
356			`else // !`ifdef PORT6
357			`assign wptr6 = 5'h0;`
358			`assign wadr6 = 5'h0;`
359			`assign rptr6 = 5'h0;`
360			`assign radr6 = 5'h0;`
361			`assign a_fifo_full_o[6] = 1'b0;`
362			`assign b_fifo_empty_o[6] = 1'b1;`
363			`endif // !`ifdef PORT6
364
365			`// WB#7`
366			`ifdef PORT7
367			`fifo_adr_counter wptr7_cnt`
368			`(`
369			`.q(wptr7),`
370			`.q_bin(wadr7),`
371			`.cke(a_we_i & (a_fifo_sel_i==3'h7)),`
372			`.clk(a_clk),`
373			`.rst(rst)`
374			`);`
375
376			`fifo_adr_counter rptr7_cnt`
377			`(`
378			`.q(rptr7),`
379			`.q_bin(radr7),`
380			`.cke(b_re_i & (b_fifo_sel_i==3'h7)),`
381			`.clk(b_clk),`
382			`.rst(rst)`
383			`);`
384
385			`versatile_fifo_async_cmp`
386			`#`
387			`(`
388			`.ADDR_WIDTH(5)`
389			`)`
390			`cmp7`
391			`(`
392			`.wptr(wptr7),`
393			`.rptr(rptr7),`
394			`.fifo_empty(b_fifo_empty_o[7]),`
395			`.fifo_full(a_fifo_full_o[7]),`
396			`.wclk(a_clk),`
397			`.rclk(b_clk),`
398			`.rst(rst)`
399			`);`
400			`else // !`ifdef PORT7
401			`assign wptr7 = 5'h0;`
402			`assign wadr7 = 5'h0;`
403			`assign rptr7 = 5'h0;`
404			`assign radr7 = 5'h0;`
405			`assign a_fifo_full_o[7] = 1'b0;`
406			`assign b_fifo_empty_o[7] = 1'b1;`
407			`endif // !`ifdef PORT7
408
409			`assign dpram_a_a = (a_fifo_sel_i==3'd0) ? {a_fifo_sel_i,wadr0} :`
410			`(a_fifo_sel_i==3'd1) ? {a_fifo_sel_i,wadr1} :`
411			`(a_fifo_sel_i==3'd2) ? {a_fifo_sel_i,wadr2} :`
412			`(a_fifo_sel_i==3'd3) ? {a_fifo_sel_i,wadr3} :`
413			`(a_fifo_sel_i==3'd4) ? {a_fifo_sel_i,wadr4} :`
414			`(a_fifo_sel_i==3'd5) ? {a_fifo_sel_i,wadr5} :`
415			`(a_fifo_sel_i==3'd6) ? {a_fifo_sel_i,wadr6} :`
416			`{a_fifo_sel_i,wadr7} ;`
417
418			`assign dpram_a_b = (b_fifo_sel_i==3'd0) ? {b_fifo_sel_i,radr0} :`
419			`(b_fifo_sel_i==3'd1) ? {b_fifo_sel_i,radr1} :`
420			`(b_fifo_sel_i==3'd2) ? {b_fifo_sel_i,radr2} :`
421			`(b_fifo_sel_i==3'd3) ? {b_fifo_sel_i,radr3} :`
422			`(b_fifo_sel_i==3'd4) ? {b_fifo_sel_i,radr4} :`
423			`(b_fifo_sel_i==3'd5) ? {b_fifo_sel_i,radr5} :`
424			`(b_fifo_sel_i==3'd6) ? {b_fifo_sel_i,radr6} :`
425			`{b_fifo_sel_i,radr7} ;`
426
427
428			`ifdef ACTEL
429			`TwoPortRAM_256x36 dpram`
430			`(`
431			`.WD(a_dat_i),`
432			`.RD(b_dat_o),`
433			`.WEN(a_we_i),`
434			`//.REN(b_re_i),`
435			`.REN(1'b1),`
436			`.WADDR(dpram_a_a),`
437			`.RADDR(dpram_a_b),`
438			`.WCLK(a_clk),`
439			`.RCLK(b_clk)`
440			`);`
441			`else
442			`vfifo_dual_port_ram_dc_dw`
443			`/* #`
444			`(`
445			`.ADDR_WIDTH(8),`
446			`.DATA_WIDTH(36)`
447			`)*/`
448			`dpram`
449			`(`
450			`.d_a(a_dat_i),`
451			`.q_a(),`
452			`.adr_a(dpram_a_a),`
453			`.we_a(a_we_i),`
454			`.clk_a(a_clk),`
455			`.q_b(b_dat_o),`
456			`.adr_b(dpram_a_b),`
457			`.d_b(36'h0),`
458			`.we_b(1'b0),`
459			`.clk_b(b_clk)`
460			`);`
461			`endif
462			`endmodule // sd_fifo`