OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [versatile_mem_ctrl_defines.v] - Blame information for rev 408

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius 
//`define ACTEL
2 
`define XILINX
3 
//`define ALTERA
4 
//`define GENERIC_PRIMITIVES
5 
//`define SDR_16
6 
`define DDR_16
7 
`define INT_CLOCKED_DATA_CAPTURE
8 
//`define DEL_DQS_DATA_CAPTURE_1
9 
//`define DEL_DQS_DATA_CAPTURE_2
10 
 
11 
`define PORT0
12 
`define PORT1
13 
//`define PORT2
14 
//`define PORT3
15 
`define PORT4
16 
//`define PORT5
17 
//`define PORT6
18 
//`define PORT7
19 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.