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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sim/] [bin/] [ordb1a3pe1500-or1ksim.cfg] - Blame information for rev 475

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/* ordb1a3pe1500-or1ksim.cfg -- Simulator configuration script file for
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   ordb1a3pe1500 ORPSoC board build.
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   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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   Copyright (C) 2010, Embecosm Limited
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   Contributor Jeremy Bennett
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see . */
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/* -------------------------------------------------------------------------- */
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/* The Ork1sim has various parameters, that can be set in configuration files
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   like this one. The user can specify a configuration file at startu[ with
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   the -f  option.
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   The user guide (see the 'doc' directory) gives full details on
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   configuration files. This is a reference configuration, which may be used
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   as a starting point for customization.
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   A number of peripherals are mapped at standard addresses (above 0x80000000)
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   in the Verilog RTL of ORPSoC standard sitribution. The same values should
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   be used in Or1ksim section definitions to match the behavior of the Verilog
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      0x90000000 UART
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      0x91000000 GPIO
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      0x92000000 Ethernet
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   Not all verilog modules are modeled in or1ksim.                            */
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/* -------------------------------------------------------------------------- */
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/* Simulator section
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   verbose               = 0|1
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   debug                 = 0-9
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   profile               = 0|1
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   prof_file             = "" (default: "sim.profile")
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   mprofile              = 0|1
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   mprof_file            = "" (default: "sim.mprofile")
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   history               = 0|1
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   exe_log               = 0|1
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   exe_log_type          = hardware|simple|software|default
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   exe_log_start         =  (default: 0)
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   exe_log_end           =  (default: never end)
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   exe_log_marker        =  (default: no markers)
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   exe_log_file          = "" (default: "executed.log")
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   exe_bin_insn_log      = 0|1
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   exe_bin_insn_log_file = "" (default: "exe-insn.bin")
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   clkcycle              = [ps|ns|us|ms]
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*/
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section sim
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  clkcycle = 50ns
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end
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/* CPU section
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   ver         =  (default: 0)
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   cfg         =  (default: 0)
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   rev         =  (default: 0)
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   upr         =  (see user manual for default settings)
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   cfgr        =  (default: 0x00000020)
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   sr          =  (default: 0x00008001)
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   superscalar = 0|1
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   hazards     = 0|1
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   dependstats = 0|1
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   sbuf_len    =  (default: 0)
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   hardfloat   = 0|1
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*/
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section cpu
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  ver = 0x12
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  cfg = 0x00
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  rev = 0x0001
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end
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/* Memory section
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   type        = unknown|random|unknown|pattern
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   random_seed =  (default: -1)
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   pattern     =  (default: 0)
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   baseaddr    =  (default: 0)
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   size        =  (default: 1024)
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   name        = "" (default: "anonymous memory block")
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   ce          =  (default: -1)
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   mc          =  (default: 0)
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   delayr      =  (default: 1)
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   delayw      =  (default: 1)
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   log         = "" (default: NULL)
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*/
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section memory
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  name        = "RAM"
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  type        = unknown
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  baseaddr    = 0x00000000
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  size        = 0x02000000
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  delayr      = 1
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  delayw      = 1
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end
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/* Data MMU section
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   enabled   = 0|1
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   nsets     =  (default: 1)
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   nways     =  (default: 1)
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   pagesize  =  (default: 8192)
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   entrysize =  (default: 1)
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   ustates   =  (default: 1)
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   hitdelay  =  (default: 1)
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   missdelay =  (default: 1)
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*/
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section dmmu
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  enabled   = 1
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  nsets     = 64
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  nways     = 1
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  pagesize  = 8192
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  hitdelay  = 0
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  missdelay = 0
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end
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/* Instruction MMU section
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   enabled   = 0|1
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   nsets     =  (default: 1)
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   nways     =  (default: 1)
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   pagesize  =  (default: 8192)
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   entrysize =  (default: 1)
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   ustates   =  (default: 1)
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   hitdelay  =  (default: 1)
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   missdelay =  (default: 1)
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*/
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section immu
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  enabled   = 1
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  nsets     = 64
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  nways     = 1
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  pagesize  = 8192
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  hitdelay  = 0
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  missdelay = 0
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end
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/* Data cache section
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   enabled         = 0|1
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   nsets           =  (default: 1)
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   nways           =  (default: 1)
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   blocksize       =  (default: 16)
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   ustates         =  (default: 2)
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   load_hitdelay   =  (default: 2)
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   load_missdelay  =  (default: 2)
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   store_hitdelay  =  (default: 0)
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   store_missdelay =  (default: 0)
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*/
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section dc
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  enabled         = 1
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  nsets           = 256
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  nways           = 1
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  blocksize       = 16
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  load_hitdelay   = 0
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  load_missdelay  = 0
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  store_hitdelay  = 0
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  store_missdelay = 0
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end
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/* Instruction cache section
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   enabled    = 0|1
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   nsets      =  (default: 1)
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   nways      =  (default: 1)
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   blocksize  =  (default: 16)
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   ustates    =  (default: 2)
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   hitdelay   =  (default: 1)
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   missdelay  =  (default: 1)
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*/
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section ic
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  enabled   = 1
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  nsets     = 512
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  nways     = 1
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  blocksize = 16
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  hitdelay  = 0
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  missdelay = 0
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end
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/* Programmable interrupt controller section
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  enabled      = 0|1
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  edge_trigger = 0|1 (default: 1)
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*/
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section pic
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  enabled = 1
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end
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/* Power management section
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   enabled = 0|1
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*/
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section pm
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  enabled = 0
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end
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/* Debug unit section
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   enabled     = 0|1
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   rsp_enabled = 0|1
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   rsp_port    =  (default: 51000)
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   vapi_id     =  (default: 0)
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*/
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section debug
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  enabled = 0
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end
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/* UART section
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   enabled  = 0|1
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   baseaddr =  (default: 0)
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   channel  = "value>" (default: "xterm:")
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   irq      =  (default: 0)
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   16550    = 0|1
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   jitter   =  (default: 0)
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   vapi_id  =  (default: 0)
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*/
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section uart
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  enabled  = 1
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  baseaddr = 0x90000000
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  irq      = 2
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  16550    = 1
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end
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/* Ethernet section
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   enabled    = 0|1
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   baseaddr   =  (default: 0)
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   dma        =  (default: 0)
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   irq        =  (default: 0)
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   rtx_type   = 0|1
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   rx_channel =  (default: 0)
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   tx_channel =  (default: 0)
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   rxfile     = "" (default: "eth_rx")
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   txfile     = "" (default: "eth_rx")
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   sockif     = "" (default: "or1ksim_eth")
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   vapi_id    =  (default: 0)
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*/
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section ethernet
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  enabled  = 1
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  baseaddr = 0x92000000
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  irq      = 4
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  rtx_type = "tap"
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  tap_dev = "tap0"
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  dummy_crc = 1
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end

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