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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [board/] [include/] [board.h] - Blame information for rev 485

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Line No. Rev Author Line
1 408 julius
#ifndef _BOARD_H_
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#define _BOARD_H_
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//#define IN_CLK              50000000 // Hz
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//#define IN_CLK              32000000 // Hz
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//#define IN_CLK              30000000 // HZ
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//#define IN_CLK              24000000 // HZ
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#define IN_CLK                20000000 // HZ
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//#define IN_CLK              18000000 // HZ
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//#define IN_CLK              16000000 // HZ
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//
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// ROM bootloader
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//
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// Uncomment the appropriate bootloader define. This will effect the bootrom.S
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// file, which is compiled and converted into Verilog for inclusion at 
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// synthesis time. See bootloader/bootloader.S for details on each option.
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#ifndef PRELOAD_RAM
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#define BOOTROM_SPI_FLASH
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//#define BOOTROM_GOTO_RESET
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//#define BOOTROM_LOOP_AT_ZERO
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//#define BOOTROM_LOOP_IN_ROM
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#else
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#define BOOTROM_GOTO_RESET
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#endif
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//
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// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
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//
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#define SDRAM_BASE                 0x0
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//#define MT48LC32M16A2 // 64MB SDRAM part
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#define MT48LC16M16A2 // 32MB SDRAM part
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//#define MT48LC4M16A2 // 8MB SDRAM part
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#define FLASHROM_BASE       0xcf000000
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#define FLASHROM_SIZE            0x100
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#define GPIO_0_BASE         0x91000000
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#define UART0_BASE          0x90000000
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#define UART0_IRQ                    2
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#define UART0_BAUD_RATE         115200
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#define UART1_BASE          0x93000000
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#define UART1_IRQ                    3
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#define UART1_BAUD_RATE         115200
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#define UART2_BASE          0x94000000
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#define UART2_IRQ                    5
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#define UART2_BAUD_RATE         115200
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#define SPI0_BASE           0xb0000000
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#define SPI0_IRQ                     6
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#define SPI1_BASE           0xb1000000
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#define SPI1_IRQ                     7
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#define SPI2_BASE           0xb2000000
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#define SPI2_IRQ                     8
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#define I2C_0_BASE          0xa0000000
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#define I2C_0_IRQ                   10
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#define I2C_1_BASE          0xa1000000
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#define I2C_1_IRQ                   11
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#define I2C_2_BASE          0xa2000000
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#define I2C_2_IRQ                   12
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#define I2C_3_BASE          0xa3000000
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#define I2C_3_IRQ                   13
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#define USB0_BASE            0x9c000000
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#define USB0_HOST_IRQ                20
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#define USB0_SLAVE_IRQ               21
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#define USB1_BASE            0x9d000000
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#define USB1_HOST_IRQ                22
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#define USB1_SLAVE_IRQ               23
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#define ETH0_BASE            0x92000000
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#define ETH0_IRQ                      4
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#define ETH_MACADDR0               0x00
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#define ETH_MACADDR1               0x12
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#define ETH_MACADDR2               0x34
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#define ETH_MACADDR3               0x56
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#define ETH_MACADDR4               0x78
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#define ETH_MACADDR5               0x9a
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//
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// OR1200 tick timer period define
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//
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#define TICKS_PER_SEC   100
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//
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// UART driver initialisation
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// 
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#define UART_NUM_CORES 3
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#define UART_BASE_ADDRESSES_CSV                                         \
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        UART0_BASE, UART2_BASE, UART2_BASE
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#define UART_BAUD_RATES_CSV                                             \
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        UART0_BAUD_RATE, UART1_BAUD_RATE, UART1_BAUD_RATE
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#endif

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