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/*

 *

 * USB usbhostslave core slave register defines

 *

 * Julius Baxter, julius@opencores.org

 *

 */

#ifndef _USBHOSTSLAVE_HOST_H_

#define _USBHOSTSLAVE_HOST_H_

extern const int USBHOSTSLAVE_HOST_CORE_ADR[2];

char usb_host_init (int core);

// ---

// --- Host/slave constants

// ---

enum hostSlaveCommonRegs {

  HOST_SLAVE_MODE_CTRL = 0,

  HOST_SLAVE_VERSION_NUM

};

// ---

// --- Slave constants

// ---

enum endPointConstants {

  NUM_OF_ENDPOINTS = 4,

  NUM_OF_REGISTERS_PER_ENDPOINT = 4,

  BASE_INDEX_FOR_ENDPOINT_REGS = 0,

  ENDPOINT_CONTROL_REG = 0,

  ENDPOINT_STATUS_REG = 1,

  ENDPOINT_TRANSTYPE_STATUS_REG = 2,

  NAK_TRANSTYPE_STATUS_REG = 3 };

enum SCRegIndices {

  LAST_ENDP_REG = BASE_INDEX_FOR_ENDPOINT_REGS + (NUM_OF_REGISTERS_PER_ENDPOINT * NUM_OF_ENDPOINTS) - 1,

  SC_CONTROL_REG,

  SC_LINE_STATUS_REG,

  SC_INTERRUPT_STATUS_REG,

  SC_INTERRUPT_MASK_REG,

  SC_ADDRESS,

  SC_FRAME_NUM_MSP,

  SC_FRAME_NUM_LSP,

  SCREG_BUFFER_LEN };

enum SCRXStatusRegIndices {

  SC_CRC_ERROR_BIT = 0,

  SC_BIT_STUFF_ERROR_BIT,

  SC_RX_OVERFLOW_BIT,

  SC_RX_TIME_OUT_BIT,

  SC_NAK_SENT_BIT,

  SC_STALL_SENT_BIT,

  SC_ACK_RXED_BIT,

  SC_DATA_SEQUENCE_BIT };

enum SCEndPointControlRegIndices {

  ENDPOINT_ENABLE_BIT = 0,

  ENDPOINT_READY_BIT,

  ENDPOINT_OUTDATA_SEQUENCE_BIT,

  ENDPOINT_SEND_STALL_BIT,

  ENDPOINT_ISO_ENABLE_BIT };

enum SCMasterControlegIndices {

  SC_GLOBAL_ENABLE_BIT = 0,

  SC_TX_LINE_STATE_LSBIT,

  SC_TX_LINE_STATE_MSBIT,

  SC_DIRECT_CONTROL_BIT,

  SC_FULL_SPEED_LINE_POLARITY_BIT,

  SC_FULL_SPEED_LINE_RATE_BIT,

  SC_CONNECT_TO_HOST_BIT };

enum SCinterruptRegIndices {

  SC_TRANS_DONE_BIT = 0,

  SC_RESUME_INT_BIT,

  SC_RESET_EVENT_BIT,    //Line has entered reset state, or left reset state

  SC_SOF_RECEIVED_BIT,

  SC_NAK_SENT_INT_BIT,

  SC_VBUS_DET_INT_BIT };

enum SC_TXTransactionTypes {

  SC_SETUP_TRANS = 0,

  SC_IN_TRANS,

  SC_OUTDATA_TRANS };

enum SC_timeOuts {

  SC_RX_PACKET_TOUT = 18 };

enum SCFakeOutConstants {

  SC_TB_RX_TOUT = 0,

  SC_TB_DC_AND_IDLE_TRIG,

  SC_TB_RESET };

enum RXConnectStateConstants {

  SC_VBUS_DETECT_BIT = 2};

// ---

// --- Host constants

// ---

enum timeOuts {

  RX_PACKET_TOUT = 18 };

enum HCRegIndices {

  TX_CONTROL_REG=0,

  TX_TRANS_TYPE_REG,

  TX_LINE_CONTROL_REG,

  TX_SOF_ENABLE_REG,

  TX_ADDR_REG,

  TX_ENDP_REG,

  FRAME_NUM_MSB_REG,

  FRAME_NUM_LSB_REG,

  INTERRUPT_STATUS_REG,

  INTERRUPT_MASK_REG,

  RX_STATUS_REG,

  RX_PID_REG,

  RX_ADDR_REG,

  RX_ENDP_REG,

  RX_CONNECT_STATE_REG,

  SOF_TIMER_MSB_REG,

  HCREG_BUFFER_LEN /* must be last constant in this enum */

};

enum TXControlRegIndices {

  TRANS_REQ_BIT = 0,

  SOF_SYNC_BIT,

  PREAMBLE_ENABLE_BIT,

  ISO_ENABLE_BIT };

enum interruptRegIndices {

  TRANS_DONE_BIT = 0,

  RESUME_INT_BIT,

  CONNECTION_EVENT_BIT,

  SOF_SENT_BIT };

enum RXStatusRegIndices {

  CRC_ERROR_BIT = 0,

  BIT_STUFF_ERROR_BIT,

  RX_OVERFLOW_BIT,

  RX_TIME_OUT_BIT,

  NAK_RXED_BIT,

  STALL_RXED_BIT,

  ACK_RXED_BIT,

  DATA_SEQUENCE_BIT };

enum TXTransactionTypes {

  SETUP_TRANS = 0,

  IN_TRANS,

  OUTDATA0_TRANS,

  OUTDATA1_TRANS };

enum TXLineControlIndices {

  TX_LINE_STATE_LSBIT = 0,

  TX_LINE_STATE_MSBIT,

  DIRECT_CONTROL_BIT,

  FULL_SPEED_LINE_POLARITY_BIT,

  FULL_SPEED_LINE_RATE_BIT };

enum TXSOFEnableIndices {

  SOF_EN_BIT = 0 };

enum SOFTimeConstants {

  SOF_TX_TIME = 20,

  SOF_TX_MARGIN = 2 };

enum HCFakeOutConstants {

  HC_TB_RX_TOUT = 0,

  HC_TB_DC_AND_IDLE_TRIG,

  HC_TB_SOF_TRIG,

  HC_TB_RESET };

// ---

// --- Fifo constants

// ---

// fifo adddresses

enum FifoAddresses  {

  FIFO_DATA_REG = 0,

  FIFO_STATUS_REG,

  FIFO_DATA_COUNT_MSB,

  FIFO_DATA_COUNT_LSB,

  FIFO_CONTROL_REG   };

enum fifoSizes {

  SMALLEST_FIFO_SIZE = 64,

  LARGEST_FIFO_SIZE = 64,

  HOST_TX_FIFO_SIZE = 64,

  HOST_RX_FIFO_SIZE = 64,

  SLAVE_TX0_FIFO_SIZE = 64,

  SLAVE_RX0_FIFO_SIZE = 64,

  SLAVE_TX1_FIFO_SIZE = 64,

  SLAVE_RX1_FIFO_SIZE = 64,

  SLAVE_TX2_FIFO_SIZE = 64,

  SLAVE_RX2_FIFO_SIZE = 64,

  SLAVE_TX3_FIFO_SIZE = 64,

  SLAVE_RX3_FIFO_SIZE = 64

};

// ---

// --- Memory map

// ---

// top level memory regions

enum memoryRegions {

  HCREG_BASE = 0x0,

  HOST_RX_FIFO_BASE = 0x20,

  HOST_TX_FIFO_BASE = 0x30,

  SCREG_BASE = 0x40,

  EP0_RX_FIFO_BASE = 0x60,

  EP0_TX_FIFO_BASE = 0x70,

  EP1_RX_FIFO_BASE = 0x80,

  EP1_TX_FIFO_BASE = 0x90,

  EP2_RX_FIFO_BASE = 0xa0,

  EP2_TX_FIFO_BASE = 0xb0,

  EP3_RX_FIFO_BASE = 0xc0,

  EP3_TX_FIFO_BASE = 0xd0,

  HOST_SLAVE_CONTROL_BASE = 0xe0 };

// Host registers

enum hostMemMap {

  RA_HC_TX_CONTROL_REG = HCREG_BASE+TX_CONTROL_REG,

  RA_HC_TX_TRANS_TYPE_REG = HCREG_BASE+TX_TRANS_TYPE_REG,

  RA_HC_TX_LINE_CONTROL_REG = HCREG_BASE+TX_LINE_CONTROL_REG,

  RA_HC_TX_SOF_ENABLE_REG = HCREG_BASE+TX_SOF_ENABLE_REG,

  RA_HC_TX_ADDR_REG = HCREG_BASE+TX_ADDR_REG,

  RA_HC_TX_ENDP_REG = HCREG_BASE+TX_ENDP_REG,

  RA_HC_FRAME_NUM_MSB_REG = HCREG_BASE+FRAME_NUM_MSB_REG,

  RA_HC_FRAME_NUM_LSB_REG = HCREG_BASE+FRAME_NUM_LSB_REG,

  RA_HC_INTERRUPT_STATUS_REG = HCREG_BASE+INTERRUPT_STATUS_REG,

  RA_HC_INTERRUPT_MASK_REG = HCREG_BASE+INTERRUPT_MASK_REG,

  RA_HC_RX_STATUS_REG = HCREG_BASE+RX_STATUS_REG,

  RA_HC_RX_PID_REG = HCREG_BASE+RX_PID_REG,

  RA_HC_RX_ADDR_REG = HCREG_BASE+RX_ADDR_REG,

  RA_HC_RX_ENDP_REG = HCREG_BASE+RX_ENDP_REG,

  RA_HC_RX_CONNECT_STATE_REG = HCREG_BASE+RX_CONNECT_STATE_REG,

  RA_HC_RX_SOF_TIMER_MSB_REG = HCREG_BASE+SOF_TIMER_MSB_REG,

  RA_HC_RX_FIFO_DATA_REG = HOST_RX_FIFO_BASE + FIFO_DATA_REG,

  RA_HC_RX_FIFO_STATUS_REG = HOST_RX_FIFO_BASE + FIFO_STATUS_REG,

  RA_HC_RX_FIFO_DATA_COUNT_MSB = HOST_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_HC_RX_FIFO_DATA_COUNT_LSB = HOST_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_HC_RX_FIFO_CONTROL_REG = HOST_RX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_HC_TX_FIFO_DATA_REG = HOST_TX_FIFO_BASE + FIFO_DATA_REG,

  RA_HC_TX_FIFO_STATUS_REG = HOST_TX_FIFO_BASE + FIFO_STATUS_REG,

  RA_HC_TX_FIFO_DATA_COUNT_MSB = HOST_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_HC_TX_FIFO_DATA_COUNT_LSB = HOST_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_HC_TX_FIFO_CONTROL_REG = HOST_TX_FIFO_BASE + FIFO_CONTROL_REG,

};

enum slaveMemMap {

  RA_EP0_CONTROL_REG = SCREG_BASE + ENDPOINT_CONTROL_REG,

  RA_EP0_STATUS_REG = SCREG_BASE + ENDPOINT_STATUS_REG,

  RA_EP0_TRANSTYPE_STATUS_REG = SCREG_BASE + ENDPOINT_TRANSTYPE_STATUS_REG,

  RA_EP0_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + NAK_TRANSTYPE_STATUS_REG,

  RA_EP1_CONTROL_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + ENDPOINT_CONTROL_REG,

  RA_EP1_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + ENDPOINT_STATUS_REG,

  RA_EP1_TRANSTYPE_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT+ ENDPOINT_TRANSTYPE_STATUS_REG,

  RA_EP1_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + NAK_TRANSTYPE_STATUS_REG,

  RA_EP2_CONTROL_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_CONTROL_REG,

  RA_EP2_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_STATUS_REG,

  RA_EP2_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_TRANSTYPE_STATUS_REG,

  RA_EP2_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + NAK_TRANSTYPE_STATUS_REG,

  RA_EP3_CONTROL_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_CONTROL_REG,

  RA_EP3_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_STATUS_REG,

  RA_EP3_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_TRANSTYPE_STATUS_REG,

  RA_EP3_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + NAK_TRANSTYPE_STATUS_REG,

  RA_SC_CONTROL_REG = SCREG_BASE + SC_CONTROL_REG,

  RA_SC_LINE_STATUS_REG = SCREG_BASE + SC_LINE_STATUS_REG,

  RA_SC_INTERRUPT_STATUS_REG = SCREG_BASE + SC_INTERRUPT_STATUS_REG,

  RA_SC_INTERRUPT_MASK_REG = SCREG_BASE + SC_INTERRUPT_MASK_REG,

  RA_SC_ADDRESS = SCREG_BASE + SC_ADDRESS,

  RA_SC_FRAME_NUM_MSP = SCREG_BASE + SC_FRAME_NUM_MSP,

  RA_SC_FRAME_NUM_LSP = SCREG_BASE + SC_FRAME_NUM_LSP,

  RA_EP0_RX_FIFO_DATA_REG = EP0_RX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP0_RX_FIFO_STATUS_REG = EP0_RX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP0_RX_FIFO_DATA_COUNT_MSB = EP0_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP0_RX_FIFO_DATA_COUNT_LSB = EP0_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP0_RX_FIFO_CONTROL_REG = EP0_RX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP0_TX_FIFO_DATA_REG = EP0_TX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP0_TX_FIFO_STATUS_REG = EP0_TX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP0_TX_FIFO_DATA_COUNT_MSB = EP0_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP0_TX_FIFO_DATA_COUNT_LSB = EP0_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP0_TX_FIFO_CONTROL_REG = EP0_TX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP1_RX_FIFO_DATA_REG = EP1_RX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP1_RX_FIFO_STATUS_REG = EP1_RX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP1_RX_FIFO_DATA_COUNT_MSB = EP1_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP1_RX_FIFO_DATA_COUNT_LSB = EP1_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP1_RX_FIFO_CONTROL_REG = EP1_RX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP1_TX_FIFO_DATA_REG = EP1_TX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP1_TX_FIFO_STATUS_REG = EP1_TX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP1_TX_FIFO_DATA_COUNT_MSB = EP1_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP1_TX_FIFO_DATA_COUNT_LSB = EP1_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP1_TX_FIFO_CONTROL_REG = EP1_TX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP2_RX_FIFO_DATA_REG = EP2_RX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP2_RX_FIFO_STATUS_REG = EP2_RX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP2_RX_FIFO_DATA_COUNT_MSB = EP2_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP2_RX_FIFO_DATA_COUNT_LSB = EP2_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP2_RX_FIFO_CONTROL_REG = EP2_RX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP2_TX_FIFO_DATA_REG = EP2_TX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP2_TX_FIFO_STATUS_REG = EP2_TX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP2_TX_FIFO_DATA_COUNT_MSB = EP2_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP2_TX_FIFO_DATA_COUNT_LSB = EP2_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP2_TX_FIFO_CONTROL_REG = EP2_TX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP3_RX_FIFO_DATA_REG = EP3_RX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP3_RX_FIFO_STATUS_REG = EP3_RX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP3_RX_FIFO_DATA_COUNT_MSB = EP3_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP3_RX_FIFO_DATA_COUNT_LSB = EP3_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP3_RX_FIFO_CONTROL_REG = EP3_RX_FIFO_BASE + FIFO_CONTROL_REG,

  RA_EP3_TX_FIFO_DATA_REG = EP3_TX_FIFO_BASE + FIFO_DATA_REG,

  RA_EP3_TX_FIFO_STATUS_REG = EP3_TX_FIFO_BASE + FIFO_STATUS_REG,

  RA_EP3_TX_FIFO_DATA_COUNT_MSB = EP3_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,

  RA_EP3_TX_FIFO_DATA_COUNT_LSB = EP3_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,

  RA_EP3_TX_FIFO_CONTROL_REG = EP3_TX_FIFO_BASE + FIFO_CONTROL_REG

};

enum hostSlaveCommonMemMap {

  RA_HOST_SLAVE_MODE = HOST_SLAVE_CONTROL_BASE + HOST_SLAVE_MODE_CTRL,

  RA_HOST_SLAVE_VERSION = HOST_SLAVE_CONTROL_BASE + HOST_SLAVE_VERSION_NUM

};

// ---

// --- USB SIE constants

// ---

enum USBLineStates {

  // ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo

  ONE_ZERO = 0x2,

  ZERO_ONE = 0x1,

  SE0 = 0x0,

  SE1 = 0x3 };

enum limits {

  MAX_CONSEC_SAME_BITS = 6,

  RESUME_WAIT_TIME = 10,

  RESUME_LEN = 40,

  CONNECT_WAIT_TIME = 120,

  DISCONNECT_WAIT_TIME = 120 };

enum RXConnectStates {

  DISCONNECT = 0,

  LOW_SPEED_CONNECT = 1,

  FULL_SPEED_CONNECT = 2 };

// ---

// --- USB 1.1 constants

// ---

enum PIDTypes {

  OUT = 0x1,

  IN = 0x9,

  SOF = 0x5,

  SETUP = 0xd,

  DATA0 = 0x3,

  DATA1 = 0xb,

  ACK = 0x2,

  NAK = 0xa,

  STALL = 0xe,

  PREAMBLE = 0xc };

enum PIDGroups {

  SPECIAL = 0x0,

  TOKEN = 0x1,

  HANDSHAKE = 0x2,

  DATA = 0x3 };

enum SyncByte {

  SYNC_BYTE = 0x80 };

enum hostSlaveFlags {

  SLAVE = 0,

  HOST};

enum dataGenFlags {

  NO_GEN=0,

  SEQ_GEN,

  RAND_GEN};

// Added by Julius

enum usbStandardRequests {

  GET_STATUS=0,

  CLEAR_FEATURE,

  RESERVED0,

  SET_FEATURE,

  RESERVED1,

  SET_ADDRESS,

  GET_DESCRIPTOR,

  SET_DESCRIPTOR,

  GET_CONFIGURATION,

  SET_CONFIGURATION};

#endif