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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [tests/] [usbhostslave/] [sim/] [usbhostslave-hostsimple.c] - Blame information for rev 408

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/*
 *
 * USB simple host test
 *
 * Adam Edvardsson, adam.edvardsson@orsoc.se
 * Julius Baxter, julius.baxter@orsoc.se
 *
 */
 
#include "cpu-utils.h"
#include "spr-defs.h"
#include "board.h"
#include "usbhostslave-host.h"
#include "int.h"
#include "printf.h"
 
// Ensure we have USB in the design, or we cannot run this test
#include "orpsoc-defines.h"
 
#ifndef USB0
# ifndef USB1
#  error
#  error No USB module in design!
#  error
# else
// Using USB1, check that it's a HOST
#  ifdef USB1_ONLY_SLAVE
#   error
#   error Module USB1 is a slave only, cannot run host tests
#   error
#  else
#   define USBHOSTCORE 1
#  endif
# endif
#else
# define USBHOSTCORE 0
#endif
 
#ifndef USBHOSTCORE
# ifndef USB1
#  ifndef USB0
#   error
#   error No USB module in design!
#   error
#  else
#   define USBHOSTCORE 0
#  endif
# endif
#endif
 
volatile unsigned char int_status;
 
#if 1
#    define debug printf
#else
#    define debug
#endif
 
//Interupt handler just read status register and return, simply to test board connectivity
void usb_int_handler(void *corenum);
int send_packet(char usb_core, char USBAddress, char USBEndPoint,
                char transType, char dSize);
void usb_int_handler(void *corenum)
{
        char status;
        int core = USBHOSTCORE; //*((int*)corenum); // For some reason this doesn't work!
        status =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_INTERRUPT_STATUS_REG);
 
        //clear interrupt
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_INTERRUPT_STATUS_REG) =
            0xff;
 
        int_status = status;
 
        return;
 
}
 
/*T0, Check for correct values in registers
  Return failed register
  Print value of failed register
*/
int T1(usb_core)
{
        int ret = 0;
        int i;
        debug("T1 Register Init Val \n");
        volatile unsigned char usb_data_rw;
        //Initilisation test, read all register       
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + 0xE0) = 0x02;       //RESET
        for (i = HCREG_BASE; i < (HCREG_BASE + 15); i++) {
                usb_data_rw = (REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + i));
                if (usb_data_rw != 0) {
                        ret = i;
                        report(usb_data_rw);
                }
 
        }
 
        for (i = HOST_RX_FIFO_BASE; i < (HOST_RX_FIFO_BASE + 3); i++) {
                usb_data_rw = (REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + i));
                if (usb_data_rw != 0) {
                        //ret=i;
                        report(usb_data_rw);
                }
 
        }
        for (i = HOST_TX_FIFO_BASE; i < (HOST_TX_FIFO_BASE + 4); i++) {
                usb_data_rw = (REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + i));
                if (usb_data_rw != 0) {
                        ret = i;
                        report(usb_data_rw);
                }
 
        }
 
        return 0;
}
 
/*T2, Write to a register and readback. Reset core and read register
  Return failed part
  Print value of failed register
*/
int T2(usb_core)
{
        volatile unsigned char usb_data_rw;
        int ret = 0;
 
        //HOST MODE    
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + 0xE0) = 0x01;
 
        debug("T2 Register Write/Read\n");
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + TX_LINE_CONTROL_REG) = 0x18;
        usb_data_rw =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_TX_LINE_CONTROL_REG);
        if (usb_data_rw != 0x18) {
                report(usb_data_rw);
                return 1;
 
        }
 
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HOST_SLAVE_MODE) = 0x02;
        usb_data_rw =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_TX_LINE_CONTROL_REG);
        if (usb_data_rw != 0x00) {
                report(usb_data_rw);
                return 2;
        }
 
        return ret;
}
 
/*T3, Setup fullspeed and check so the connection interupt is generated
  Return failed part (1 = timeout, 2 = wrong connectivity)
  If fail: Print value of connect state register
*/
 
int T3(usb_core)
{
        int k = 0;
        volatile unsigned char usb_data_rw;
 
        debug("T3 Enable core %d and setup fullspeed\n", usb_core);
 
        //debug("Enable core and setup fullspeed  ");
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HOST_SLAVE_MODE) = 0x01;
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_LINE_CONTROL_REG) =
            0x18;
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_INTERRUPT_MASK_REG) =
            0xff;
 
        //Wait for interupt
        while (k < 100) {
                k++;
        }
 
        int_status = 0;
 
        usb_data_rw
            =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_RX_CONNECT_STATE_REG);
 
        usb_data_rw
            =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_RX_CONNECT_STATE_REG);
 
        if (usb_data_rw != 0x02) {
                report(usb_data_rw);
                return 1;
        }
 
        return 0;
}
 
/*T4, Transfer test 1, send data
 * Device address = 0x00, 2 byte SETUP transaction to Endpoint 0.
 * Return failed (1 = timeout,)
 * If fail: Print value of connect state register
 */
 
int T4(usb_core)
{
        int k = 0;
        volatile unsigned char usb_data_rw;
        char USBAddress = 0x00;
        char USBEndPoint = 0x00;
        char transType = 0x00;
        char dSize = 0;
 
        debug("T4 Transfer test 1\n");
        usb_data_rw =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_INTERRUPT_STATUS_REG);
        send_packet(usb_core, USBAddress, USBEndPoint, transType, dSize);
 
        while ((int_status & 0x01) != 0x01) {
                k++;
                if (k > 1000) { //timeout    
                        report(k);
                        return 1;
                }
        }
        int_status = 0;
 
        return 0;
}
 
/*T5, Transfer test 2, send data
 * Device address = 0x5a, 64 byte OUT DATA0 transaction to Endpoint 1. ");
 * Return failed (1 = timeout )
 * If fail: Print value of connect state register
 */
 
int T5(usb_core)
{
        int k = 0;
        volatile unsigned char usb_data_rw;
 
        char USBAddress = 0x5a;
        char USBEndPoint = 0x01;
        char transType = 2;
        char dSize = 64;
 
        debug("T5 Transfer test 2\n");
        usb_data_rw =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_INTERRUPT_STATUS_REG);
        send_packet(usb_core, USBAddress, USBEndPoint, transType, dSize);
 
        while ((int_status & 0x01) != 0x01) {
                k++;
                if (k > 1000) { //timeout    
                        report(k);
                        return 1;
                }
        }
        int_status = 0;
 
        return 0;
}
 
/*T6, Transfer test 3, recive data,
 * Device address = 0x5a, 64 byte OUT DATA0 transaction to Endpoint 1. ");
 * Return failed (1 = timeout, 2= To litle data recived)
 * If fail: Print value of connect state register
 */
 
int T6(usb_core)
{
        int i, k = 0;
        volatile unsigned char usb_data_rw;
 
        char USBAddress = 0x01;
        char USBEndPoint = 0x02;
        char transType = 1;
        char dSize = 64;
 
        debug("T6 Transfer test 3\n");
        usb_data_rw =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                 RA_HC_INTERRUPT_STATUS_REG);
        send_packet(usb_core, USBAddress, USBEndPoint, transType, dSize);
 
        while ((int_status & 0x01) != 0x01) {
                k++;
                if (k > 1000) { //timeout    
                        report(k);
                        return 1;
                }
        }
        int_status = 0;
 
        usb_data_rw = REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + 0x23);
        if (usb_data_rw != 64)
                return 2;
 
        for (i = dSize; i > 0; i = i - 1) {
                usb_data_rw =
                    REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                         RA_HC_RX_FIFO_DATA_REG);
                report(usb_data_rw);
 
        }
        return 0;
 
        return 0;
}
 
int send_packet(char usb_core, char USBAddress, char USBEndPoint,
                char transType, char dSize)
{
        int i;
        int data = 0;
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_ADDR_REG) =
            USBAddress;
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_ENDP_REG) =
            USBEndPoint;
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_TRANS_TYPE_REG) =
            transType;
 
        for (i = 0; i < dSize; i = i + 1) {
                REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +
                     RA_HC_TX_FIFO_DATA_REG) = data;
                data = data + 1;
        }
 
        REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_CONTROL_REG) =
            0x01;
 
}
 
#define EXPECTED_VERSION 0x20
int main()
{
        char USBAddress = 0x00;
        char USBEndPoint = 0x00;
        char transType = 0x00;
        int dataSize = 4;
 
        int i;
        char data = 0;
        volatile int k = 0;
 
        int usb_core = USBHOSTCORE;
        int test_result;
        volatile unsigned char usb_data_rw;
 
        // init user interrupt handler
        int_init();
 
#if USBHOSTCORE==0
        /* Install USB host core 0 interrupt handler */
        int_add(USB0_HOST_IRQ, usb_int_handler, (void *)&usb_core);
#endif
#if USBHOSTCORE==1
        /* Install USB host core 1 interrupt handler */
        int_add(USB1_HOST_IRQ, usb_int_handler, (void *)&usb_core);
#endif
 
        /* Enable interrupts in supervisor register */
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
 
        debug("\nStarting USB host test\n");
 
        usb_data_rw =
            REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HOST_SLAVE_VERSION);
 
        if (usb_data_rw != EXPECTED_VERSION) {
                debug("Wrong core_verison");
                exit(usb_data_rw);
        }
        //Start testing
 
        test_result = T1(usb_core);
        if (test_result > 0)
                exit(test_result);
        report(0x00000001);
 
        test_result = T2(usb_core);
        if (test_result > 1)
                exit(test_result);
        report(0x00000002);
 
        test_result = T3(usb_core);
        if (test_result > 1)
                exit(test_result);
        report(0x00000003);
 
        test_result = T4(usb_core);
        if (test_result > 1)
                exit(test_result);
        report(0x00000004);
 
        test_result = T5(usb_core);
        if (test_result > 1)
                exit(test_result);
        report(0x00000005);
 
        test_result = T6(usb_core);
        if (test_result > 1)
                exit(test_result);
        report(0x00000006);
 
        exit(0x8000000d);
}

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [tests/] [usbhostslave/] [sim/] [usbhostslave-hostsimple.c] - Blame information for rev 408

Line No.	Rev	Author	Line
1	408	julius	`/*`
2			`*`
3			`* USB simple host test`
4			`*`
5			`* Adam Edvardsson, adam.edvardsson@orsoc.se`
6			`* Julius Baxter, julius.baxter@orsoc.se`
7			`*`
8			`*/`
9
10			`#include "cpu-utils.h"`
11			`#include "spr-defs.h"`
12			`#include "board.h"`
13			`#include "usbhostslave-host.h"`
14			`#include "int.h"`
15			`#include "printf.h"`
16
17			`// Ensure we have USB in the design, or we cannot run this test`
18			`#include "orpsoc-defines.h"`
19
20			`#ifndef USB0`
21			`# ifndef USB1`
22			`# error`
23			`# error No USB module in design!`
24			`# error`
25			`# else`
26			`// Using USB1, check that it's a HOST`
27			`# ifdef USB1_ONLY_SLAVE`
28			`# error`
29			`# error Module USB1 is a slave only, cannot run host tests`
30			`# error`
31			`# else`
32			`# define USBHOSTCORE 1`
33			`# endif`
34			`# endif`
35			`#else`
36			`# define USBHOSTCORE 0`
37			`#endif`
38
39			`#ifndef USBHOSTCORE`
40			`# ifndef USB1`
41			`# ifndef USB0`
42			`# error`
43			`# error No USB module in design!`
44			`# error`
45			`# else`
46			`# define USBHOSTCORE 0`
47			`# endif`
48			`# endif`
49			`#endif`
50
51			`volatile unsigned char int_status;`
52
53			`#if 1`
54			`# define debug printf`
55			`#else`
56			`# define debug`
57			`#endif`
58
59			`//Interupt handler just read status register and return, simply to test board connectivity`
60			`void usb_int_handler(void *corenum);`
61			`int send_packet(char usb_core, char USBAddress, char USBEndPoint,`
62			`char transType, char dSize);`
63			`void usb_int_handler(void *corenum)`
64			`{`
65			`char status;`
66			`int core = USBHOSTCORE; //((int)corenum); // For some reason this doesn't work!`
67			`status =`
68			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_INTERRUPT_STATUS_REG);`
69
70			`//clear interrupt`
71			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[core] + RA_HC_INTERRUPT_STATUS_REG) =`
72			`0xff;`
73
74			`int_status = status;`
75
76			`return;`
77
78			`}`
79
80			`/*T0, Check for correct values in registers`
81			`Return failed register`
82			`Print value of failed register`
83			`*/`
84			`int T1(usb_core)`
85			`{`
86			`int ret = 0;`
87			`int i;`
88			`debug("T1 Register Init Val \n");`
89			`volatile unsigned char usb_data_rw;`
90			`//Initilisation test, read all register`
91			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + 0xE0) = 0x02; //RESET`
92			`for (i = HCREG_BASE; i < (HCREG_BASE + 15); i++) {`
93			`usb_data_rw = (REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + i));`
94			`if (usb_data_rw != 0) {`
95			`ret = i;`
96			`report(usb_data_rw);`
97			`}`
98
99			`}`
100
101			`for (i = HOST_RX_FIFO_BASE; i < (HOST_RX_FIFO_BASE + 3); i++) {`
102			`usb_data_rw = (REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + i));`
103			`if (usb_data_rw != 0) {`
104			`//ret=i;`
105			`report(usb_data_rw);`
106			`}`
107
108			`}`
109			`for (i = HOST_TX_FIFO_BASE; i < (HOST_TX_FIFO_BASE + 4); i++) {`
110			`usb_data_rw = (REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + i));`
111			`if (usb_data_rw != 0) {`
112			`ret = i;`
113			`report(usb_data_rw);`
114			`}`
115
116			`}`
117
118			`return 0;`
119			`}`
120
121			`/*T2, Write to a register and readback. Reset core and read register`
122			`Return failed part`
123			`Print value of failed register`
124			`*/`
125			`int T2(usb_core)`
126			`{`
127			`volatile unsigned char usb_data_rw;`
128			`int ret = 0;`
129
130			`//HOST MODE`
131			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + 0xE0) = 0x01;`
132
133			`debug("T2 Register Write/Read\n");`
134			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + TX_LINE_CONTROL_REG) = 0x18;`
135			`usb_data_rw =`
136			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
137			`RA_HC_TX_LINE_CONTROL_REG);`
138			`if (usb_data_rw != 0x18) {`
139			`report(usb_data_rw);`
140			`return 1;`
141
142			`}`
143
144			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HOST_SLAVE_MODE) = 0x02;`
145			`usb_data_rw =`
146			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
147			`RA_HC_TX_LINE_CONTROL_REG);`
148			`if (usb_data_rw != 0x00) {`
149			`report(usb_data_rw);`
150			`return 2;`
151			`}`
152
153			`return ret;`
154			`}`
155
156			`/*T3, Setup fullspeed and check so the connection interupt is generated`
157			`Return failed part (1 = timeout, 2 = wrong connectivity)`
158			`If fail: Print value of connect state register`
159			`*/`
160
161			`int T3(usb_core)`
162			`{`
163			`int k = 0;`
164			`volatile unsigned char usb_data_rw;`
165
166			`debug("T3 Enable core %d and setup fullspeed\n", usb_core);`
167
168			`//debug("Enable core and setup fullspeed ");`
169			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HOST_SLAVE_MODE) = 0x01;`
170			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_LINE_CONTROL_REG) =`
171			`0x18;`
172			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_INTERRUPT_MASK_REG) =`
173			`0xff;`
174
175			`//Wait for interupt`
176			`while (k < 100) {`
177			`k++;`
178			`}`
179
180			`int_status = 0;`
181
182			`usb_data_rw`
183			`=`
184			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
185			`RA_HC_RX_CONNECT_STATE_REG);`
186
187			`usb_data_rw`
188			`=`
189			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
190			`RA_HC_RX_CONNECT_STATE_REG);`
191
192			`if (usb_data_rw != 0x02) {`
193			`report(usb_data_rw);`
194			`return 1;`
195			`}`
196
197			`return 0;`
198			`}`
199
200			`/*T4, Transfer test 1, send data`
201			`* Device address = 0x00, 2 byte SETUP transaction to Endpoint 0.`
202			`* Return failed (1 = timeout,)`
203			`* If fail: Print value of connect state register`
204			`*/`
205
206			`int T4(usb_core)`
207			`{`
208			`int k = 0;`
209			`volatile unsigned char usb_data_rw;`
210			`char USBAddress = 0x00;`
211			`char USBEndPoint = 0x00;`
212			`char transType = 0x00;`
213			`char dSize = 0;`
214
215			`debug("T4 Transfer test 1\n");`
216			`usb_data_rw =`
217			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
218			`RA_HC_INTERRUPT_STATUS_REG);`
219			`send_packet(usb_core, USBAddress, USBEndPoint, transType, dSize);`
220
221			`while ((int_status & 0x01) != 0x01) {`
222			`k++;`
223			`if (k > 1000) { //timeout`
224			`report(k);`
225			`return 1;`
226			`}`
227			`}`
228			`int_status = 0;`
229
230			`return 0;`
231			`}`
232
233			`/*T5, Transfer test 2, send data`
234			`* Device address = 0x5a, 64 byte OUT DATA0 transaction to Endpoint 1. ");`
235			`* Return failed (1 = timeout )`
236			`* If fail: Print value of connect state register`
237			`*/`
238
239			`int T5(usb_core)`
240			`{`
241			`int k = 0;`
242			`volatile unsigned char usb_data_rw;`
243
244			`char USBAddress = 0x5a;`
245			`char USBEndPoint = 0x01;`
246			`char transType = 2;`
247			`char dSize = 64;`
248
249			`debug("T5 Transfer test 2\n");`
250			`usb_data_rw =`
251			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
252			`RA_HC_INTERRUPT_STATUS_REG);`
253			`send_packet(usb_core, USBAddress, USBEndPoint, transType, dSize);`
254
255			`while ((int_status & 0x01) != 0x01) {`
256			`k++;`
257			`if (k > 1000) { //timeout`
258			`report(k);`
259			`return 1;`
260			`}`
261			`}`
262			`int_status = 0;`
263
264			`return 0;`
265			`}`
266
267			`/*T6, Transfer test 3, recive data,`
268			`* Device address = 0x5a, 64 byte OUT DATA0 transaction to Endpoint 1. ");`
269			`* Return failed (1 = timeout, 2= To litle data recived)`
270			`* If fail: Print value of connect state register`
271			`*/`
272
273			`int T6(usb_core)`
274			`{`
275			`int i, k = 0;`
276			`volatile unsigned char usb_data_rw;`
277
278			`char USBAddress = 0x01;`
279			`char USBEndPoint = 0x02;`
280			`char transType = 1;`
281			`char dSize = 64;`
282
283			`debug("T6 Transfer test 3\n");`
284			`usb_data_rw =`
285			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
286			`RA_HC_INTERRUPT_STATUS_REG);`
287			`send_packet(usb_core, USBAddress, USBEndPoint, transType, dSize);`
288
289			`while ((int_status & 0x01) != 0x01) {`
290			`k++;`
291			`if (k > 1000) { //timeout`
292			`report(k);`
293			`return 1;`
294			`}`
295			`}`
296			`int_status = 0;`
297
298			`usb_data_rw = REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + 0x23);`
299			`if (usb_data_rw != 64)`
300			`return 2;`
301
302			`for (i = dSize; i > 0; i = i - 1) {`
303			`usb_data_rw =`
304			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
305			`RA_HC_RX_FIFO_DATA_REG);`
306			`report(usb_data_rw);`
307
308			`}`
309			`return 0;`
310
311			`return 0;`
312			`}`
313
314			`int send_packet(char usb_core, char USBAddress, char USBEndPoint,`
315			`char transType, char dSize)`
316			`{`
317			`int i;`
318			`int data = 0;`
319			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_ADDR_REG) =`
320			`USBAddress;`
321			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_ENDP_REG) =`
322			`USBEndPoint;`
323			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_TRANS_TYPE_REG) =`
324			`transType;`
325
326			`for (i = 0; i < dSize; i = i + 1) {`
327			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] +`
328			`RA_HC_TX_FIFO_DATA_REG) = data;`
329			`data = data + 1;`
330			`}`
331
332			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HC_TX_CONTROL_REG) =`
333			`0x01;`
334
335			`}`
336
337			`#define EXPECTED_VERSION 0x20`
338			`int main()`
339			`{`
340			`char USBAddress = 0x00;`
341			`char USBEndPoint = 0x00;`
342			`char transType = 0x00;`
343			`int dataSize = 4;`
344
345			`int i;`
346			`char data = 0;`
347			`volatile int k = 0;`
348
349			`int usb_core = USBHOSTCORE;`
350			`int test_result;`
351			`volatile unsigned char usb_data_rw;`
352
353			`// init user interrupt handler`
354			`int_init();`
355
356			`#if USBHOSTCORE==0`
357			`/* Install USB host core 0 interrupt handler */`
358			`int_add(USB0_HOST_IRQ, usb_int_handler, (void *)&usb_core);`
359			`#endif`
360			`#if USBHOSTCORE==1`
361			`/* Install USB host core 1 interrupt handler */`
362			`int_add(USB1_HOST_IRQ, usb_int_handler, (void *)&usb_core);`
363			`#endif`
364
365			`/* Enable interrupts in supervisor register */`
366			`mtspr(SPR_SR, mfspr(SPR_SR) \| SPR_SR_IEE);`
367
368			`debug("\nStarting USB host test\n");`
369
370			`usb_data_rw =`
371			`REG8(USBHOSTSLAVE_HOST_CORE_ADR[usb_core] + RA_HOST_SLAVE_VERSION);`
372
373			`if (usb_data_rw != EXPECTED_VERSION) {`
374			`debug("Wrong core_verison");`
375			`exit(usb_data_rw);`
376			`}`
377			`//Start testing`
378
379			`test_result = T1(usb_core);`
380			`if (test_result > 0)`
381			`exit(test_result);`
382			`report(0x00000001);`
383
384			`test_result = T2(usb_core);`
385			`if (test_result > 1)`
386			`exit(test_result);`
387			`report(0x00000002);`
388
389			`test_result = T3(usb_core);`
390			`if (test_result > 1)`
391			`exit(test_result);`
392			`report(0x00000003);`
393
394			`test_result = T4(usb_core);`
395			`if (test_result > 1)`
396			`exit(test_result);`
397			`report(0x00000004);`
398
399			`test_result = T5(usb_core);`
400			`if (test_result > 1)`
401			`exit(test_result);`
402			`report(0x00000005);`
403
404			`test_result = T6(usb_core);`
405			`if (test_result > 1)`
406			`exit(test_result);`
407			`report(0x00000006);`
408
409			`exit(0x8000000d);`
410			`}`