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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [tests/] [usbhostslave/] [sim/] [usbhostslave-slavesimple.c] - Blame information for rev 408

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Line No. Rev Author Line
1 408 julius 
/*
2 
 *
3 
 * Simple USB slave test
4 
 *
5 
 * Adam Edvardsson, adam.edvardsson@orsoc.se
6 
 * Julius Baxter, julius.baxter@orsoc.se
7 
 *
8 
 */
9 
 
10 
#include "cpu-utils.h"
11 
#include "spr-defs.h"
12 
#include "board.h"
13 
#include "usbhostslave-slave.h"
14 
#include "int.h"
15 
#include "printf.h"
16 
volatile int i;
17 
 
18 
// We rely on USB1 being a slave, check it's in the design.
19 
#include "orpsoc-defines.h"
20 
 
21 
# ifndef USB1
22 
#  error
23 
#  error USB1 module not in design - enable it to run USB slave tests
24 
#  error
25 
# else
26 
// Using USB1, check that it's a HOST
27 
#  ifdef USB1_ONLY_HOST
28 
#   error
29 
#   error Module USB1 is a host only - must have slave capability to run tests
30 
#   error
31 
#  else
32 
#   define USBSLAVECORE 1
33 
#  endif
34 
# endif
35 
 
36 
int main()
37 
{
38 
 
39 
        int usb_core = USBSLAVECORE;
40 
 
41 
        volatile unsigned char interrupt_status;
42 
 
43 
        // disable all endpoints first
44 
        usb_slave_global_disable_endpoints(usb_core);
45 
 
46 
        printf("\nUSB Slave test for usb core %d\n", USBSLAVECORE);
47 
 
48 
        //Enable slave Setup slave
49 
        //Enable fullspeed,
50 
        //Connect to host (D+ pullup)
51 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_SC_CONTROL_REG) =
52 
            0x71;
53 
        //Set Slave addres
54 
        usb_slave_set_addr(usb_core, 0x63);
55 
        //Enable endpont
56 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_EP0_CONTROL_REG) =
57 
            0x03;
58 
        //Enable interupt
59 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
60 
             USBSLAVE_SC_INTERRUPT_MASK_REG) = 0xff;
61 
 
62 
        //Test 1, check for VBUS connection
63 
        //Poll for VBUS interupt.
64 
        interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
65 
                                USBSLAVE_SC_INTERRUPT_STATUS_REG);
66 
 
67 
        while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT)
68 
               != USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT) {
69 
 
70 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
71 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
72 
 
73 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
74 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
75 
 
76 
        }
77 
 
78 
        //VBUS change detected
79 
 
80 
        // Clear interrupt
81 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
82 
             USBSLAVE_SC_INTERRUPT_STATUS_REG)
83 
            = USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT;
84 
 
85 
        // Check so VBUS is present
86 
        if ((REG8
87 
             (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
88 
              USBSLAVE_SC_LINE_STATUS_REG) &
89 
             USBSLAVE_SC_LINE_STATUS_REG_VBUS_STATE)
90 
            == USBSLAVE_SC_LINE_STATUS_REG_VBUS_STATE)
91 
        {
92 
                report(0x00000001);
93 
        } else {
94 
                report(0x00000001);
95 
                exit(0xBAAAAAAD);
96 
        }
97 
 
98 
        //Test 2, check for bus-reset and fullspeed present
99 
        interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
100 
                                USBSLAVE_SC_INTERRUPT_STATUS_REG);
101 
        while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT)
102 
               != USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT) {
103 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
104 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
105 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
106 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
107 
 
108 
        }
109 
 
110 
        //Bus reset
111 
        // Clear interrupt
112 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
113 
             USBSLAVE_SC_INTERRUPT_STATUS_REG)
114 
            = USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT;
115 
 
116 
        //Check so Fullspeed is activated
117 
        if ((REG8
118 
             (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
119 
              USBSLAVE_SC_LINE_STATUS_REG) &
120 
             USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_FSPEED)
121 
            == USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_FSPEED) {
122 
                report(0x00000002);
123 
        } else {
124 
                report(0x00000002);
125 
                exit(0xBAAAAAAD);
126 
        }
127 
 
128 
        // Test 3, check for first transfer completion and check for correct data,
129 
        // transfertype and nr byte sent.
130 
        //
131 
        interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
132 
                                USBSLAVE_SC_INTERRUPT_STATUS_REG);
133 
        while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE)
134 
               != USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE) {
135 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
136 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
137 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
138 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
139 
 
140 
        }
141 
 
142 
        //Transfer complete, check for correct typ of transfer (SETUP_TRANSFER)
143 
        if (REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
144 
                 USBSLAVE_EP0_TRANSTYPE_STATUS_REG) != 0) {
145 
                report(0x10000003);
146 
                exit(0xBAAAAAAD);
147 
        }
148 
        //Check nr byte sent
149 
        if (REG8
150 
            (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
151 
             USBSLAVE_EP0_RX_FIFO_DATA_CNT_LSB) != 2) {
152 
                report(0x20000003);
153 
                exit(0xBAAAAAAD);
154 
        }
155 
        //Check recived data
156 
        if ((REG8
157 
             (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
158 
              USBSLAVE_EP0_RX_FIFO_DATA) == 0)
159 
            &&
160 
            (REG8
161 
             (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
162 
              USBSLAVE_EP0_RX_FIFO_DATA) == 1)) {
163 
                report(0x00000003);
164 
        } else {
165 
                report(0x00000003);
166 
                report(0xBAAAAAAD);
167 
                exit(0);
168 
        }
169 
 
170 
        //Enable endpoint again
171 
        //Enable fullspeed,
172 
 
173 
        //Connect to host (D+ pullup)
174 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_SC_CONTROL_REG) =
175 
            0x71;
176 
 
177 
        //Enable endpont
178 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_EP0_CONTROL_REG) =
179 
            0x03;
180 
 
181 
        // Clear interrupt
182 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
183 
             USBSLAVE_SC_INTERRUPT_STATUS_REG)
184 
            = USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE;
185 
 
186 
        // Test 4, check for first transfer completion and check for correct data,
187 
        // transfertype and nr byte sent.
188 
        //
189 
        interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
190 
                                USBSLAVE_SC_INTERRUPT_STATUS_REG);
191 
        while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE)
192 
               != USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE) {
193 
                interrupt_status =
194 
                    REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
195 
                         USBSLAVE_SC_INTERRUPT_STATUS_REG);
196 
                interrupt_status =
197 
                    REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
198 
                         USBSLAVE_SC_INTERRUPT_STATUS_REG);
199 
 
200 
        }
201 
 
202 
        //Transfer complete, check for correct typ of transfer (OUT_TRANSFER)
203 
        if (REG8
204 
            (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
205 
             USBSLAVE_EP0_TRANSTYPE_STATUS_REG)
206 
            != USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_OUTDATA) {
207 
                report(0x10000004);
208 
                exit(0xBAAAAAAD);
209 
        }
210 
        //Check nr byte sent
211 
        if (REG8
212 
            (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
213 
             USBSLAVE_EP0_RX_FIFO_DATA_CNT_LSB) != 20) {
214 
                report(0x20000004);
215 
                exit(0xBAAAAAAD);
216 
        }
217 
        //Check recived data
218 
        for (i = 0; i < 20; i++) {
219 
 
220 
                if (REG8
221 
                    (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
222 
                     USBSLAVE_EP0_RX_FIFO_DATA) != i) {
223 
                        report(0x00000004);
224 
                        report(0xBAAAAAAD);
225 
                        exit(0);
226 
                }
227 
        }
228 
        report(0x00000004);
229 
 
230 
        //Test 5, check for NAK interupt, and type of transfer.
231 
        //
232 
        interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
233 
                                USBSLAVE_SC_INTERRUPT_STATUS_REG);
234 
        while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_NAK_SENT)
235 
               != USBSLAVE_SC_INTERRUPT_STATUS_REG_NAK_SENT) {
236 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
237 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
238 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
239 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
240 
 
241 
        }
242 
 
243 
        //Transfer NAK, check for correct typ of transfer (OUT_TRANSFER)
244 
        if (REG8
245 
            (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
246 
             USBSLAVE_EP0_NAK_TRANSTYPE_STATUS_REG)
247 
            != USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_OUTDATA) {
248 
                report(0x10000005);
249 
                exit(0xBAAAAAAD);
250 
        }
251 
 
252 
        report(0x00000005);
253 
 
254 
        // Clear all interrupt
255 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
256 
             USBSLAVE_SC_INTERRUPT_STATUS_REG) = 0x3f;
257 
 
258 
        //Test 6, IN-transfer to endpoint 2
259 
        //Connect to host (D+ pullup)
260 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_SC_CONTROL_REG) =
261 
            0x71;
262 
        usb_slave_set_addr(usb_core, 0x63);
263 
        //Enable endpoint
264 
        REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_EP2_CONTROL_REG) =
265 
            0x03;
266 
 
267 
        //Fill TX_FIFO
268 
        for (i = 0; i <= 20; i++) {
269 
                REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
270 
                     USBSLAVE_EP2_TX_FIFO_DATA) = i;
271 
        }
272 
 
273 
        interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
274 
                                USBSLAVE_SC_INTERRUPT_STATUS_REG);
275 
 
276 
        while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE)
277 
               != USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE) {
278 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
279 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
280 
                interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
281 
                                        USBSLAVE_SC_INTERRUPT_STATUS_REG);
282 
 
283 
        }
284 
 
285 
        //Transfer complete, check for correct typ of transfer (IN_TRANSFER)
286 
 
287 
        if ((REG8
288 
             (USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
289 
              USBSLAVE_EP2_TRANSTYPE_STATUS_REG)
290 
             & USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_IN) !=
291 
            USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_IN) {
292 
                report(0x10000006);
293 
                exit(0xBAAAAAAD);
294 
        }
295 
 
296 
        //Fill TX_FIFO
297 
        //while(1){}
298 
 
299 
        //When transfer request arrive, fill TX-FIFO 0-20, and start transfer
300 
        // data = 8'h00;
301 
        //for (i=0; i<dataSize; i=i+1) begin
302 
        //   testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
303 
        //  data = data + 1'b1;
304 
        //  end
305 
        // testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
306 
 
307 
        // Finish simulation
308 
        exit(0x8000000d);
309 
}

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