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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [syn/] [synplify/] [bin/] [Makefile] - Blame information for rev 449

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Line No. Rev Author Line
1 408 julius
#
2
# Makefile for synthesis
3
#
4
# To generate the EDIF, just do "# make all"
5
#
6
# To synthesize for older ORSoC board with A3P1000, do:
7
#       # make clean all FPGA_FAMILY=ProASIC3 FPGA_PART=A3P1000
8
#
9
# Note: correct pll model must be linked in backend path.
10
#
11
 
12
# Name of the directory we're currently in
13
CUR_DIR=$(shell pwd)
14
 
15
# The root path of the board build
16
BOARD_DIR ?=$(CUR_DIR)/../../..
17
PROJECT_ROOT=$(BOARD_DIR)/../../..
18
 
19
# Export BOARD_PATH for the software makefiles
20
BOARD_PATH=$(BOARD_DIR)
21
export BOARD_PATH
22
 
23
DESIGN_NAME=orpsoc
24
 
25
# Paths to other important parts of this test suite
26
 
27
# Paths to other important parts of this test suite
28
COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
29
COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
30
#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
31
 
32
BOARD_RTL_DIR=$(BOARD_DIR)/rtl
33
BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
34
# Only 1 include path for board builds - their own!
35
BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
36
#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
37
 
38
 
39
BACKEND_DIR=$(BOARD_DIR)/backend
40
BACKEND_VERILOG_DIR=$(BACKEND_DIR)/rtl/verilog
41
 
42
# Set V=1 when calling make to enable verbose output
43
# mainly for debugging purposes.
44
ifeq ($(V), 1)
45
Q=
46
else
47
Q ?=@
48
endif
49
 
50
 
51
#
52
# Verilog DUT source variables
53
#
54
# First we get a list of modules in the RTL path of the board's path.
55
# Next we check which modules not in the board's RTL path are in the root RTL
56
# path (modules which can be commonly instantiated, but over which board
57
# build-specific versions take precedence.)
58
 
59
# Paths under board/***/rtl/verilog we wish to exclude when getting modules
60
BOARD_VERILOG_MODULES_EXCLUDE= include
61
BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
62
# Apply exclude to list of modules
63
BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
64
 
65
# Rule for debugging this script
66
print-board-modules:
67
        @echo echo; echo "\t### Board verilog modules ###"; echo;
68
        @echo $(BOARD_RTL_VERILOG_MODULES)
69
 
70
# Now get list of modules that we don't have a version of in the board path
71
COMMON_VERILOG_MODULES_EXCLUDE= include
72
COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
73
 
74
COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
75
COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
76
 
77
# Rule for debugging this script
78
print-common-modules-exclude:
79
        @echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo;
80
        @echo "$(COMMON_VERILOG_MODULES_EXCLUDE)"
81
 
82
print-common-modules:
83
        @echo echo; echo "\t###  Verilog modules from common RTL dir ###"; echo
84
        @echo $(COMMON_RTL_VERILOG_MODULES)
85
 
86
# List of verilog source files (only .v files!)
87
# Board RTL modules first
88
RTL_VERILOG_SRC=$(shell for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then ls $(BOARD_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
89
# Common RTL module source
90
RTL_VERILOG_SRC +=$(shell for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then ls $(COMMON_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
91
 
92
# List of verilog includes from board RTL path - only for rule sensitivity
93
RTL_VERILOG_INCLUDES=$(shell ls $(BOARD_RTL_VERILOG_INCLUDE_DIR)/*.*)
94
 
95
#
96
# Add backend files here, except for the proasic3 library
97
#
98
RTL_VERILOG_SRC+=$(shell ls $(BACKEND_VERILOG_DIR)/*.v)
99
 
100
#
101
# VHDL DUT source variables
102
#
103
# VHDL modules
104
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
105
# VHDL sources
106
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
107
 
108
# Tool settings
109
# For Linux, the Actel licenses only support Synplify Pro
110
SYN_WORK_DIR            ?=synplify_work
111
SYN_SCRIPT              ?=synplify.prj  # We will generate this
112
SYN_LOG                 ?=syn.log
113
SYN_TOOL                ?=synplify_pro  # Name of the executable to call
114
# Options passed after the executable.
115 439 julius
SYN_LICENSE_OPTS        ?=-licensetype synplifypro_actel
116 408 julius
SYN_TOOL_OPTS           ?=$(SYN_SCRIPT) $(SYN_LICENSE_OPTS) -batch -log $(SYN_LOG)
117
 
118
 
119
SYN_PROJ_NAME ?= $(DESIGN_NAME)
120
RTL_TOP ?= $(DESIGN_NAME)_top
121
EDIF_FILE ?=$(RTL_TOP).edn
122
EDIF_FILE_OUT ?= ../out/$(EDIF_FILE)
123 411 julius
VLOG_NETLIST_FILE ?=$(RTL_TOP).vm
124
VLOG_NETLIST_FILE_OUT ?= ../out/$(VLOG_NETLIST_FILE)
125 408 julius
# Synthesis params
126
#FREQ ?= 50.0000
127
FREQ ?= 125.000
128
FPGA_FAMILY ?=ProASIC3E
129
#FPGA_PART ?=A3P1000
130
FPGA_PART ?=A3PE1500
131
FPGA_PACKAGE ?=PQFP208
132
#FPGA_SPEED_GRADE ?=-2
133
FPGA_SPEED_GRADE ?=Std
134
MAXFAN ?=50
135
MAXFAN_HARD ?=0
136
RETIMING ?=1
137
GLOBALTHRESH ?=50
138
DISABLE_IO_INSERTION ?= 0
139
RESOURCE_SHARING ?=1
140
 
141
# Time reporting variable
142
NUM_PATHS=50
143
NUM_ENDPOINTS=50
144
 
145
SDC_FILE=$(DESIGN_NAME)_top.sdc
146
 
147
# Rule to print out current config of current session
148
print-config:
149
        @echo; echo "\t### Synthesis make configuration ###"; echo
150
        @echo "\tRTL_TOP="$(RTL_TOP)
151
        @echo "\tFPGA_FAMILY="$(FPGA_FAMILY)
152
        @echo "\tFPGA_PART="$(FPGA_PART)
153
        @echo "\tFPGA_PACKAGE="$(FPGA_PACKAGE)
154
        @echo "\tFPGA_SPEED_GRADE="$(FPGA_SPEED_GRADE)
155
        @echo "\tFREQ="$(FREQ)
156
        @echo "\tMAXFAN="$(MAXFAN)
157
        @echo "\tMAXFAN_HARD="$(MAXFAN_HARD)
158
        @echo "\tRETIMING="$(RETIMING)
159
        @echo "\tGLOBALTHRESH="$(GLOBALTHRESH)
160
        @echo "\tDISABLE_IO_INSERTION="$(DISABLE_IO_INSERTION)
161
        @echo "\tRESOURCE_SHARING="$(RESOURCE_SHARING)
162
        @echo
163
 
164
 
165
 
166 411 julius
all: print-config $(EDIF_FILE_OUT) $(VLOG_NETLIST_FILE_OUT)
167 408 julius
 
168
#create the work dir
169
$(SYN_WORK_DIR):
170
        mkdir $(SYN_WORK_DIR)
171
 
172
#
173
# Dynamically created files included by different parts of the defines
174
#
175
 
176
BOOTROM_FILE=bootrom.v
177 415 julius
BOARD_SW_DIR=$(BOARD_DIR)/sw
178
BOARD_BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
179
BOOTROM_VERILOG=$(BOARD_BOOTROM_SW_DIR)/$(BOOTROM_FILE)
180 408 julius
bootrom: $(BOOTROM_VERILOG)
181 415 julius
$(BOOTROM_VERILOG):
182
        $(MAKE) -C $(BOARD_BOOTROM_SW_DIR) $(BOOTROM_FILE)
183 408 julius
 
184
SYNDIR_BOOTROM_VERILOG=$(SYN_WORK_DIR)/$(BOOTROM_FILE)
185
$(SYNDIR_BOOTROM_VERILOG): $(BOOTROM_VERILOG)
186
        cp $^ $@
187
 
188
TIMESCALE_FILE=timescale.v
189
SYNDIR_TIMESCALE_FILE=$(SYN_WORK_DIR)/$(TIMESCALE_FILE)
190
$(SYNDIR_TIMESCALE_FILE):
191
        $(Q)echo "" > $@
192
 
193
SYN_VERILOG_DEFINES=synthesis-defines.v
194
SYNDIR_SYN_VERILOG_DEFINES=$(SYN_WORK_DIR)/$(SYN_VERILOG_DEFINES)
195
$(SYNDIR_SYN_VERILOG_DEFINES):
196
        $(Q)echo "\`define SYNTHESIS" > $@
197
        $(Q)echo "\`define ACTEL" >> $@
198
        $(Q)echo "" >> $@
199
 
200
GENERATED_DEFINES = $(SYNDIR_BOOTROM_VERILOG)
201
GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE)
202
GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES)
203
 
204
# Generate the prj file
205
.PHONY: $(SYN_WORK_DIR)/$(SYN_SCRIPT)
206
$(SYN_WORK_DIR)/$(SYN_SCRIPT): $(SYN_WORK_DIR) $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(GENERATED_DEFINES) $(SYN_WORK_DIR)/$(SDC_FILE)
207
        $(Q)echo; echo "\t### Generating Synplify project file ###"; echo
208
        $(Q)echo -n "# Autogenerated synthesis script " > $@
209
        $(Q)date >> $@
210
        $(Q)for file in $(RTL_VERILOG_SRC); do \
211
                echo "add_file -verilog "$$file >> $@; \
212
        done
213
        $(Q)for file in $(RTL_VHDL_SRC); do \
214
                echo "add_file -vhdl "$$file >> $@; \
215
        done
216
        $(Q)echo "add_file -constraint "$(SDC_FILE) >> $@
217
        $(Q)echo "set_option -include_path "$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@
218
        $(Q)echo "set_option -include_path ." >> $@
219
        $(Q)echo "impl -add "$(SYN_PROJ_NAME)" -type fpga" >> $@
220
        $(Q)echo "set_option -technology "$(FPGA_FAMILY) >> $@
221
        $(Q)echo "set_option -part "$(FPGA_PART) >> $@
222
        $(Q)echo "set_option -package "$(FPGA_PACKAGE) >> $@
223
        $(Q)echo "set_option -speed_grade "$(FPGA_SPEED_GRADE) >> $@
224
        $(Q)echo "set_option -part_companion \"\"" >> $@
225
        $(Q)echo "set_option -use_fsm_explorer 0" >> $@
226
        $(Q)echo "set_option -top_module \""$(RTL_TOP)"\"" >> $@
227
        $(Q)echo "set_option -symbolic_fsm_compiler 1" >> $@
228
        $(Q)echo "set_option -compiler_compatible 0" >> $@
229
        $(Q)echo "set_option -resource_sharing "$(RESOURCE_SHARING) >> $@
230
        $(Q)echo "set_option -frequency "$(FREQ) >> $@
231
        $(Q)echo "set_option -write_verilog 1" >> $@
232
        $(Q)echo "set_option -write_vhdl 0" >> $@
233
        $(Q)echo "set_option -run_prop_extract 1" >> $@
234
        $(Q)echo "set_option -maxfan "$(MAXFAN) >> $@
235
        $(Q)echo "set_option -maxfan_hard "$(MAXFAN_HARD) >> $@
236
        $(Q)echo "set_option -disable_io_insertion "$(DISABLE_IO_INSERTION) >> $@
237
        $(Q)echo "set_option -retiming "$(RETIMING) >> $@
238
        $(Q)echo "set_option -report_path 4000" >> $@
239
        $(Q)echo "set_option -opcond COMWC" >> $@
240
        $(Q)echo "set_option -update_models_cp 0" >> $@
241
        $(Q)echo "set_option -preserve_registers 0" >> $@
242
        $(Q)echo "set_option -globalthreshold "$(GLOBALTHRESH) >> $@
243
        $(Q)echo "set_option -syn_global_buffers 18" >> $@
244
        $(Q)echo "set_option -reporting_filter {-from {*} -to {*}}" >> $@
245
        $(Q)echo "set_option -reporting_filename "$(RTL_TOP)".ta" >> $@
246
        $(Q)echo "set_option -reporting_output_srm 0" >> $@
247
        $(Q)echo "set_option -write_apr_constraint 1" >> $@
248
        $(Q)echo "project -result_format \"edif\"" >> $@
249
        $(Q)echo "project -result_file \""$(EDIF_FILE)"\"" >> $@
250
        $(Q)echo "set_option -vlog_std v2001" >> $@
251
        $(Q)echo "set_option -num_startend_points "$(NUM_ENDPOINTS) >> $@
252
        $(Q)echo "set_option -num_critical_paths "$(NUM_PATHS) >> $@
253
        $(Q)echo "set_option -project_relative_includes 1" >> $@
254
        $(Q)echo "impl -active \""$(SYN_PROJ_NAME)"\"" >> $@
255
 
256
#
257
# Constraint script generation
258
#
259
IN_CLK_PERIOD_NS = 15.625 # 64 MHz
260
WB_CLK_PERIOD_NS = 31.25 # 32 MHz
261
#
262
# Timing (SDC)
263
#
264
# I can't figure out how to get these constraints into synplify properly..
265
# but doesn't really appear to matter, we simply overconstrain the whole
266
# thing to fastest frequency we need, which is currently:
267
# SMII @ 125MHz
268
#
269
$(SYN_WORK_DIR)/$(SDC_FILE):
270
        $(Q)echo; echo "\t### Generating SDC file ###"; echo
271
        $(Q)rm -f $@
272
        $(Q)echo >> $@
273
#       $(Q)echo "create_clock  -name { sys_clk } -period "$(IN_CLK_PERIOD_NS)" { p:sys_clk  } " >> $@
274
#       $(Q)echo "create_clock  -name { tck_pad_i } -period 100.000 -waveform { 0.000 50.000  }  { p:tck_pad_i  } " >> $@
275
#       $(Q)echo "create_generated_clock  -name { clkgen0/pll0/Core:GLA } -divide_by 72  -multiply_by 36  -source { clkgen0/pll0/Core:CLKA } { clkgen0/pll0/Core:GLA  }" >> $@
276
#       $(Q)echo "create_generated_clock  -name { clkgen0/pll0/Core:GLB } -divide_by 36  -multiply_by 36  -source { clkgen0/pll0/Core:CLKA } { clkgen0/pll0/Core:GLB  } " >> $@
277
#       $(Q)echo "create_generated_clock  -name { clkgen0.pll0.wb_clk_i } -divide_by 72  -multiply_by 36  -source { t:clkgen0.pll0.wb_clk_i } { t:clkgen0.pll0.wb_clk_i  }" >> $@
278
 
279
 
280
# change into work dir, call synplify, hopefully create the edif
281
$(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(EDIF_FILE): $(SYN_WORK_DIR)/$(SYN_SCRIPT)
282
        cd $(SYN_WORK_DIR) && time $(SYN_TOOL) $(SYN_TOOL_OPTS)
283
 
284
##
285
# Generate a report for each module, and for whole thing
286
##
287
MODULES ?=arbiter_ibus arbiter_dbus arbiter_bytebus jtag_tap or1200_top dbg_if rom ram_wb uart16550 spacewire_wb_if mp2_top simple_spi i2c_core_wb_if usbslave scet gpio versatile_mem_ctrl urtu_top
288
MODULES_SRR=$(shell for mod in $(MODULES); do echo $(SYN_WORK_DIR)"/"$(SYN_PROJ_NAME)"/"$$mod".srr"; done)
289
 
290
syn-report: $(MODULES_SRR)
291
        rm -f $@
292
        for srrfile in $^; do \
293
                echo `echo $$srrfile | xargs basename | cut -d '.' -f 1`>> $@; \
294
                grep "Core Cells" $$srrfile >> $@; \
295
                grep "Block Rams" $$srrfile >> $@; \
296
                grep -B 1 -A 5 "Starting Clock" $$srrfile >> $@; \
297
                echo >> $@; echo >> $@; \
298
        done
299
 
300
%.srr:
301
        @echo; echo "\tGenerating "$@; echo
302
        export RTL_TOP=$(shell echo $@ | xargs basename | cut -d '.' -f 1); \
303
        $(MAKE) $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$$RTL_TOP.edn
304
 
305
 
306
$(EDIF_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(EDIF_FILE)
307
        cp $^ $@
308
 
309 411 julius
$(VLOG_NETLIST_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(VLOG_NETLIST_FILE)
310
        cp $^ $@
311
 
312 449 julius
distclean: clean-sw clean clean-edifs
313 408 julius
 
314
clean-sw:
315 449 julius
        $(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean
316 408 julius
 
317
clean: clean-build
318
 
319
clean-edifs:
320
        rm -f *.edn ../out/*
321
 
322
clean-build:
323
        rm -rf $(SYN_WORK_DIR) *.edn
324
 
325
clean-srr:
326
        rm $(MODULES_SRR)

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