OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [include/] [uart_defines.v] - Blame information for rev 627

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 627 stekern
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  uart_defines.v                                              ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the "UART 16550 compatible" project    ////
7
////  http://www.opencores.org/cores/uart16550/                   ////
8
////                                                              ////
9
////  Documentation related to this project:                      ////
10
////  - http://www.opencores.org/cores/uart16550/                 ////
11
////                                                              ////
12
////  Projects compatibility:                                     ////
13
////  - WISHBONE                                                  ////
14
////  RS232 Protocol                                              ////
15
////  16550D uart (mostly supported)                              ////
16
////                                                              ////
17
////  Overview (main Features):                                   ////
18
////  Defines of the Core                                         ////
19
////                                                              ////
20
////  Known problems (limits):                                    ////
21
////  None                                                        ////
22
////                                                              ////
23
////  To Do:                                                      ////
24
////  Nothing.                                                    ////
25
////                                                              ////
26
////  Author(s):                                                  ////
27
////      - gorban@opencores.org                                  ////
28
////      - Jacob Gorban                                          ////
29
////      - Igor Mohor (igorm@opencores.org)                      ////
30
////                                                              ////
31
////  Created:        2001/05/12                                  ////
32
////  Last Updated:   2001/05/17                                  ////
33
////                  (See log for the revision history)          ////
34
////                                                              ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
////                                                              ////
38
//// Copyright (C) 2000, 2001 Authors                             ////
39
////                                                              ////
40
//// This source file may be used and distributed without         ////
41
//// restriction provided that this copyright statement is not    ////
42
//// removed from the file and that any derivative work contains  ////
43
//// the original copyright notice and the associated disclaimer. ////
44
////                                                              ////
45
//// This source file is free software; you can redistribute it   ////
46
//// and/or modify it under the terms of the GNU Lesser General   ////
47
//// Public License as published by the Free Software Foundation; ////
48
//// either version 2.1 of the License, or (at your option) any   ////
49
//// later version.                                               ////
50
////                                                              ////
51
//// This source is distributed in the hope that it will be       ////
52
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55
//// details.                                                     ////
56
////                                                              ////
57
//// You should have received a copy of the GNU Lesser General    ////
58
//// Public License along with this source; if not, download it   ////
59
//// from http://www.opencores.org/lgpl.shtml                     ////
60
////                                                              ////
61
//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65
// $Log: not supported by cvs2svn $
66
// Revision 1.13  2003/06/11 16:37:47  gorban
67
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
68
//
69
// Revision 1.12  2002/07/22 23:02:23  gorban
70
// Bug Fixes:
71
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
72
//   Problem reported by Kenny.Tung.
73
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
74
//
75
// Improvements:
76
//  * Made FIFO's as general inferrable memory where possible.
77
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
78
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
79
//
80
//  * Added optional baudrate output (baud_o).
81
//  This is identical to BAUDOUT* signal on 16550 chip.
82
//  It outputs 16xbit_clock_rate - the divided clock.
83
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
84
//
85
// Revision 1.10  2001/12/11 08:55:40  mohor
86
// Scratch register define added.
87
//
88
// Revision 1.9  2001/12/03 21:44:29  gorban
89
// Updated specification documentation.
90
// Added full 32-bit data bus interface, now as default.
91
// Address is 5-bit wide in 32-bit data bus mode.
92
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
93
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
94
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
95
// My small test bench is modified to work with 32-bit mode.
96
//
97
// Revision 1.8  2001/11/26 21:38:54  gorban
98
// Lots of fixes:
99
// Break condition wasn't handled correctly at all.
100
// LSR bits could lose their values.
101
// LSR value after reset was wrong.
102
// Timing of THRE interrupt signal corrected.
103
// LSR bit 0 timing corrected.
104
//
105
// Revision 1.7  2001/08/24 21:01:12  mohor
106
// Things connected to parity changed.
107
// Clock devider changed.
108
//
109
// Revision 1.6  2001/08/23 16:05:05  mohor
110
// Stop bit bug fixed.
111
// Parity bug fixed.
112
// WISHBONE read cycle bug fixed,
113
// OE indicator (Overrun Error) bug fixed.
114
// PE indicator (Parity Error) bug fixed.
115
// Register read bug fixed.
116
//
117
// Revision 1.5  2001/05/31 20:08:01  gorban
118
// FIFO changes and other corrections.
119
//
120
// Revision 1.4  2001/05/21 19:12:02  gorban
121
// Corrected some Linter messages.
122
//
123
// Revision 1.3  2001/05/17 18:34:18  gorban
124
// First 'stable' release. Should be sythesizable now. Also added new header.
125
//
126
// Revision 1.0  2001-05-17 21:27:11+02  jacob
127
// Initial revision
128
//
129
//
130
 
131
// remove comments to restore to use the new version with 8 data bit interface
132
// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
133
// also, in 8-bit version there'll be no debugging features included
134
// CAUTION: doesn't work with current version of OR1200
135
`define DATA_BUS_WIDTH_8
136
 
137
`ifdef DATA_BUS_WIDTH_8
138
 `define UART_ADDR_WIDTH 3
139
 `define UART_DATA_WIDTH 8
140
`else
141
 `define UART_ADDR_WIDTH 5
142
 `define UART_DATA_WIDTH 32
143
`endif
144
 
145
// Uncomment this if you want your UART to have
146
// 16xBaudrate output port.
147
// If defined, the enable signal will be used to drive baudrate_o signal
148
// It's frequency is 16xbaudrate
149
 
150
// `define UART_HAS_BAUDRATE_OUTPUT
151
 
152
// Register addresses
153
`define UART_REG_RB     `UART_ADDR_WIDTH'd0     // receiver buffer
154
`define UART_REG_TR  `UART_ADDR_WIDTH'd0        // transmitter
155
`define UART_REG_IE     `UART_ADDR_WIDTH'd1     // Interrupt enable
156
`define UART_REG_II  `UART_ADDR_WIDTH'd2        // Interrupt identification
157
`define UART_REG_FC  `UART_ADDR_WIDTH'd2        // FIFO control
158
`define UART_REG_LC     `UART_ADDR_WIDTH'd3     // Line Control
159
`define UART_REG_MC     `UART_ADDR_WIDTH'd4     // Modem control
160
`define UART_REG_LS  `UART_ADDR_WIDTH'd5        // Line status
161
`define UART_REG_MS  `UART_ADDR_WIDTH'd6        // Modem status
162
`define UART_REG_SR  `UART_ADDR_WIDTH'd7        // Scratch register
163
`define UART_REG_DL1    `UART_ADDR_WIDTH'd0     // Divisor latch bytes (1-2)
164
`define UART_REG_DL2    `UART_ADDR_WIDTH'd1
165
 
166
// Interrupt Enable register bits
167
`define UART_IE_RDA     0        // Received Data available interrupt
168
`define UART_IE_THRE    1       // Transmitter Holding Register empty interrupt
169
`define UART_IE_RLS     2       // Receiver Line Status Interrupt
170
`define UART_IE_MS      3       // Modem Status Interrupt
171
 
172
// Interrupt Identification register bits
173
`define UART_II_IP      0        // Interrupt pending when 0
174
`define UART_II_II      3:1     // Interrupt identification
175
 
176
// Interrupt identification values for bits 3:1
177
`define UART_II_RLS     3'b011  // Receiver Line Status
178
`define UART_II_RDA     3'b010  // Receiver Data available
179
`define UART_II_TI      3'b110  // Timeout Indication
180
`define UART_II_THRE    3'b001  // Transmitter Holding Register empty
181
`define UART_II_MS      3'b000  // Modem Status
182
 
183
// FIFO Control Register bits
184
`define UART_FC_TL      1:0      // Trigger level
185
 
186
// FIFO trigger level values
187
`define UART_FC_1               2'b00
188
`define UART_FC_4               2'b01
189
`define UART_FC_8               2'b10
190
`define UART_FC_14      2'b11
191
 
192
// Line Control register bits
193
`define UART_LC_BITS    1:0      // bits in character
194
`define UART_LC_SB      2       // stop bits
195
`define UART_LC_PE      3       // parity enable
196
`define UART_LC_EP      4       // even parity
197
`define UART_LC_SP      5       // stick parity
198
`define UART_LC_BC      6       // Break control
199
`define UART_LC_DL      7       // Divisor Latch access bit
200
 
201
// Modem Control register bits
202
`define UART_MC_DTR     0
203
`define UART_MC_RTS     1
204
`define UART_MC_OUT1    2
205
`define UART_MC_OUT2    3
206
`define UART_MC_LB      4       // Loopback mode
207
 
208
// Line Status Register bits
209
`define UART_LS_DR      0        // Data ready
210
`define UART_LS_OE      1       // Overrun Error
211
`define UART_LS_PE      2       // Parity Error
212
`define UART_LS_FE      3       // Framing Error
213
`define UART_LS_BI      4       // Break interrupt
214
`define UART_LS_TFE     5       // Transmit FIFO is empty
215
`define UART_LS_TE      6       // Transmitter Empty indicator
216
`define UART_LS_EI      7       // Error indicator
217
 
218
// Modem Status Register bits
219
`define UART_MS_DCTS    0        // Delta signals
220
`define UART_MS_DDSR    1
221
`define UART_MS_TERI    2
222
`define UART_MS_DDCD    3
223
`define UART_MS_CCTS    4       // Complement signals
224
`define UART_MS_CDSR    5
225
`define UART_MS_CRI     6
226
`define UART_MS_CDCD    7
227
 
228
// FIFO parameter defines
229
 
230
`define UART_FIFO_WIDTH 8
231
`define UART_FIFO_DEPTH 16
232
`define UART_FIFO_POINTER_W     4
233
`define UART_FIFO_COUNTER_W     5
234
// receiver fifo has width 11 because it has break, parity and framing error bits
235
`define UART_FIFO_REC_WIDTH  11
236
 
237
 
238
`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
239
`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
240
`define FAST_TEST   1           // 64/1024 packets are sent
241
 
242
// Defines hard baud prescaler register - uncomment to enable
243
//`define PRESCALER_PRESET_HARD
244
// 115200 baud preset values
245
// 20MHz: prescaler 10.8 (11, rounded up)
246
//`define PRESCALER_HIGH_PRESET 8'd0
247
//`define PRESCALER_LOW_PRESET 8'd11
248
// 50MHz: prescaler 27.1
249
//`define PRESCALER_HIGH_PRESET 8'd0
250
//`define PRESCALER_LOW_PRESET 8'd27
251
// 66MHz: prescaler 36.1
252
//`define PRESCALER_HIGH_PRESET 8'd0
253
//`define PRESCALER_LOW_PRESET 8'd36
254
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.