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//////////////////////////////////////////////////////////////////////

///                                                               //// 

/// ORPSoC top for Atlys board                                    ////

///                                                               ////

/// Instantiates modules, depending on ORPSoC defines file        ////

///                                                               ////

/// Julius Baxter, julius@opencores.org                           ////

/// Contributor(s):                                               ////

///   Stefan Kristiansson, stefan.kristiansson@saunalahti.fi      ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

`include "orpsoc-defines.v"

`include "synthesis-defines.v"

module orpsoc_top

  (

`ifdef JTAG_DEBUG

    tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i,

`endif

`ifdef XILINX_DDR2

    ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n,

    ddr2_rzq, ddr2_zio, ddr2_odt, ddr2_cke, ddr2_dm, ddr2_udm,

    ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_udqs, ddr2_udqs_n,

    ddr2_ck, ddr2_ck_n,

`endif

`ifdef XILINX_SSRAM

    sram_clk, sram_clk_fb, sram_flash_addr, sram_flash_data,

    sram_cen, sram_flash_oe_n, sram_flash_we_n, sram_bw,

    sram_adv_ld_n, sram_mode,

`endif

`ifdef UART0

    uart0_srx_pad_i, uart0_stx_pad_o,

`ifdef UART0_EXPHEADER

    uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o,

`endif

`endif

`ifdef SPI0

    spi0_mosi_o, spi0_ss_o, spi0_sck_o, spi0_miso_i,

`endif

`ifdef I2C0

    i2c0_sda_io, i2c0_scl_io,

`endif

`ifdef I2C1

    i2c1_sda_io, i2c1_scl_io,

`endif

`ifdef GPIO0

    gpio0_io,

`endif

`ifdef ETH0

    eth0_tx_clk, eth0_tx_data, eth0_tx_en, eth0_tx_er,

    eth0_rx_clk, eth0_rx_data, eth0_dv, eth0_rx_er,

    eth0_col, eth0_crs,

    eth0_mdc_pad_o, eth0_md_pad_io,

 `ifdef ETH0_PHY_RST

    eth0_rst_n_o,

 `endif

`endif

    sys_clk_in,

    rst_n_pad_i

    );

`include "orpsoc-params.v"

   input sys_clk_in;

   input rst_n_pad_i;

`ifdef JTAG_DEBUG

   output tdo_pad_o;

   input  tms_pad_i;

   input  tck_pad_i;

   input  tdi_pad_i;

`endif

`ifdef XILINX_DDR2

   output [12:0]               ddr2_a;

   output [2:0]        ddr2_ba;

   output                     ddr2_ras_n;

   output                     ddr2_cas_n;

   output                         ddr2_we_n;

   output                 ddr2_rzq;

   output                 ddr2_zio;

   output                     ddr2_odt;

   output                     ddr2_cke;

   output                     ddr2_dm;

   output                     ddr2_udm;

   inout [15:0]        ddr2_dq;

   inout                      ddr2_dqs;

   inout                      ddr2_dqs_n;

   inout                      ddr2_udqs;

   inout                      ddr2_udqs_n;

   output                     ddr2_ck;

   output                     ddr2_ck_n;

`endif

`ifdef UART0

   input         uart0_srx_pad_i;

   output        uart0_stx_pad_o;

   // Duplicates of the UART signals, this time to the USB debug cable

`ifdef UART0_EXPHEADER

   input         uart0_srx_expheader_pad_i;

   output        uart0_stx_expheader_pad_o;

`endif

`endif

`ifdef SPI0

   output        spi0_mosi_o;

   output [spi0_ss_width-1:0] spi0_ss_o;

   output                    spi0_sck_o;

   input                     spi0_miso_i;

`endif

`ifdef I2C0

   inout                      i2c0_sda_io, i2c0_scl_io;

`endif

`ifdef I2C1

   inout                      i2c1_sda_io, i2c1_scl_io;

`endif

`ifdef GPIO0

   inout [gpio0_io_width-1:0] gpio0_io;

`endif

`ifdef ETH0

   input                      eth0_tx_clk;

   output [3:0]        eth0_tx_data;

   output                     eth0_tx_en;

   output                     eth0_tx_er;

   input                      eth0_rx_clk;

   input [3:0]                 eth0_rx_data;

   input                      eth0_dv;

   input                      eth0_rx_er;

   input                      eth0_col;

   input                      eth0_crs;

   output                     eth0_mdc_pad_o;

   inout                      eth0_md_pad_io;

 `ifdef ETH0_PHY_RST

   output                     eth0_rst_n_o;

 `endif

`endif //  `ifdef ETH0

   ////////////////////////////////////////////////////////////////////////

   //

   // Clock and reset generation module

   // 

   ////////////////////////////////////////////////////////////////////////

   //

   // Wires

   //

   wire                       wb_clk, wb_rst;

   wire                       ddr2_if_clk, ddr2_if_rst;

   wire                       clk100;

   wire                       dbg_tck;

   clkgen clkgen0

     (

      .sys_clk_in                (sys_clk_in),

      .wb_clk_o                  (wb_clk),

      .wb_rst_o                  (wb_rst),

`ifdef JTAG_DEBUG

      .tck_pad_i                 (tck_pad_i),

      .dbg_tck_o                 (dbg_tck),

`endif

`ifdef XILINX_DDR2

      .ddr2_if_clk_o             (ddr2_if_clk),

      .ddr2_if_rst_o             (ddr2_if_rst),

      .clk100_o                  (clk100),

`endif

      // Asynchronous active low reset

      .rst_n_pad_i               (rst_n_pad_i)

      );

   ////////////////////////////////////////////////////////////////////////

   //

   // Arbiter

   // 

   ////////////////////////////////////////////////////////////////////////

   // Wire naming convention:

   // First: wishbone master or slave (wbm/wbs)

   // Second: Which bus it's on instruction or data (i/d)

   // Third: Between which module and the arbiter the wires are

   // Fourth: Signal name

   // Fifth: Direction relative to module (not bus/arbiter!)

   //        ie. wbm_d_or12_adr_o is address OUT from the or1200

   // OR1200 instruction bus wires

   wire [wb_aw-1:0]            wbm_i_or12_adr_o;

   wire [wb_dw-1:0]            wbm_i_or12_dat_o;

   wire [3:0]                  wbm_i_or12_sel_o;

   wire                       wbm_i_or12_we_o;

   wire                       wbm_i_or12_cyc_o;

   wire                       wbm_i_or12_stb_o;

   wire [2:0]                  wbm_i_or12_cti_o;

   wire [1:0]                  wbm_i_or12_bte_o;

   wire [wb_dw-1:0]            wbm_i_or12_dat_i;

   wire                       wbm_i_or12_ack_i;

   wire                       wbm_i_or12_err_i;

   wire                       wbm_i_or12_rty_i;

   // OR1200 data bus wires   

   wire [wb_aw-1:0]            wbm_d_or12_adr_o;

   wire [wb_dw-1:0]            wbm_d_or12_dat_o;

   wire [3:0]                  wbm_d_or12_sel_o;

   wire                       wbm_d_or12_we_o;

   wire                       wbm_d_or12_cyc_o;

   wire                       wbm_d_or12_stb_o;

   wire [2:0]                  wbm_d_or12_cti_o;

   wire [1:0]                  wbm_d_or12_bte_o;

   wire [wb_dw-1:0]            wbm_d_or12_dat_i;

   wire                       wbm_d_or12_ack_i;

   wire                       wbm_d_or12_err_i;

   wire                       wbm_d_or12_rty_i;

   // Debug interface bus wires   

   wire [wb_aw-1:0]            wbm_d_dbg_adr_o;

   wire [wb_dw-1:0]            wbm_d_dbg_dat_o;

   wire [3:0]                  wbm_d_dbg_sel_o;

   wire                       wbm_d_dbg_we_o;

   wire                       wbm_d_dbg_cyc_o;

   wire                       wbm_d_dbg_stb_o;

   wire [2:0]                  wbm_d_dbg_cti_o;

   wire [1:0]                  wbm_d_dbg_bte_o;

   wire [wb_dw-1:0]            wbm_d_dbg_dat_i;

   wire                       wbm_d_dbg_ack_i;

   wire                       wbm_d_dbg_err_i;

   wire                       wbm_d_dbg_rty_i;

   // Byte bus bridge master signals

   wire [wb_aw-1:0]            wbm_b_d_adr_o;

   wire [wb_dw-1:0]            wbm_b_d_dat_o;

   wire [3:0]                  wbm_b_d_sel_o;

   wire                       wbm_b_d_we_o;

   wire                       wbm_b_d_cyc_o;

   wire                       wbm_b_d_stb_o;

   wire [2:0]                  wbm_b_d_cti_o;

   wire [1:0]                  wbm_b_d_bte_o;

   wire [wb_dw-1:0]            wbm_b_d_dat_i;

   wire                       wbm_b_d_ack_i;

   wire                       wbm_b_d_err_i;

   wire                       wbm_b_d_rty_i;

   // Instruction bus slave wires //

   // rom0 instruction bus wires

   wire [31:0]                 wbs_i_rom0_adr_i;

   wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_i;

   wire [3:0]                        wbs_i_rom0_sel_i;

   wire                             wbs_i_rom0_we_i;

   wire                             wbs_i_rom0_cyc_i;

   wire                             wbs_i_rom0_stb_i;

   wire [2:0]                        wbs_i_rom0_cti_i;

   wire [1:0]                        wbs_i_rom0_bte_i;

   wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_o;

   wire                             wbs_i_rom0_ack_o;

   wire                             wbs_i_rom0_err_o;

   wire                             wbs_i_rom0_rty_o;

   // mc0 instruction bus wires

   wire [31:0]                       wbs_i_mc0_adr_i;

   wire [wbs_i_mc0_data_width-1:0]  wbs_i_mc0_dat_i;

   wire [3:0]                        wbs_i_mc0_sel_i;

   wire                             wbs_i_mc0_we_i;

   wire                             wbs_i_mc0_cyc_i;

   wire                             wbs_i_mc0_stb_i;

   wire [2:0]                        wbs_i_mc0_cti_i;

   wire [1:0]                        wbs_i_mc0_bte_i;

   wire [wbs_i_mc0_data_width-1:0]  wbs_i_mc0_dat_o;

   wire                             wbs_i_mc0_ack_o;

   wire                             wbs_i_mc0_err_o;

   wire                             wbs_i_mc0_rty_o;

   // Data bus slave wires //

   // mc0 data bus wires

   wire [31:0]                       wbs_d_mc0_adr_i;

   wire [wbs_d_mc0_data_width-1:0]  wbs_d_mc0_dat_i;

   wire [3:0]                        wbs_d_mc0_sel_i;

   wire                             wbs_d_mc0_we_i;

   wire                             wbs_d_mc0_cyc_i;

   wire                             wbs_d_mc0_stb_i;

   wire [2:0]                        wbs_d_mc0_cti_i;

   wire [1:0]                        wbs_d_mc0_bte_i;

   wire [wbs_d_mc0_data_width-1:0]  wbs_d_mc0_dat_o;

   wire                             wbs_d_mc0_ack_o;

   wire                             wbs_d_mc0_err_o;

   wire                             wbs_d_mc0_rty_o;

   // i2c0 wires

   wire [31:0]                       wbs_d_i2c0_adr_i;

   wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i;

   wire [3:0]                        wbs_d_i2c0_sel_i;

   wire                             wbs_d_i2c0_we_i;

   wire                             wbs_d_i2c0_cyc_i;

   wire                             wbs_d_i2c0_stb_i;

   wire [2:0]                        wbs_d_i2c0_cti_i;

   wire [1:0]                        wbs_d_i2c0_bte_i;

   wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o;

   wire                             wbs_d_i2c0_ack_o;

   wire                             wbs_d_i2c0_err_o;

   wire                             wbs_d_i2c0_rty_o;

   // i2c1 wires

   wire [31:0]                       wbs_d_i2c1_adr_i;

   wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i;

   wire [3:0]                        wbs_d_i2c1_sel_i;

   wire                             wbs_d_i2c1_we_i;

   wire                             wbs_d_i2c1_cyc_i;

   wire                             wbs_d_i2c1_stb_i;

   wire [2:0]                        wbs_d_i2c1_cti_i;

   wire [1:0]                        wbs_d_i2c1_bte_i;

   wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o;

   wire                             wbs_d_i2c1_ack_o;

   wire                             wbs_d_i2c1_err_o;

   wire                             wbs_d_i2c1_rty_o;

   // spi0 wires

   wire [31:0]                       wbs_d_spi0_adr_i;

   wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i;

   wire [3:0]                        wbs_d_spi0_sel_i;

   wire                             wbs_d_spi0_we_i;

   wire                             wbs_d_spi0_cyc_i;

   wire                             wbs_d_spi0_stb_i;

   wire [2:0]                        wbs_d_spi0_cti_i;

   wire [1:0]                        wbs_d_spi0_bte_i;

   wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o;

   wire                             wbs_d_spi0_ack_o;

   wire                             wbs_d_spi0_err_o;

   wire                             wbs_d_spi0_rty_o;

   // uart0 wires

   wire [31:0]                        wbs_d_uart0_adr_i;

   wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i;

   wire [3:0]                         wbs_d_uart0_sel_i;

   wire                              wbs_d_uart0_we_i;

   wire                              wbs_d_uart0_cyc_i;

   wire                              wbs_d_uart0_stb_i;

   wire [2:0]                         wbs_d_uart0_cti_i;

   wire [1:0]                         wbs_d_uart0_bte_i;

   wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o;

   wire                              wbs_d_uart0_ack_o;

   wire                              wbs_d_uart0_err_o;

   wire                              wbs_d_uart0_rty_o;

   // gpio0 wires

   wire [31:0]                        wbs_d_gpio0_adr_i;

   wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i;

   wire [3:0]                         wbs_d_gpio0_sel_i;

   wire                              wbs_d_gpio0_we_i;

   wire                              wbs_d_gpio0_cyc_i;

   wire                              wbs_d_gpio0_stb_i;

   wire [2:0]                         wbs_d_gpio0_cti_i;

   wire [1:0]                         wbs_d_gpio0_bte_i;

   wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o;

   wire                              wbs_d_gpio0_ack_o;

   wire                              wbs_d_gpio0_err_o;

   wire                              wbs_d_gpio0_rty_o;

   // eth0 slave wires

   wire [31:0]                             wbs_d_eth0_adr_i;

   wire [wbs_d_eth0_data_width-1:0]        wbs_d_eth0_dat_i;

   wire [3:0]                              wbs_d_eth0_sel_i;

   wire                                   wbs_d_eth0_we_i;

   wire                                   wbs_d_eth0_cyc_i;

   wire                                   wbs_d_eth0_stb_i;

   wire [2:0]                              wbs_d_eth0_cti_i;

   wire [1:0]                              wbs_d_eth0_bte_i;

   wire [wbs_d_eth0_data_width-1:0]        wbs_d_eth0_dat_o;

   wire                                   wbs_d_eth0_ack_o;

   wire                                   wbs_d_eth0_err_o;

   wire                                   wbs_d_eth0_rty_o;

   // eth0 master wires

   wire [wbm_eth0_addr_width-1:0]          wbm_eth0_adr_o;

   wire [wbm_eth0_data_width-1:0]          wbm_eth0_dat_o;

   wire [3:0]                              wbm_eth0_sel_o;

   wire                                   wbm_eth0_we_o;

   wire                                   wbm_eth0_cyc_o;

   wire                                   wbm_eth0_stb_o;

   wire [2:0]                              wbm_eth0_cti_o;

   wire [1:0]                              wbm_eth0_bte_o;

   wire [wbm_eth0_data_width-1:0]         wbm_eth0_dat_i;

   wire                                   wbm_eth0_ack_i;

   wire                                   wbm_eth0_err_i;

   wire                                   wbm_eth0_rty_i;

   //

   // Wishbone instruction bus arbiter

   //

   arbiter_ibus arbiter_ibus0

     (

      // Instruction Bus Master

      // Inputs to arbiter from master

      .wbm_adr_o                        (wbm_i_or12_adr_o),

      .wbm_dat_o                        (wbm_i_or12_dat_o),

      .wbm_sel_o                        (wbm_i_or12_sel_o),

      .wbm_we_o                         (wbm_i_or12_we_o),

      .wbm_cyc_o                        (wbm_i_or12_cyc_o),

      .wbm_stb_o                        (wbm_i_or12_stb_o),

      .wbm_cti_o                        (wbm_i_or12_cti_o),

      .wbm_bte_o                        (wbm_i_or12_bte_o),

      // Outputs to master from arbiter

      .wbm_dat_i                        (wbm_i_or12_dat_i),

      .wbm_ack_i                        (wbm_i_or12_ack_i),

      .wbm_err_i                        (wbm_i_or12_err_i),

      .wbm_rty_i                        (wbm_i_or12_rty_i),

      // Slave 0

      // Inputs to slave from arbiter

      .wbs0_adr_i                       (wbs_i_rom0_adr_i),

      .wbs0_dat_i                       (wbs_i_rom0_dat_i),

      .wbs0_sel_i                       (wbs_i_rom0_sel_i),

      .wbs0_we_i                        (wbs_i_rom0_we_i),

      .wbs0_cyc_i                       (wbs_i_rom0_cyc_i),

      .wbs0_stb_i                       (wbs_i_rom0_stb_i),

      .wbs0_cti_i                       (wbs_i_rom0_cti_i),

      .wbs0_bte_i                       (wbs_i_rom0_bte_i),

      // Outputs from slave to arbiter      

      .wbs0_dat_o                       (wbs_i_rom0_dat_o),

      .wbs0_ack_o                       (wbs_i_rom0_ack_o),

      .wbs0_err_o                       (wbs_i_rom0_err_o),

      .wbs0_rty_o                       (wbs_i_rom0_rty_o),

      // Slave 1

      // Inputs to slave from arbiter

      .wbs1_adr_i                       (wbs_i_mc0_adr_i),

      .wbs1_dat_i                       (wbs_i_mc0_dat_i),

      .wbs1_sel_i                       (wbs_i_mc0_sel_i),

      .wbs1_we_i                        (wbs_i_mc0_we_i),

      .wbs1_cyc_i                       (wbs_i_mc0_cyc_i),

      .wbs1_stb_i                       (wbs_i_mc0_stb_i),

      .wbs1_cti_i                       (wbs_i_mc0_cti_i),

      .wbs1_bte_i                       (wbs_i_mc0_bte_i),

      // Outputs from slave to arbiter

      .wbs1_dat_o                       (wbs_i_mc0_dat_o),

      .wbs1_ack_o                       (wbs_i_mc0_ack_o),

      .wbs1_err_o                       (wbs_i_mc0_err_o),

      .wbs1_rty_o                       (wbs_i_mc0_rty_o),

      // Clock, reset inputs

      .wb_clk                           (wb_clk),

      .wb_rst                           (wb_rst));

   defparam arbiter_ibus0.wb_addr_match_width = ibus_arb_addr_match_width;

   defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // FLASH ROM

   defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // Main memory

   //

   // Wishbone data bus arbiter

   //

   arbiter_dbus arbiter_dbus0

     (

      // Master 0

      // Inputs to arbiter from master

      .wbm0_adr_o                       (wbm_d_or12_adr_o),

      .wbm0_dat_o                       (wbm_d_or12_dat_o),

      .wbm0_sel_o                       (wbm_d_or12_sel_o),

      .wbm0_we_o                        (wbm_d_or12_we_o),

      .wbm0_cyc_o                       (wbm_d_or12_cyc_o),

      .wbm0_stb_o                       (wbm_d_or12_stb_o),

      .wbm0_cti_o                       (wbm_d_or12_cti_o),

      .wbm0_bte_o                       (wbm_d_or12_bte_o),

      // Outputs to master from arbiter

      .wbm0_dat_i                       (wbm_d_or12_dat_i),

      .wbm0_ack_i                       (wbm_d_or12_ack_i),

      .wbm0_err_i                       (wbm_d_or12_err_i),

      .wbm0_rty_i                       (wbm_d_or12_rty_i),

      // Master 0

      // Inputs to arbiter from master

      .wbm1_adr_o                       (wbm_d_dbg_adr_o),

      .wbm1_dat_o                       (wbm_d_dbg_dat_o),

      .wbm1_we_o                        (wbm_d_dbg_we_o),

      .wbm1_cyc_o                       (wbm_d_dbg_cyc_o),

      .wbm1_sel_o                       (wbm_d_dbg_sel_o),

      .wbm1_stb_o                       (wbm_d_dbg_stb_o),

      .wbm1_cti_o                       (wbm_d_dbg_cti_o),

      .wbm1_bte_o                       (wbm_d_dbg_bte_o),

      // Outputs to master from arbiter      

      .wbm1_dat_i                       (wbm_d_dbg_dat_i),

      .wbm1_ack_i                       (wbm_d_dbg_ack_i),

      .wbm1_err_i                       (wbm_d_dbg_err_i),

      .wbm1_rty_i                       (wbm_d_dbg_rty_i),

      // Slaves

      .wbs0_adr_i                       (wbs_d_mc0_adr_i),

      .wbs0_dat_i                       (wbs_d_mc0_dat_i),

      .wbs0_sel_i                       (wbs_d_mc0_sel_i),

      .wbs0_we_i                        (wbs_d_mc0_we_i),

      .wbs0_cyc_i                       (wbs_d_mc0_cyc_i),

      .wbs0_stb_i                       (wbs_d_mc0_stb_i),

      .wbs0_cti_i                       (wbs_d_mc0_cti_i),

      .wbs0_bte_i                       (wbs_d_mc0_bte_i),

      .wbs0_dat_o                       (wbs_d_mc0_dat_o),

      .wbs0_ack_o                       (wbs_d_mc0_ack_o),

      .wbs0_err_o                       (wbs_d_mc0_err_o),

      .wbs0_rty_o                       (wbs_d_mc0_rty_o),

      .wbs1_adr_i                       (wbs_d_eth0_adr_i),

      .wbs1_dat_i                       (wbs_d_eth0_dat_i),

      .wbs1_sel_i                       (wbs_d_eth0_sel_i),

      .wbs1_we_i                        (wbs_d_eth0_we_i),

      .wbs1_cyc_i                       (wbs_d_eth0_cyc_i),

      .wbs1_stb_i                       (wbs_d_eth0_stb_i),

      .wbs1_cti_i                       (wbs_d_eth0_cti_i),

      .wbs1_bte_i                       (wbs_d_eth0_bte_i),

      .wbs1_dat_o                       (wbs_d_eth0_dat_o),

      .wbs1_ack_o                       (wbs_d_eth0_ack_o),

      .wbs1_err_o                       (wbs_d_eth0_err_o),

      .wbs1_rty_o                       (wbs_d_eth0_rty_o),

      .wbs2_adr_i                       (wbm_b_d_adr_o),

      .wbs2_dat_i                       (wbm_b_d_dat_o),

      .wbs2_sel_i                       (wbm_b_d_sel_o),

      .wbs2_we_i                        (wbm_b_d_we_o),

      .wbs2_cyc_i                       (wbm_b_d_cyc_o),

      .wbs2_stb_i                       (wbm_b_d_stb_o),

      .wbs2_cti_i                       (wbm_b_d_cti_o),

      .wbs2_bte_i                       (wbm_b_d_bte_o),

      .wbs2_dat_o                       (wbm_b_d_dat_i),

      .wbs2_ack_o                       (wbm_b_d_ack_i),

      .wbs2_err_o                       (wbm_b_d_err_i),

      .wbs2_rty_o                       (wbm_b_d_rty_i),

      // Clock, reset inputs

      .wb_clk                   (wb_clk),

      .wb_rst                   (wb_rst));

   // These settings are from top level params file

   defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width;

   defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;

   defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr;

   defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;

   //

   // Wishbone byte-wide bus arbiter

   //   

   arbiter_bytebus arbiter_bytebus0

     (

      // Master 0

      // Inputs to arbiter from master

      .wbm0_adr_o                       (wbm_b_d_adr_o),

      .wbm0_dat_o                       (wbm_b_d_dat_o),

      .wbm0_sel_o                       (wbm_b_d_sel_o),

      .wbm0_we_o                        (wbm_b_d_we_o),

      .wbm0_cyc_o                       (wbm_b_d_cyc_o),

      .wbm0_stb_o                       (wbm_b_d_stb_o),

      .wbm0_cti_o                       (wbm_b_d_cti_o),

      .wbm0_bte_o                       (wbm_b_d_bte_o),

      // Outputs to master from arbiter

      .wbm0_dat_i                       (wbm_b_d_dat_i),

      .wbm0_ack_i                       (wbm_b_d_ack_i),

      .wbm0_err_i                       (wbm_b_d_err_i),

      .wbm0_rty_i                       (wbm_b_d_rty_i),

      // Byte bus slaves

      .wbs0_adr_i                       (wbs_d_uart0_adr_i),

      .wbs0_dat_i                       (wbs_d_uart0_dat_i),

      .wbs0_we_i                        (wbs_d_uart0_we_i),

      .wbs0_cyc_i                       (wbs_d_uart0_cyc_i),

      .wbs0_stb_i                       (wbs_d_uart0_stb_i),

      .wbs0_cti_i                       (wbs_d_uart0_cti_i),

      .wbs0_bte_i                       (wbs_d_uart0_bte_i),

      .wbs0_dat_o                       (wbs_d_uart0_dat_o),

      .wbs0_ack_o                       (wbs_d_uart0_ack_o),

      .wbs0_err_o                       (wbs_d_uart0_err_o),

      .wbs0_rty_o                       (wbs_d_uart0_rty_o),

      .wbs1_adr_i                       (wbs_d_gpio0_adr_i),

      .wbs1_dat_i                       (wbs_d_gpio0_dat_i),

      .wbs1_we_i                        (wbs_d_gpio0_we_i),

      .wbs1_cyc_i                       (wbs_d_gpio0_cyc_i),

      .wbs1_stb_i                       (wbs_d_gpio0_stb_i),

      .wbs1_cti_i                       (wbs_d_gpio0_cti_i),

      .wbs1_bte_i                       (wbs_d_gpio0_bte_i),

      .wbs1_dat_o                       (wbs_d_gpio0_dat_o),

      .wbs1_ack_o                       (wbs_d_gpio0_ack_o),

      .wbs1_err_o                       (wbs_d_gpio0_err_o),

      .wbs1_rty_o                       (wbs_d_gpio0_rty_o),

      .wbs2_adr_i                       (wbs_d_i2c0_adr_i),

      .wbs2_dat_i                       (wbs_d_i2c0_dat_i),

      .wbs2_we_i                        (wbs_d_i2c0_we_i),

      .wbs2_cyc_i                       (wbs_d_i2c0_cyc_i),

      .wbs2_stb_i                       (wbs_d_i2c0_stb_i),

      .wbs2_cti_i                       (wbs_d_i2c0_cti_i),

      .wbs2_bte_i                       (wbs_d_i2c0_bte_i),

      .wbs2_dat_o                       (wbs_d_i2c0_dat_o),

      .wbs2_ack_o                       (wbs_d_i2c0_ack_o),

      .wbs2_err_o                       (wbs_d_i2c0_err_o),

      .wbs2_rty_o                       (wbs_d_i2c0_rty_o),

      .wbs3_adr_i                       (wbs_d_i2c1_adr_i),

      .wbs3_dat_i                       (wbs_d_i2c1_dat_i),

      .wbs3_we_i                        (wbs_d_i2c1_we_i),

      .wbs3_cyc_i                       (wbs_d_i2c1_cyc_i),

      .wbs3_stb_i                       (wbs_d_i2c1_stb_i),

      .wbs3_cti_i                       (wbs_d_i2c1_cti_i),

      .wbs3_bte_i                       (wbs_d_i2c1_bte_i),

      .wbs3_dat_o                       (wbs_d_i2c1_dat_o),

      .wbs3_ack_o                       (wbs_d_i2c1_ack_o),

      .wbs3_err_o                       (wbs_d_i2c1_err_o),

      .wbs3_rty_o                       (wbs_d_i2c1_rty_o),

      .wbs4_adr_i                       (wbs_d_spi0_adr_i),

      .wbs4_dat_i                       (wbs_d_spi0_dat_i),

      .wbs4_we_i                        (wbs_d_spi0_we_i),

      .wbs4_cyc_i                       (wbs_d_spi0_cyc_i),

      .wbs4_stb_i                       (wbs_d_spi0_stb_i),

      .wbs4_cti_i                       (wbs_d_spi0_cti_i),

      .wbs4_bte_i                       (wbs_d_spi0_bte_i),

      .wbs4_dat_o                       (wbs_d_spi0_dat_o),

      .wbs4_ack_o                       (wbs_d_spi0_ack_o),

      .wbs4_err_o                       (wbs_d_spi0_err_o),

      .wbs4_rty_o                       (wbs_d_spi0_rty_o),

      // Clock, reset inputs

      .wb_clk                   (wb_clk),

      .wb_rst                   (wb_rst));

   defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;

   defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves;

   defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr;

   defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr;

   defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr;

   defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr;

   defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr;

`ifdef JTAG_DEBUG

   ////////////////////////////////////////////////////////////////////////

   //

   // JTAG TAP

   // 

   ////////////////////////////////////////////////////////////////////////

   //

   // Wires

   //

   wire                                   dbg_if_select;

   wire                                   dbg_if_tdo;

   wire                                   jtag_tap_tdo;

   wire                                   jtag_tap_shift_dr, jtag_tap_pause_dr,

                                          jtag_tap_upate_dr, jtag_tap_capture_dr;