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Xilinx DDR2 controller with Wishbone interface
 
This is a Xilinx technology-dependent DDR2 memory controller, based on a
controller from Xilinx's memory interface generator (MIG), with a small cache
memory and Wishbone wrapper.
 
The xilinx_ddr2_wb_if.v is a 3-master arbiter for the controller.
The xilinx_ddr2_if.v is the actual interface between the Wishbone bus and
Xilinx MIG control interface.
 
When synthesizing, take note of the xilinx_ddr2_if_cache module, that is a
dual-port memory, with different aspects on each size, and cannot be inferred.
The NGC should be in the appropriate place in the synthesis or backend
directories.
 
 

Line No.	Rev	Author	Line
1	627	stekern	`Xilinx DDR2 controller with Wishbone interface`
2
3			`This is a Xilinx technology-dependent DDR2 memory controller, based on a`
4			`controller from Xilinx's memory interface generator (MIG), with a small cache`
5			`memory and Wishbone wrapper.`
6
7			`The xilinx_ddr2_wb_if.v is a 3-master arbiter for the controller.`
8			`The xilinx_ddr2_if.v is the actual interface between the Wishbone bus and`
9			`Xilinx MIG control interface.`
10
11			`When synthesizing, take note of the xilinx_ddr2_if_cache module, that is a`
12			`dual-port memory, with different aspects on each size, and cannot be inferred.`
13			`The NGC should be in the appropriate place in the synthesis or backend`
14			`directories.`
15
16

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [xilinx_ddr2/] [README] - Blame information for rev 627