OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [par/] [bin/] [Makefile] - Blame information for rev 415

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 415 julius
######################################################################
2
####                                                              ####
3
####  ORPSoC Xilinx backend Makefile                              ####
4
####                                                              ####
5
####  Author(s):                                                  ####
6
####      - Julius Baxter, julius@opencores.org                   ####
7
####                                                              ####
8
####                                                              ####
9
######################################################################
10
####                                                              ####
11
#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG            ####
12
####                                                              ####
13
#### This source file may be used and distributed without         ####
14
#### restriction provided that this copyright statement is not    ####
15
#### removed from the file and that any derivative work contains  ####
16
#### the original copyright notice and the associated disclaimer. ####
17
####                                                              ####
18
#### This source file is free software; you can redistribute it   ####
19
#### and/or modify it under the terms of the GNU Lesser General   ####
20
#### Public License as published by the Free Software Foundation; ####
21
#### either version 2.1 of the License, or (at your option) any   ####
22
#### later version.                                               ####
23
####                                                              ####
24
#### This source is distributed in the hope that it will be       ####
25
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
26
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
27
#### PURPOSE.  See the GNU Lesser General Public License for more ####
28
#### details.                                                     ####
29
####                                                              ####
30
#### You should have received a copy of the GNU Lesser General    ####
31
#### Public License along with this source; if not, download it   ####
32
#### from http://www.opencores.org/lgpl.shtml                     ####
33
####                                                              ####
34
######################################################################
35 67 julius
 
36 415 julius
# Name of the directory we're currently in
37
CUR_DIR=$(shell pwd)
38 67 julius
 
39 415 julius
# The root path of the board build
40
BOARD_DIR ?=$(CUR_DIR)/../../..
41
PROJECT_ROOT=$(BOARD_DIR)/../../..
42 67 julius
 
43 415 julius
SYN_DIR=$(BOARD_DIR)/syn/xst
44
SYN_RUN_DIR=$(SYN_DIR)/run
45
 
46
BOARD_BACKEND_DIR=$(BOARD_DIR)/backend/bin
47
 
48
DESIGN_NAME=orpsoc
49
BOARD_NAME=ml501
50
 
51
# Set V=1 when calling make to enable verbose output
52
# mainly for debugging purposes.
53
ifeq ($(V), 1)
54
Q=
55
else
56
Q ?=@
57
endif
58
 
59
BOARD_RTL_DIR=$(BOARD_DIR)/rtl
60
BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
61
# Only 1 include path for board builds - their own!
62
BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
63
BOARD_DESIGN_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
64
 
65
DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(BOARD_DESIGN_VERILOG_DEFINES) | cut -d ':' -f 1)
66
DESIGN_DEFINES=$(shell cat $(BOARD_DESIGN_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
67
 
68
# Rule to look at what defines are being extracted from main file
69
print-defines:
70
        @echo; echo "\t### Design defines ###"; echo
71
        @echo "\tParsing "$(BOARD_DESIGN_VERILOG_DEFINES)" and exporting:"
72
        @echo $(DESIGN_DEFINES)
73
 
74
 
75
# Backend tool path
76
# Check that the XILINX_PATH variable is set
77
ifeq ($(XILINX_PATH),)
78
$(error XILINX_PATH environment variable not set. Set it and rerun)
79
endif
80
XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
81
XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
82
ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
83
$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
84
endif
85
 
86
 
87
#
88
# Options for Xilinx PAR tools
89
#
90
FPGA_PART=xc5vlx50-ff676-1
91 67 julius
XILINX_FLAGS=-intstyle silent
92
XILINX_MAP_FLAGS=-logic_opt off
93 415 julius
XILINX_AREA_TARGET = speed
94
TIMING_REPORT_OPTIONS = -u 1000 -e 1000
95
SPI_FLASH_SIZE_KBYTES ?=2048
96
SPI_BOOTLOADER_SW_OFFSET_HEX ?=1c0000
97 67 julius
 
98 415 julius
print-config:
99
        $(Q)echo; echo "\t### Backend make configuration ###"; echo
100
        $(Q)echo "\tFPGA_PART="$(FPGA_PART)
101
        $(Q)echo "\tXILINX_FLAGS="$(XILINX_FLAGS)
102
        $(Q)echo "\tXILINX_MAP_FLAGS="$(XILINX_MAP_FLAGS)
103
        $(Q)echo "\tXILINX_AREA_TARGET="$(XILINX_AREA_TARGET)
104
        $(Q)echo "\tTIMING_REPORT_OPTIONS="$(TIMING_REPORT_OPTIONS)
105
        $(Q)echo "\tSPI_FLASH_SIZE_KBYTES="$(SPI_FLASH_SIZE_KBYTES)
106
        $(Q)echo "\tSPI_BOOTLOADER_SW_OFFSET_HEX="$(SPI_BOOTLOADER_SW_OFFSET_HEX)
107
 
108
 
109
 
110
NGC_FILE=$(SYN_RUN_DIR)/$(DESIGN_NAME).ngc
111
NGD_FILE=$(DESIGN_NAME).ngd
112
UCF_FILE=../bin/$(BOARD_NAME).ucf
113
MAPPED_NCD=$(DESIGN_NAME)_mapped.ncd
114
PARRED_NCD=$(DESIGN_NAME).ncd
115
PCF_FILE=$(DESIGN_NAME).pcf
116
BIT_FILE=$(DESIGN_NAME).bit
117
BIT_FILE_FOR_SPI=$(DESIGN_NAME)_spiboot.bit
118
BATCH_FILE=$(DESIGN_NAME).batch
119
MCS_FILE=$(DESIGN_NAME).mcs
120
 
121
$(NGC_FILE):
122
        $(Q)$(MAKE) -C $(SYN_RUN_DIR) $(DESIGN_NAME).ngc
123
 
124
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
125 67 julius
        @echo; echo "\t#### Running NGDBuild ####";
126
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
127 415 julius
        ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_DIR) -uc $(UCF_FILE) \
128
        $(NGC_FILE) $@ )
129 67 julius
 
130
#This target uses Xilinx tools to perform Mapping
131 415 julius
$(MAPPED_NCD): $(NGD_FILE)
132 67 julius
        @echo; echo "\t#### Mapping ####";
133
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
134
        export XIL_MAP_NO_DSP_AUTOREG=1 && \
135
        export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
136 415 julius
        map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
137
        -timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE))
138 67 julius
 
139
#This target uses Xilinx tools to Place & Route the design
140 415 julius
$(PARRED_NCD): $(MAPPED_NCD)
141 67 julius
        @echo; echo "\t#### PAR'ing ####";
142
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
143 415 julius
        par -w -pl high -rl high $(XILINX_FLAGS) $< $@ $(PCD_FILE) )
144 67 julius
 
145 415 julius
#This target uses Xilinx tools to generate a bitstream for download
146
$(BIT_FILE): $(PARRED_NCD)
147 67 julius
        @echo; echo "\t#### Generating .bit file ####";
148
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
149 415 julius
        bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ )
150 67 julius
 
151 415 julius
$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
152
        @echo; echo "\t#### Generating .bit file for SPI load ####";
153
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
154
        bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ )
155
ifeq ($(BOOTLOADER_BIN),)
156
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
157
        @echo; echo "\t#### Generating .mcs file for SPI load ####";
158
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
159
        promgen -spi -p mcs -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< )
160
else
161
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
162
        @echo; echo "\t#### Generating .mcs file for SPI load ####";
163
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
164
        promgen -spi -p mcs -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
165
        -data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \
166
         )
167
endif
168
 
169 67 julius
#this target downloads the bitstream to the target fpga
170 415 julius
download: $(BIT_FILE) $(BATCH_FILE)
171 67 julius
        $(Q)( . ${XILINX_PATH}/settings32.sh && \
172 415 julius
        impact -batch $(BATCH_FILE) )
173 67 julius
 
174
#This target uses netgen to make a simulation netlist
175 415 julius
netlist: $(PARRED_NCD)
176 67 julius
        @echo; echo "\t#### Generating netlist ####";
177
        $(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
178 415 julius
        netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<)
179 67 julius
 
180
#This one uses TRCE to make a timing report
181 415 julius
timingreport: $(PARRED_NCD)
182 67 julius
        @echo; echo "\t#### Generating timing report ####";
183
        $(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
184 415 julius
        trce $(TIMING_REPORT_OPTIONS) $< )
185 67 julius
 
186
 
187
clean:
188 415 julius
        $(Q)rm -rf *.*
189 67 julius
 
190 415 julius
clean-syn:
191
        $(Q)$(MAKE) -C $(SYN_RUN_DIR) clean-all
192
 
193
clean-all: clean-syn clean
194
 
195
.PRECIOUS : $(PARRED_NCD) $(MAPPED_NCD) $(NGC_FILE) $(NGD_FILE) $(BIT_FILE) $(BIT_FILE_FOR_SPI)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.