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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [ddr2_model.v] - Blame information for rev 360

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1 67 julius
/****************************************************************************************
2
*
3
*    File Name:  ddr2.v
4
*      Version:  5.80
5
*        Model:  BUS Functional
6
*
7
* Dependencies:  ddr2_parameters.vh
8
*
9
*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)
10
*
11
*   Limitation:  - doesn't check for average refresh timings
12
*                - positive ck and ck_n edges are used to form internal clock
13
*                - positive dqs and dqs_n edges are used to latch data
14
*                - test mode is not modeled
15
*
16
*         Note:  - Set simulator resolution to "ps" accuracy
17
*                - Set Debug = 0 to disable $display messages
18
*
19
*   Disclaimer   This software code and all associated documentation, comments or other
20
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
21
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
22
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
23
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
24
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
25
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
26
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
27
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
28
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
29
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
30
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
31
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
32
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
33
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
34
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
35
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
36
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
37
*                limitation of liability for consequential or incidental damages, the
38
*                above limitation may not apply to you.
39
*
40
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
41
*
42
* Rev   Author   Date        Changes
43
* ---------------------------------------------------------------------------------------
44
* 1.00  JMK      07/29/03    Initial Release
45
* 1.10  JMK      08/09/03    Timing Parameter updates to tIS, tIH, tDS, tDH
46
* 2.20  JMK      08/07/03    General cleanup
47
* 2.30  JMK      11/26/03    Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
48
*                            Added AL_MIN and AL_MAX parameters.
49
*                            Removed support for OCD.
50
* 2.40  JMK      01/15/04    Removed verilog 2001 constructs.
51
* 2.50  JMK      01/29/04    Removed tRP checks during Precharge command.
52
* 2.60  JMK      04/20/04    Fixed tWTR check.
53
* 2.70  JMK      04/30/04    Added tRFC maximum check.
54
*                            Combined Self Refresh and Power Down always blocks.
55
*                            Added Reset Function (CKE LOW Anytime).
56
* 2.80  JMK      08/19/04    Precharge is treated as NOP when bank is not active.
57
*                            Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
58
*                            tRFC maximum violation will only display one time.
59
* 2.90  JMK      11/05/04    Fixed DQS checking during write.
60
*                            Fixed false tRFC max assertion during power up and self ref.
61
*                            Added warning for 200us CKE low time during initialization.
62
*                            Added -3, -3E, and -37V speed grades to ddr2_parameters.v
63
* 3.00  JMK      04/22/05    Removed ODT off requirement during power down.
64
*                            Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
65
*                            Added ODT status messages.
66
*                            Updated the initialization sequence.
67
*                            Disable ODT and CLK pins during self refresh.
68
*                            Disable cmd and addr pins during power down and self refresh.
69
* 3.10  JMK      06/07/05    Disable trpa checking if the part does not have 8 banks.
70
*                            Changed tAXPD message from error to a warning.
71
*                            Added tDSS checking.
72
*                            Removed tDQSL checking during tWPRE and tWPST.
73
*                            Fixed a burst order error during writes.
74
*                            Renamed parameters file with .vh extension.
75
* 3.20  JMK      07/18/05    Removed 14 tCK requirement from LMR to READ.
76
* 3.30  JMK      08/03/05    Added check for interrupting a burst with auto precharge.
77
* 4.00  JMK      11/21/05    Parameter names all UPPERCASE, signal names all lowercase.
78
*                            Clock jitter can be tolerated within specification range.
79
*                            Clock frequency is sampled from the CK pin.
80
*                            Scaleable up to 64 DQ and 16 DQS bits.
81
*                            Read data can be randomly skewed using RANDOM_OUT_DELAY.
82
*                            Parameterized read and write DQS, and read DQ.
83
*                            Initialization can be bypassed using initialize task.
84
* 4.10  JMK      11/30/05    Fixed compile errors when `MAX_MEM was defined.
85
* 4.20  JMK      12/09/05    Fixed memory addressing error when `MAX_MEM was defined.
86
* 4.30  JMK      02/15/06    Added dummy write to initialization sequence.
87
*                            Removed tWPST maximum checking.
88
*                            Rising dqs_n edge latches data when enabled in EMR.
89
*                            Fixed a sign error in the tJIT(cc) calculation.
90
* 4.40  JMK      02/16/06    Fixed dummy write when`MAX_MEM was defined.
91
* 4.50  JMK      02/27/06    Fixed extra tDQSS assertions.
92
*                            Fixed tRCD and tWTR checking.
93
*                            Errors entering Power Down or Self Refresh will cause reset.
94
*                            Ignore dqs_n when disabled in EMR.
95
* 5.00  JMK      04/24/06    Test stimulus now included from external file (subtest.vh)
96
*                            Fixed tRFC max assertion during self refresh.
97
*                            Fixed tANPD checking during Power Down.
98
*                            Removed dummy write from initialization sequence.
99
* 5.01  JMK      04/28/06    Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
100
*                            Removed Auto Precharge error message during Power Down Enter.
101
* 5.10  JMK      07/26/06    Created internal clock using ck and ck_n.
102
*                            RDQS can only be enabled in EMR for x8 configurations.
103
*                            CAS latency is checked vs frequency when DLL locks.
104
*                            tMOD changed from tCK units to ns units.
105
*                            Added 50 Ohm setting for Rtt in EMR.
106
*                            Improved checking of DQS during writes.
107
* 5.20  JMK      10/02/06    Fixed DQS checking for interrupting write to write and x16.
108
* 5.30  JMK      05/25/07    Fixed checking for 0-Z transition on write postamble.
109
* 5.50  JMK      05/30/08    Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
110
*                            Added a register delay to ddr2_module.v when RDIMM is defined.
111
*                            Added multi-chip package model support in ddr2_mcp.v
112
*                            Added High Temp Self Refresh rate setting in EMRS2[7]
113
* 5.70  JMK      04/23/09    Updated tRPA definition
114
*                            Increased internal width to 72 bit DQ bus
115
* 5.80  SPH      08/12/09    Fixed tRAS maximum violation (only check if bank still open)
116
****************************************************************************************/
117
 
118
// DO NOT CHANGE THE TIMESCALE
119
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
120
`timescale 1ps / 1ps
121
 
122
module ddr2_model (
123
    ck,
124
    ck_n,
125
    cke,
126
    cs_n,
127
    ras_n,
128
    cas_n,
129
    we_n,
130
    dm_rdqs,
131
    ba,
132
    addr,
133
    dq,
134
    dqs,
135
    dqs_n,
136
    rdqs_n,
137
    odt
138
);
139
 
140
`include "ddr2_model_parameters.vh"
141
 
142
    // text macros
143
    `define DQ_PER_DQS DQ_BITS/DQS_BITS
144
    `define BANKS      (1<<BA_BITS)
145
    `define MAX_BITS   (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
146
    `define MAX_SIZE   (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
147
    `define MEM_SIZE   (1<<MEM_BITS)
148
    `define MAX_PIPE   2*(AL_MAX + CL_MAX)
149
 
150
    // Declare Ports
151
    input   ck;
152
    input   ck_n;
153
    input   cke;
154
    input   cs_n;
155
    input   ras_n;
156
    input   cas_n;
157
    input   we_n;
158
    inout   [DM_BITS-1:0]   dm_rdqs;
159
    input   [BA_BITS-1:0]   ba;
160
    input   [ADDR_BITS-1:0] addr;
161
    inout   [DQ_BITS-1:0]   dq;
162
    inout   [DQS_BITS-1:0]  dqs;
163
    inout   [DQS_BITS-1:0]  dqs_n;
164
    output  [DQS_BITS-1:0]  rdqs_n;
165
    input   odt;
166
 
167
    // clock jitter
168
    real    tck_avg;
169
    time    tck_sample [TDLLK-1:0];
170
    time    tch_sample [TDLLK-1:0];
171
    time    tcl_sample [TDLLK-1:0];
172
    time    tck_i;
173
    time    tch_i;
174
    time    tcl_i;
175
    real    tch_avg;
176
    real    tcl_avg;
177
    time    tm_ck_pos;
178
    time    tm_ck_neg;
179
    real    tjit_per_rtime;
180
    integer tjit_cc_time;
181
    real    terr_nper_rtime;
182
 
183
    // clock skew
184
    real    out_delay;
185
    integer dqsck [DQS_BITS-1:0];
186
    integer dqsck_min;
187
    integer dqsck_max;
188
    integer dqsq_min;
189
    integer dqsq_max;
190
    integer seed;
191
 
192
    // Mode Registers
193
    reg     burst_order;
194
    reg     [BL_BITS:0] burst_length;
195
    integer cas_latency;
196
    integer additive_latency;
197
    reg     dll_reset;
198
    reg     dll_locked;
199
    reg     dll_en;
200
    integer write_recovery;
201
    reg     low_power;
202
    reg     [1:0] odt_rtt;
203
    reg     odt_en;
204
    reg     [2:0] ocd;
205
    reg     dqs_n_en;
206
    reg     rdqs_en;
207
    reg     out_en;
208
    integer read_latency;
209
    integer write_latency;
210
 
211
    // cmd encoding
212
   parameter LOAD_MODE = 4'b0000;
213
   parameter REFRESH   = 4'b0001;
214
   parameter PRECHARGE = 4'b0010;
215
   parameter ACTIVATE  = 4'b0011;
216
   parameter WRITE     = 4'b0100;
217
   parameter READ      = 4'b0101;
218
   parameter NOP       = 4'b0111;
219
   parameter PWR_DOWN  = 4'b1000;
220
   parameter SELF_REF  = 4'b100;
221
 
222
 
223
    reg [8*9-1:0] cmd_string [9:0];
224
    initial begin
225
        cmd_string[LOAD_MODE] = "Load Mode";
226
        cmd_string[REFRESH  ] = "Refresh  ";
227
        cmd_string[PRECHARGE] = "Precharge";
228
        cmd_string[ACTIVATE ] = "Activate ";
229
        cmd_string[WRITE    ] = "Write    ";
230
        cmd_string[READ     ] = "Read     ";
231
        cmd_string[NOP      ] = "No Op    ";
232
        cmd_string[PWR_DOWN ] = "Pwr Down ";
233
        cmd_string[SELF_REF ] = "Self Ref ";
234
    end
235
 
236
    // command state
237
    reg     [`BANKS-1:0] active_bank;
238
    reg     [`BANKS-1:0] auto_precharge_bank;
239
    reg     [`BANKS-1:0] write_precharge_bank;
240
    reg     [`BANKS-1:0] read_precharge_bank;
241
    reg     [ROW_BITS-1:0] active_row [`BANKS-1:0];
242
    reg     in_power_down;
243
    reg     in_self_refresh;
244
    reg     [3:0] init_mode_reg;
245
    reg     init_done;
246
    integer init_step;
247
    reg     er_trfc_max;
248
    reg     odt_state;
249
    reg     prev_odt;
250
 
251
    // cmd timers/counters
252
    integer ref_cntr;
253
    integer ck_cntr;
254
    integer ck_load_mode;
255
    integer ck_write;
256
    integer ck_read;
257
    integer ck_write_ap;
258
    integer ck_power_down;
259
    integer ck_slow_exit_pd;
260
    integer ck_self_refresh;
261
    integer ck_cke;
262
    integer ck_odt;
263
    integer ck_dll_reset;
264
    integer ck_bank_write     [`BANKS-1:0];
265
    integer ck_bank_read      [`BANKS-1:0];
266
    time    tm_refresh;
267
    time    tm_precharge;
268
    time    tm_precharge_all;
269
    time    tm_activate;
270
    time    tm_write_end;
271
    time    tm_self_refresh;
272
    time    tm_odt_en;
273
    time    tm_bank_precharge [`BANKS-1:0];
274
    time    tm_bank_activate  [`BANKS-1:0];
275
    time    tm_bank_write_end [`BANKS-1:0];
276
    time    tm_bank_read_end  [`BANKS-1:0];
277
 
278
    // pipelines
279
    reg     [`MAX_PIPE:0]   al_pipeline;
280
    reg     [`MAX_PIPE:0]   wr_pipeline;
281
    reg     [`MAX_PIPE:0]   rd_pipeline;
282
    reg     [`MAX_PIPE:0]   odt_pipeline;
283
    reg     [BA_BITS-1:0]   ba_pipeline  [`MAX_PIPE:0];
284
    reg     [ROW_BITS-1:0]  row_pipeline [`MAX_PIPE:0];
285
    reg     [COL_BITS-1:0]  col_pipeline [`MAX_PIPE:0];
286
    reg     prev_cke;
287
 
288
    // data state
289
    reg     [BL_MAX*DQ_BITS-1:0] memory_data;
290
    reg     [BL_MAX*DQ_BITS-1:0] bit_mask;
291
    reg     [BL_BITS-1:0]        burst_position;
292
    reg     [BL_BITS:0]          burst_cntr;
293
    reg     [DQ_BITS-1:0]        dq_temp;
294
    reg     [35:0] check_write_postamble;
295
    reg     [35:0] check_write_preamble;
296
    reg     [35:0] check_write_dqs_high;
297
    reg     [35:0] check_write_dqs_low;
298
    reg     [17:0] check_dm_tdipw;
299
    reg     [71:0] check_dq_tdipw;
300
 
301
    // data timers/counters
302
    time    tm_cke;
303
    time    tm_odt;
304
    time    tm_tdqss;
305
    time    tm_dm        [17:0];
306
    time    tm_dqs       [17:0];
307
    time    tm_dqs_pos   [35:0];
308
    time    tm_dqss_pos  [35:0];
309
    time    tm_dqs_neg   [35:0];
310
    time    tm_dq        [71:0];
311
    time    tm_cmd_addr  [22:0];
312
    reg [8*7-1:0] cmd_addr_string [22:0];
313
    initial begin
314
        cmd_addr_string[ 0] = "CS_N   ";
315
        cmd_addr_string[ 1] = "RAS_N  ";
316
        cmd_addr_string[ 2] = "CAS_N  ";
317
        cmd_addr_string[ 3] = "WE_N   ";
318
        cmd_addr_string[ 4] = "BA 0   ";
319
        cmd_addr_string[ 5] = "BA 1   ";
320
        cmd_addr_string[ 6] = "BA 2   ";
321
        cmd_addr_string[ 7] = "ADDR  0";
322
        cmd_addr_string[ 8] = "ADDR  1";
323
        cmd_addr_string[ 9] = "ADDR  2";
324
        cmd_addr_string[10] = "ADDR  3";
325
        cmd_addr_string[11] = "ADDR  4";
326
        cmd_addr_string[12] = "ADDR  5";
327
        cmd_addr_string[13] = "ADDR  6";
328
        cmd_addr_string[14] = "ADDR  7";
329
        cmd_addr_string[15] = "ADDR  8";
330
        cmd_addr_string[16] = "ADDR  9";
331
        cmd_addr_string[17] = "ADDR 10";
332
        cmd_addr_string[18] = "ADDR 11";
333
        cmd_addr_string[19] = "ADDR 12";
334
        cmd_addr_string[20] = "ADDR 13";
335
        cmd_addr_string[21] = "ADDR 14";
336
        cmd_addr_string[22] = "ADDR 15";
337
    end
338
 
339
    reg [8*5-1:0] dqs_string [1:0];
340
    initial begin
341
        dqs_string[0] = "DQS  ";
342
        dqs_string[1] = "DQS_N";
343
    end
344
 
345
    // Memory Storage
346
`ifdef MAX_MEM
347
    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MAX_SIZE-1];
348
`else
349
    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MEM_SIZE-1];
350
    reg     [`MAX_BITS-1:0]      address [0:`MEM_SIZE-1];
351
    reg     [MEM_BITS:0]         memory_index;
352
    reg     [MEM_BITS:0]         memory_used;
353
`endif
354
 
355
    // receive
356
    reg            ck_in;
357
    reg            ck_n_in;
358
    reg            cke_in;
359
    reg            cs_n_in;
360
    reg            ras_n_in;
361
    reg            cas_n_in;
362
    reg            we_n_in;
363
    reg     [17:0] dm_in;
364
    reg     [2:0]  ba_in;
365
    reg     [15:0] addr_in;
366
    reg     [71:0] dq_in;
367
    reg     [35:0] dqs_in;
368
    reg            odt_in;
369
 
370
    reg     [17:0] dm_in_pos;
371
    reg     [17:0] dm_in_neg;
372
    reg     [71:0] dq_in_pos;
373
    reg     [71:0] dq_in_neg;
374
    reg            dq_in_valid;
375
    reg            dqs_in_valid;
376
    integer        wdqs_cntr;
377
    integer        wdq_cntr;
378
    integer        wdqs_pos_cntr [35:0];
379
    reg            b2b_write;
380
    reg     [35:0] prev_dqs_in;
381
    reg            diff_ck;
382
 
383
    always @(ck     ) ck_in     <= #BUS_DELAY ck;
384
    always @(ck_n   ) ck_n_in   <= #BUS_DELAY ck_n;
385
    always @(cke    ) cke_in    <= #BUS_DELAY cke;
386
    always @(cs_n   ) cs_n_in   <= #BUS_DELAY cs_n;
387
    always @(ras_n  ) ras_n_in  <= #BUS_DELAY ras_n;
388
    always @(cas_n  ) cas_n_in  <= #BUS_DELAY cas_n;
389
    always @(we_n   ) we_n_in   <= #BUS_DELAY we_n;
390
    always @(dm_rdqs) dm_in     <= #BUS_DELAY dm_rdqs;
391
    always @(ba     ) ba_in     <= #BUS_DELAY ba;
392
    always @(addr   ) addr_in   <= #BUS_DELAY addr;
393
    always @(dq     ) dq_in     <= #BUS_DELAY dq;
394
    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
395
    always @(odt    ) odt_in    <= #BUS_DELAY odt;
396
    // create internal clock
397
    always @(posedge ck_in)   diff_ck <= ck_in;
398
    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
399
 
400
    wire    [17:0] dqs_even = dqs_in[17:0];
401
    wire    [17:0] dqs_odd  = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
402
    wire    [3:0]  cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP;  //deselect = nop 
403
 
404
    // transmit
405
    reg                    dqs_out_en;
406
    reg     [DQS_BITS-1:0] dqs_out_en_dly;
407
    reg                    dqs_out;
408
    reg     [DQS_BITS-1:0] dqs_out_dly;
409
    reg                    dq_out_en;
410
    reg     [DQ_BITS-1:0]  dq_out_en_dly;
411
    reg     [DQ_BITS-1:0]  dq_out;
412
    reg     [DQ_BITS-1:0]  dq_out_dly;
413
    integer                rdqsen_cntr;
414
    integer                rdqs_cntr;
415
    integer                rdqen_cntr;
416
    integer                rdq_cntr;
417
 
418
    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});
419
    bufif1 buf_dm     [DM_BITS-1:0]  (dm_rdqs, dqs_out_dly,  dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
420
    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
421
    bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n,  ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
422
    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});
423
 
424
    initial begin
425
        if (BL_MAX < 2)
426
            $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);
427
        if ((1<<BO_BITS) > BL_MAX)
428
            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
429
        $timeformat (-12, 1, " ps", 1);
430
        reset_task;
431
        seed = RANDOM_SEED;
432
        ck_cntr = 0;
433
    end
434
 
435
    // calculate the absolute value of a real number
436
    function real abs_value;
437
    input arg;
438
    real arg;
439
    begin
440
        if (arg < 0.0)
441
            abs_value = -1.0 * arg;
442
        else
443
            abs_value = arg;
444
    end
445
    endfunction
446
 
447
`ifdef MAX_MEM
448
`else
449
    function get_index;
450
        input [`MAX_BITS-1:0] addr;
451
        begin : index
452
            get_index = 0;
453
            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
454
                if (address[memory_index] == addr) begin
455
                    get_index = 1;
456
                    disable index;
457
                end
458
            end
459
        end
460
    endfunction
461
`endif
462
 
463
    task memory_write;
464
        input  [BA_BITS-1:0]  bank;
465
        input  [ROW_BITS-1:0] row;
466
        input  [COL_BITS-1:0] col;
467
        input  [BL_MAX*DQ_BITS-1:0] data;
468
        reg    [`MAX_BITS-1:0] addr;
469
        begin
470
            // chop off the lowest address bits
471
            addr = {bank, row, col}/BL_MAX;
472
`ifdef MAX_MEM
473
            memory[addr] = data;
474
`else
475
            if (get_index(addr)) begin
476
                address[memory_index] = addr;
477
                memory[memory_index] = data;
478
            end else if (memory_used == `MEM_SIZE) begin
479
                $display ("%m: at time %t ERROR: Memory overflow.  Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
480
                if (STOP_ON_ERROR) $stop(0);
481
            end else begin
482
                address[memory_used] = addr;
483
                memory[memory_used] = data;
484
                memory_used = memory_used + 1;
485
            end
486
`endif
487
        end
488
    endtask
489
 
490
    task memory_read;
491
        input  [BA_BITS-1:0]  bank;
492
        input  [ROW_BITS-1:0] row;
493
        input  [COL_BITS-1:0] col;
494
        output [BL_MAX*DQ_BITS-1:0] data;
495
        reg    [`MAX_BITS-1:0] addr;
496
        begin
497
            // chop off the lowest address bits
498
            addr = {bank, row, col}/BL_MAX;
499
`ifdef MAX_MEM
500
            data = memory[addr];
501
`else
502
            if (get_index(addr)) begin
503
                data = memory[memory_index];
504
            end else begin
505
                data = {BL_MAX*DQ_BITS{1'bx}};
506
            end
507
`endif
508
        end
509
    endtask
510
 
511
    // Before this task runs, the model must be in a valid state for precharge power down.
512
    // After this task runs, NOP commands must be issued until tRFC has been met
513
    task initialize;
514
        input [ADDR_BITS-1:0] mode_reg0;
515
        input [ADDR_BITS-1:0] mode_reg1;
516
        input [ADDR_BITS-1:0] mode_reg2;
517
        input [ADDR_BITS-1:0] mode_reg3;
518
        begin
519
            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
520
            cmd_task(1,       NOP, 'bx, 'bx);
521
            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
522
            cmd_task(1, LOAD_MODE, 3, mode_reg3);
523
            cmd_task(1, LOAD_MODE, 2, mode_reg2);
524
            cmd_task(1, LOAD_MODE, 1, mode_reg1);
525
            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
526
            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
527
            cmd_task(1,   REFRESH, 'bx, 'bx);
528
            cmd_task(1,   REFRESH, 'bx, 'bx);
529
            cmd_task(1, LOAD_MODE, 0, mode_reg0);
530
            cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
531
            cmd_task(1, LOAD_MODE, 1, mode_reg1);
532
            cmd_task(0,       NOP, 'bx, 'bx);
533
        end
534
    endtask
535
 
536
    task reset_task;
537
        integer i;
538
        begin
539
            // disable inputs
540
            dq_in_valid          = 0;
541
            dqs_in_valid        <= 0;
542
            wdqs_cntr            = 0;
543
            wdq_cntr             = 0;
544
            for (i=0; i<36; i=i+1) begin
545
                wdqs_pos_cntr[i]    <= 0;
546
            end
547
            b2b_write           <= 0;
548
            // disable outputs
549
            out_en               = 0;
550
            dqs_n_en             = 0;
551
            rdqs_en              = 0;
552
            dq_out_en            = 0;
553
            rdq_cntr             = 0;
554
            dqs_out_en           = 0;
555
            rdqs_cntr            = 0;
556
            // disable ODT
557
            odt_en               = 0;
558
            odt_state            = 0;
559
            // reset bank state
560
            active_bank          = {`BANKS{1'b1}};
561
            auto_precharge_bank  = 0;
562
                read_precharge_bank  = 0;
563
                write_precharge_bank = 0;
564
            // require initialization sequence
565
            init_done            = 0;
566
            init_step            = 0;
567
            init_mode_reg        = 0;
568
            // reset DLL
569
            dll_en               = 0;
570
            dll_reset            = 0;
571
            dll_locked           = 0;
572
            ocd                  = 0;
573
            // exit power down and self refresh
574
            in_power_down        = 0;
575
            in_self_refresh      = 0;
576
            // clear pipelines
577
            al_pipeline          = 0;
578
            wr_pipeline          = 0;
579
            rd_pipeline          = 0;
580
            odt_pipeline         = 0;
581
            // clear memory
582
`ifdef MAX_MEM
583
            for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
584
                memory[i] <= 'bx;
585
            end
586
`else
587
            memory_used <= 0; //erase memory
588
`endif
589
            // clear maximum timing checks
590
            tm_refresh <= 'bx;
591
            for (i=0; i<`BANKS; i=i+1) begin
592
                tm_bank_activate[i] <= 'bx;
593
            end
594
        end
595
    endtask
596
 
597
    task chk_err;
598
        input samebank;
599
        input [BA_BITS-1:0] bank;
600
        input [3:0] fromcmd;
601
        input [3:0] cmd;
602
        reg err;
603
    begin
604
        // all matching case expressions will be evaluated
605
        casex ({samebank, fromcmd, cmd})
606
            {1'b0, LOAD_MODE, 4'b0xxx  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                       $display ("%m: at time %t ERROR:  tMRD violation during %s", $time, cmd_string[cmd]);                         end
607
            {1'b0, LOAD_MODE, 4'b100x  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                 begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time);                    init_done = 0; end end
608
            {1'b0, REFRESH  , 4'b0xxx  } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                       $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);                         end
609
            {1'b0, REFRESH  , PWR_DOWN } : ; // 1 tCK
610
            {1'b0, REFRESH  , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                 begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time);                       init_done = 0; end end
611
            {1'b0, PRECHARGE, 4'b000x  } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
612
                                                 if ($time - tm_precharge < TRP)                                                                                          $display ("%m: at time %t ERROR:   tRP violation during %s", $time, cmd_string[cmd]);                         end
613
            {1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA))                                                                          $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
614
                                                 if (DEBUG && ($time - tm_bank_precharge[bank] < TRP))                                                                    $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank);  end
615
            {1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
616
                                                 if ($time - tm_bank_precharge[bank] < TRP)                                                                               $display ("%m: at time %t ERROR:   tRP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
617
            {1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
618
            {1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP))                                             begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time);                     init_done = 0; end end
619
            {1'b0, ACTIVATE , REFRESH  } : begin if ($time - tm_activate < TRC)                                                                                           $display ("%m: at time %t ERROR:   tRC violation during %s", $time, cmd_string[cmd]);                         end
620
            {1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1))                                         $display ("%m: at time %t ERROR:  tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
621
                                                 if ($time - tm_bank_activate[bank] < TRAS_MIN)                                                                           $display ("%m: at time %t ERROR:  tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
622
            {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD)                                                                                          $display ("%m: at time %t ERROR:  tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
623
            {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC)                                                                                $display ("%m: at time %t ERROR:   tRC violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
624
            {1'b1, ACTIVATE , 4'b010x  } : ; // tRCD is checked outside this task
625
            {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
626
            {1'b1, WRITE    , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR))        $display ("%m: at time %t ERROR:   tWR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
627
            {1'b0, WRITE    , WRITE    } : begin if (ck_cntr - ck_write < TCCD)                                                                                           $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
628
            {1'b0, WRITE    , READ     } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency))           $display ("%m: at time %t ERROR:  tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
629
            {1'b0, WRITE    , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
630
                                                    |write_precharge_bank
631
                                                 || (ck_cntr - ck_write_ap < 1)
632
                                                 || (ck_cntr - ck_write < write_latency + burst_length/2 + 2)
633
                                                 || ($time - tm_write_end < TWTR)))                                                                                 begin $display ("%m: at time %t INFO: Write to Reset condition", $time);                         init_done = 0; end end
634
            {1'b1, READ     , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP))       $display ("%m: at time %t ERROR:  tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
635
            {1'b0, READ     , WRITE    } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency))                 $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
636
            {1'b0, READ     , READ     } : begin if (ck_cntr - ck_read < TCCD)                                                                                            $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
637
            {1'b0, READ     , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1))                           begin $display ("%m: at time %t INFO: Read to Reset condition", $time);                          init_done = 0; end end
638
            {1'b0, PWR_DOWN , 4'b00xx  } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
639
            {1'b0, PWR_DOWN , WRITE    } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
640
            {1'b0, PWR_DOWN , READ     } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency)                                                               $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
641
                                            else if (ck_cntr - ck_power_down < TXARD)                                                                                     $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]);                         end
642
            {1'b0, SELF_REF , 4'b00xx  } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
643
            {1'b0, SELF_REF , WRITE    } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
644
            {1'b0, SELF_REF , READ     } : begin if (ck_cntr - ck_self_refresh < TXSRD)                                                                                   $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]);                         end
645
            {1'b0, 4'b100x  , 4'b100x  } : begin if (ck_cntr - ck_cke < TCKE)                                                                                       begin $display ("%m: at time %t ERROR:  tCKE violation on CKE", $time);                          init_done = 0; end end
646
        endcase
647
    end
648
    endtask
649
 
650
    task cmd_task;
651
        input cke;
652
        input [2:0] cmd;
653
        input [BA_BITS-1:0] bank;
654
        input [ADDR_BITS-1:0] addr;
655
        reg [`BANKS:0] i;
656
        integer j;
657
        reg [`BANKS:0] tfaw_cntr;
658
        reg [COL_BITS-1:0] col;
659
        begin
660
 
661
            // tRFC max check
662
            if (!er_trfc_max && !in_self_refresh) begin
663
                if ($time - tm_refresh > TRFC_MAX) begin
664
                    $display ("%m: at time %t ERROR:  tRFC maximum violation during %s", $time, cmd_string[cmd]);
665
                    er_trfc_max = 1;
666
                end
667
            end
668
            if (cke) begin
669
                if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
670
                    for (j=0; j<NOP; j=j+1) begin
671
                        chk_err(1'b0, bank, j, cmd);
672
                        chk_err(1'b1, bank, j, cmd);
673
                    end
674
                    chk_err(1'b0, bank, PWR_DOWN, cmd);
675
                    chk_err(1'b0, bank, SELF_REF, cmd);
676
                end
677
 
678
                case (cmd)
679
                    LOAD_MODE : begin
680
                        if (|active_bank) begin
681
                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
682
                            if (STOP_ON_ERROR) $stop(0);
683
                        end else begin
684
                            if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
685
                            case (bank)
686
 
687
                                    // Burst Length
688
                                    burst_length = 1<<addr[2:0];
689
                                    if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
690
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
691
                                    end else begin
692
                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
693
                                    end
694
                                    // Burst Order
695
                                    burst_order = addr[3];
696
                                    if (!burst_order) begin
697
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
698
                                    end else if (burst_order) begin
699
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
700
                                    end else begin
701
                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
702
                                    end
703
                                    // CAS Latency
704
                                    cas_latency = addr[6:4];
705
                                    read_latency = cas_latency + additive_latency;
706
                                    write_latency = read_latency - 1;
707
                                    if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
708
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
709
                                    end else begin
710
                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
711
                                    end
712
                                    // Test Mode
713
                                    if (!addr[7]) begin
714
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
715
                                    end else begin
716
                                        $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
717
                                    end
718
                                    // DLL Reset
719
                                    dll_reset = addr[8];
720
                                    if (!dll_reset) begin
721
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
722
                                    end else if (dll_reset) begin
723
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
724
                                        dll_locked = 0;
725
                                        ck_dll_reset <= ck_cntr;
726
                                    end else begin
727
                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
728
                                    end
729
                                    // Write Recovery
730
                                    write_recovery  = addr[11:9] + 1;
731
                                    if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
732
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
733
                                    end else begin
734
                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
735
                                    end
736
                                    // Power Down Mode
737
                                    low_power = addr[12];
738
                                    if (!low_power) begin
739
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
740
                                    end else if (low_power) begin
741
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
742
                                    end else begin
743
                                        $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
744
                                    end
745
                                end
746
                                1 : begin
747
                                    // DLL Enable
748
                                    dll_en = !addr[0];
749
                                    if (!dll_en) begin
750
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
751
                                    end else if (dll_en) begin
752
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
753
                                    end else begin
754
                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
755
                                    end
756
                                    // Output Drive Strength
757
                                    if (!addr[1]) begin
758
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
759
                                    end else if (addr[1]) begin
760
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
761
                                    end else begin
762
                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
763
                                    end
764
                                    // ODT Rtt
765
                                    odt_rtt = {addr[6], addr[2]};
766
                                    if (odt_rtt == 2'b00) begin
767
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
768
                                        odt_en = 0;
769
                                    end else if (odt_rtt == 2'b01) begin
770
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
771
                                        odt_en = 1;
772
                                        tm_odt_en <= $time;
773
                                    end else if (odt_rtt == 2'b10) begin
774
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
775
                                        odt_en = 1;
776
                                        tm_odt_en <= $time;
777
                                    end else if (odt_rtt == 2'b11) begin
778
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
779
                                        odt_en = 1;
780
                                        tm_odt_en <= $time;
781
                                    end else begin
782
                                        $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
783
                                        odt_en = 0;
784
                                    end
785
                                    // Additive Latency
786
                                    additive_latency = addr[5:3];
787
                                    read_latency = cas_latency + additive_latency;
788
                                    write_latency = read_latency - 1;
789
                                    if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
790
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
791
                                    end else begin
792
                                        $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
793
                                    end
794
                                    // OCD Program
795
                                    ocd = addr[9:7];
796
                                    if (ocd == 3'b000) begin
797
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
798
                                    end else if (ocd == 3'b111) begin
799
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
800
                                    end else begin
801
                                        $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
802
                                    end
803
 
804
                                    // DQS_N Enable
805
                                    dqs_n_en = !addr[10];
806
                                    if (!dqs_n_en) begin
807
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
808
                                    end else if (dqs_n_en) begin
809
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
810
                                    end else begin
811
                                        $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
812
                                    end
813
                                    // RDQS Enable
814
                                    rdqs_en = addr[11];
815
                                    if (!rdqs_en) begin
816
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
817
                                    end else if (rdqs_en) begin
818
`ifdef x8
819
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
820
`else
821
                                        $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable.  RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
822
                                        rdqs_en = 0;
823
`endif
824
                                    end else begin
825
                                        $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
826
                                    end
827
                                    // Output Enable
828
                                    out_en = !addr[12];
829
                                    if (!out_en) begin
830
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
831
                                    end else if (out_en) begin
832
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
833
                                    end else begin
834
                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
835
                                    end
836
                                end
837
                                2 : begin
838
                                    // High Temperature Self Refresh rate
839
                                    if (!addr[7]) begin
840
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Disabled", $time, cmd_string[cmd], bank);
841
                                    end else if (addr[1]) begin
842
                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Enabled", $time, cmd_string[cmd], bank);
843
                                    end else begin
844
                                        $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
845
                                    end
846
                                    if ((addr & ~(1<<7)) !== 0) begin
847
                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
848
                                    end
849
                                end
850
                                3 : begin
851
                                    if (addr !== 0) begin
852
                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
853
                                    end
854
                                end
855
                            endcase
856
                            init_mode_reg[bank] = 1;
857
                            ck_load_mode <= ck_cntr;
858
                        end
859
                    end
860
                    REFRESH : begin
861
                        if (|active_bank) begin
862
                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
863
                            if (STOP_ON_ERROR) $stop(0);
864
                        end else begin
865
                            if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
866
                            er_trfc_max = 0;
867
                            ref_cntr = ref_cntr + 1;
868
                            tm_refresh <= $time;
869
                        end
870
                    end
871
                    PRECHARGE : begin
872
                        if (addr[AP]) begin
873
                            // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
874
                            // the number of banks already open or closed.
875
                            for (i=0; i<`BANKS; i=i+1) begin
876
                                for (j=0; j<NOP; j=j+1) begin
877
                                    chk_err(1'b0, i, j, cmd);
878
                                    chk_err(1'b1, i, j, cmd);
879
                                end
880
                                chk_err(1'b0, i, PWR_DOWN, cmd);
881
                                chk_err(1'b0, i, SELF_REF, cmd);
882
                            end
883
                            if (|auto_precharge_bank) begin
884
                                $display ("%m: at time %t ERROR: %s All Failure.  Auto Precharge is scheduled.", $time, cmd_string[cmd]);
885
                                if (STOP_ON_ERROR) $stop(0);
886
                            end else begin
887
                                if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
888
                                active_bank = 0;
889
                                tm_precharge_all <= $time;
890
                            end
891
                        end else begin
892
                            // A PRECHARGE command is allowed if there is no open row in that bank (idle state) 
893
                            // or if the previously open row is already in the process of precharging. 
894
                            // However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
895
                            if (auto_precharge_bank[bank]) begin
896
                                $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
897
                                if (STOP_ON_ERROR) $stop(0);
898
                            end else begin
899
                                if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
900
                                active_bank[bank] = 1'b0;
901
                                tm_bank_precharge[bank] <= $time;
902
                                tm_precharge <= $time;
903
                            end
904
                        end
905
                    end
906
                    ACTIVATE : begin
907
                        if (`BANKS == 8) begin
908
                            tfaw_cntr = 0;
909
                            for (i=0; i<`BANKS; i=i+1) begin
910
                                if ($time - tm_bank_activate[i] < TFAW) begin
911
                                    tfaw_cntr = tfaw_cntr + 1;
912
                                end
913
                            end
914
                            if (tfaw_cntr > 3) begin
915
                                $display ("%m: at time %t ERROR:  tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
916
                            end
917
                        end
918
 
919
                        if (!init_done) begin
920
                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
921
                            if (STOP_ON_ERROR) $stop(0);
922
                        end else if (active_bank[bank]) begin
923
                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
924
                            if (STOP_ON_ERROR) $stop(0);
925
                        end else begin
926
                            if (addr >= 1<<ROW_BITS) begin
927
                                $display ("%m: at time %t WARNING: row = %h does not exist.  Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
928
                            end
929
                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
930
                            active_bank[bank] = 1'b1;
931
                            active_row[bank] = addr;
932
                            tm_bank_activate[bank] <= $time;
933
                            tm_activate <= $time;
934
                        end
935
 
936
                    end
937
                    WRITE : begin
938
                        if (!init_done) begin
939
                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
940
                            if (STOP_ON_ERROR) $stop(0);
941
                        end else if (!active_bank[bank]) begin
942
                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
943
                            if (STOP_ON_ERROR) $stop(0);
944
                        end else if (auto_precharge_bank[bank]) begin
945
                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
946
                            if (STOP_ON_ERROR) $stop(0);
947
                        end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
948
                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
949
                            if (STOP_ON_ERROR) $stop(0);
950
                        end else begin
951
                            if (addr[AP]) begin
952
                                auto_precharge_bank[bank] = 1'b1;
953
                                write_precharge_bank[bank] = 1'b1;
954
                            end
955
                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
956
                            if (col >= 1<<COL_BITS) begin
957
                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
958
                            end
959
                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
960
                            wr_pipeline[2*write_latency + 1]  = 1;
961
                            ba_pipeline[2*write_latency + 1]  = bank;
962
                            row_pipeline[2*write_latency + 1] = active_row[bank];
963
                            col_pipeline[2*write_latency + 1] = col;
964
                            ck_bank_write[bank] <= ck_cntr;
965
                            ck_write <= ck_cntr;
966
                        end
967
                    end
968
                    READ : begin
969
                        if (!dll_locked)
970
                            $display ("%m: at time %t WARNING: %s prior to DLL locked.  Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
971
                        if (!init_done) begin
972
                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
973
                            if (STOP_ON_ERROR) $stop(0);
974
                        end else if (!active_bank[bank]) begin
975
                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
976
                            if (STOP_ON_ERROR) $stop(0);
977
                        end else if (auto_precharge_bank[bank]) begin
978
                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
979
                            if (STOP_ON_ERROR) $stop(0);
980
                        end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
981
                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
982
                            if (STOP_ON_ERROR) $stop(0);
983
                        end else begin
984
                            if (addr[AP]) begin
985
                                auto_precharge_bank[bank] = 1'b1;
986
                                read_precharge_bank[bank] = 1'b1;
987
                            end
988
                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
989
                            if (col >= 1<<COL_BITS) begin
990
                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
991
                            end
992
                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
993
                            rd_pipeline[2*read_latency - 1]  = 1;
994
                            ba_pipeline[2*read_latency - 1]  = bank;
995
                            row_pipeline[2*read_latency - 1] = active_row[bank];
996
                            col_pipeline[2*read_latency - 1] = col;
997
                            ck_bank_read[bank] <= ck_cntr;
998
                            ck_read <= ck_cntr;
999
                        end
1000
                    end
1001
                    NOP: begin
1002
                        if (in_power_down) begin
1003
                            if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
1004
                            in_power_down = 0;
1005
                            if (|active_bank & low_power) begin // slow exit active power down
1006
                                ck_slow_exit_pd <= ck_cntr;
1007
                            end
1008
                            ck_power_down <= ck_cntr;
1009
                        end
1010
                        if (in_self_refresh) begin
1011
                            if ($time - tm_cke < TISXR)
1012
                                $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
1013
                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
1014
                            in_self_refresh = 0;
1015
                            ck_dll_reset <= ck_cntr;
1016
                            ck_self_refresh <= ck_cntr;
1017
                            tm_self_refresh <= $time;
1018
                            tm_refresh <= $time;
1019
                        end
1020
                    end
1021
                endcase
1022
                if ((prev_cke !== 1) && (cmd !== NOP)) begin
1023
                    $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
1024
                end
1025
                if (!init_done) begin
1026
                    case (init_step)
1027
 
1028
                            if ($time < 200000000)
1029
                                $display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
1030
//                          if (cmd_chk + 200000000 > $time)
1031
//                              $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
1032
                            init_step = init_step + 1;
1033
                        end
1034
                        1 : if (dll_en)        init_step = init_step + 1;
1035
                        2 : begin
1036
                            if (&init_mode_reg && dll_reset) begin
1037
                                active_bank = {`BANKS{1'b1}};   // require Precharge All or bank Precharges
1038
                                ref_cntr = 0;                   // require refresh
1039
                                init_step = init_step + 1;
1040
                            end
1041
                        end
1042
                        3 : if (ref_cntr == 2) begin
1043
                            init_step = init_step + 1;
1044
                        end
1045
                        4 : if (!dll_reset)    init_step = init_step + 1;
1046
                        5 : if (ocd == 3'b111) init_step = init_step + 1;
1047
                        6 : begin
1048
                            if (ocd == 3'b000) begin
1049
                                if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
1050
                                init_done = 1;
1051
                            end
1052
                        end
1053
                    endcase
1054
                end
1055
            end else if (prev_cke) begin
1056
                if ((!init_done) && (init_step > 1)) begin
1057
                    $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
1058
                    if (STOP_ON_ERROR) $stop(0);
1059
                end
1060
                case (cmd)
1061
                    REFRESH : begin
1062
                        for (j=0; j<NOP; j=j+1) begin
1063
                            chk_err(1'b0, bank, j, SELF_REF);
1064
                        end
1065
                        chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
1066
                        chk_err(1'b0, bank, SELF_REF, SELF_REF);
1067
                        if (|active_bank) begin
1068
                            $display ("%m: at time %t ERROR: Self Refresh Failure.  All banks must be Precharged.", $time);
1069
                            if (STOP_ON_ERROR) $stop(0);
1070
                            init_done = 0;
1071
                        end else if (odt_en && odt_state) begin
1072
                            $display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
1073
                            if (STOP_ON_ERROR) $stop(0);
1074
                            init_done = 0;
1075
                        end else if (!init_done) begin
1076
                            $display ("%m: at time %t ERROR: Self Refresh Failure.  Initialization sequence is not complete.", $time);
1077
                            if (STOP_ON_ERROR) $stop(0);
1078
                        end else begin
1079
                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
1080
                            in_self_refresh = 1;
1081
                            dll_locked = 0;
1082
                        end
1083
                    end
1084
                    NOP : begin
1085
                        // entering slow_exit or precharge power down and tANPD has not been satisfied
1086
                        if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
1087
                            $display ("%m: at time %t WARNING: tANPD violation during %s.  Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
1088
                        for (j=0; j<NOP; j=j+1) begin
1089
                            chk_err(1'b0, bank, j, PWR_DOWN);
1090
                        end
1091
                        chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
1092
                        chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
1093
 
1094
                        if (!init_done) begin
1095
                            $display ("%m: at time %t ERROR: Power Down Failure.  Initialization sequence is not complete.", $time);
1096
                            if (STOP_ON_ERROR) $stop(0);
1097
                        end else begin
1098
                            if (DEBUG) begin
1099
                                if (|active_bank) begin
1100
                                    $display ("%m: at time %t INFO: Active Power Down Enter", $time);
1101
                                end else begin
1102
                                    $display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
1103
                                end
1104
                            end
1105
                            in_power_down = 1;
1106
                        end
1107
                    end
1108
                    default : begin
1109
                        $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
1110
                        init_done = 0;
1111
                    end
1112
                endcase
1113
                if (!init_done) begin
1114
                    if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred.  Device must be re-initialized.", $time);
1115
                    reset_task;
1116
                end
1117
            end
1118
            prev_cke  = cke;
1119
        end
1120
    endtask
1121
 
1122
    task data_task;
1123
        reg [BA_BITS-1:0] bank;
1124
        reg [ROW_BITS-1:0] row;
1125
        reg [COL_BITS-1:0] col;
1126
        integer i;
1127
        integer j;
1128
        begin
1129
 
1130
            if (diff_ck) begin
1131
                for (i=0; i<36; i=i+1) begin
1132
                    if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
1133
                        $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
1134
                    if (check_write_dqs_high[i])
1135
                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
1136
                end
1137
                check_write_dqs_high <= 0;
1138
            end else begin
1139
                for (i=0; i<36; i=i+1) begin
1140
                    if (dll_locked && dq_in_valid) begin
1141
                        tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
1142
                        if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
1143
                            $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
1144
                    end
1145
                    if (check_write_dqs_low[i])
1146
                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
1147
                end
1148
                check_write_preamble <= 0;
1149
                check_write_postamble <= 0;
1150
                check_write_dqs_low <= 0;
1151
            end
1152
 
1153
            if (wr_pipeline[0] || rd_pipeline[0]) begin
1154
                bank = ba_pipeline[0];
1155
                row = row_pipeline[0];
1156
                col = col_pipeline[0];
1157
                burst_cntr = 0;
1158
                memory_read(bank, row, col, memory_data);
1159
            end
1160
 
1161
            // burst counter
1162
            if (burst_cntr < burst_length) begin
1163
                burst_position = col ^ burst_cntr;
1164
                if (!burst_order) begin
1165
                    burst_position[BO_BITS-1:0] = col + burst_cntr;
1166
                end
1167
                burst_cntr = burst_cntr + 1;
1168
            end
1169
 
1170
            // write dqs counter
1171
            if (wr_pipeline[WDQS_PRE + 1]) begin
1172
                wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
1173
            end
1174
            // write dqs
1175
            if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
1176
                check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1177
            end
1178
            if (wdqs_cntr > 1) begin  // write data
1179
                if ((wdqs_cntr - WDQS_PST)%2) begin
1180
                    check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1181
                end else begin
1182
                    check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1183
                end
1184
            end
1185
            if (wdqs_cntr == WDQS_PST) begin // write postamble
1186
                check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
1187
            end
1188
            if (wdqs_cntr > 0) begin
1189
                wdqs_cntr = wdqs_cntr - 1;
1190
            end
1191
 
1192
            // write dq
1193
            if (dq_in_valid) begin // write data
1194
                bit_mask = 0;
1195
                if (diff_ck) begin
1196
                    for (i=0; i<DM_BITS; i=i+1) begin
1197
                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
1198
                    end
1199
                    memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
1200
                end else begin
1201
                    for (i=0; i<DM_BITS; i=i+1) begin
1202
                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
1203
                    end
1204
                    memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
1205
                end
1206
                dq_temp = memory_data>>(burst_position*DQ_BITS);
1207
                if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
1208
                if (burst_cntr%BL_MIN == 0) begin
1209
                    memory_write(bank, row, col, memory_data);
1210
                end
1211
            end
1212
            if (wr_pipeline[1]) begin
1213
                wdq_cntr = burst_length;
1214
            end
1215
            if (wdq_cntr > 0) begin
1216
                wdq_cntr = wdq_cntr - 1;
1217
                dq_in_valid = 1'b1;
1218
            end else begin
1219
                dq_in_valid = 1'b0;
1220
                dqs_in_valid <= 1'b0;
1221
                for (i=0; i<36; i=i+1) begin
1222
                    wdqs_pos_cntr[i] <= 0;
1223
                end
1224
            end
1225
            if (wr_pipeline[0]) begin
1226
                b2b_write <= 1'b0;
1227
            end
1228
            if (wr_pipeline[2]) begin
1229
                if (dqs_in_valid) begin
1230
                    b2b_write <= 1'b1;
1231
                end
1232
                dqs_in_valid <= 1'b1;
1233
            end
1234
            // read dqs enable counter
1235
            if (rd_pipeline[RDQSEN_PRE]) begin
1236
                rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
1237
            end
1238
            if (rdqsen_cntr > 0) begin
1239
                rdqsen_cntr = rdqsen_cntr - 1;
1240
                dqs_out_en = 1'b1;
1241
            end else begin
1242
                dqs_out_en = 1'b0;
1243
            end
1244
 
1245
            // read dqs counter
1246
            if (rd_pipeline[RDQS_PRE]) begin
1247
                rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
1248
            end
1249
            // read dqs
1250
            if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
1251
                dqs_out = 1'b0;
1252
            end else if (rdqs_cntr > RDQS_PST) begin // read data
1253
                dqs_out = rdqs_cntr - RDQS_PST;
1254
            end else if (rdqs_cntr > 0) begin // read postamble
1255
                dqs_out = 1'b0;
1256
            end else begin
1257
                dqs_out = 1'b1;
1258
            end
1259
            if (rdqs_cntr > 0) begin
1260
                rdqs_cntr = rdqs_cntr - 1;
1261
            end
1262
 
1263
            // read dq enable counter
1264
            if (rd_pipeline[RDQEN_PRE]) begin
1265
                rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
1266
            end
1267
            if (rdqen_cntr > 0) begin
1268
                rdqen_cntr = rdqen_cntr - 1;
1269
                dq_out_en = 1'b1;
1270
            end else begin
1271
                dq_out_en = 1'b0;
1272
            end
1273
            // read dq
1274
            if (rd_pipeline[0]) begin
1275
                rdq_cntr = burst_length;
1276
            end
1277
            if (rdq_cntr > 0) begin // read data
1278
                dq_temp = memory_data>>(burst_position*DQ_BITS);
1279
                dq_out = dq_temp;
1280
                if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
1281
                rdq_cntr = rdq_cntr - 1;
1282
            end else begin
1283
                dq_out = {DQ_BITS{1'b1}};
1284
            end
1285
 
1286
            // delay signals prior to output
1287
            if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
1288
                for (i=0; i<DQS_BITS; i=i+1) begin
1289
                    // DQSCK requirements
1290
                    // 1.) less than tDQSCK
1291
                    // 2.) greater than -tDQSCK
1292
                    // 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
1293
                    dqsck_max = TDQSCK;
1294
                    if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
1295
                        dqsck_max = dqsck[i] + TQHS + TDQSQ;
1296
                    end
1297
                    dqsck_min = -1*TDQSCK;
1298
                    if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
1299
                        dqsck_min = dqsck[i] - TQHS - TDQSQ;
1300
                    end
1301
 
1302
                    // DQSQ requirements
1303
                    // 1.) less than tAC - DQSCK
1304
                    // 2.) less than tDQSQ
1305
                    // 3.) greater than -tAC
1306
                    // 4.) greater than tQH from previous DQS edge
1307
                    dqsq_min = -1*TAC;
1308
                    if (dqsq_min < dqsck[i] - TQHS) begin
1309
                        dqsq_min = dqsck[i] - TQHS;
1310
                    end
1311
                    if (dqsck_min == dqsck_max) begin
1312
                        dqsck[i] = dqsck_min;
1313
                    end else begin
1314
                        dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
1315
                    end
1316
                    dqsq_max = TAC;
1317
                    if (dqsq_max > TDQSQ + dqsck[i]) begin
1318
                        dqsq_max = TDQSQ + dqsck[i];
1319
                    end
1320
 
1321
                    dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
1322
                    dqs_out_dly[i]    <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
1323
                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
1324
                        if (dq_out_en) begin // tLZ2
1325
                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
1326
                        end else begin // tHZ
1327
                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
1328
                        end
1329
                        if (dqsq_min == dqsq_max) begin
1330
                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
1331
                        end else begin
1332
                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
1333
                        end
1334
                    end
1335
                end
1336
            end else begin
1337
                out_delay = tck_avg/2.0;
1338
                dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
1339
                dqs_out_dly    <= #(out_delay) {DQS_BITS{dqs_out   }};
1340
                dq_out_en_dly  <= #(out_delay) {DQ_BITS {dq_out_en }};
1341
                dq_out_dly     <= #(out_delay) {DQ_BITS {dq_out    }};
1342
            end
1343
        end
1344
    endtask
1345
 
1346
    always @(diff_ck) begin : main
1347
        integer i;
1348
 
1349
        if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
1350
            $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
1351
        data_task;
1352
        if (diff_ck) begin
1353
            // check setup of command signals
1354
            if ($time > TIS) begin
1355
                if ($time - tm_cke < TIS)
1356
                    $display ("%m: at time %t ERROR:   tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
1357
                if (cke_in) begin
1358
                    for (i=0; i<22; i=i+1) begin
1359
                        if ($time - tm_cmd_addr[i] < TIS)
1360
                            $display ("%m: at time %t ERROR:   tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
1361
                    end
1362
                end
1363
            end
1364
 
1365
            // update current state
1366
            if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
1367
                // check CL value against the clock frequency
1368
                if (cas_latency*tck_avg < CL_TIME)
1369
                    $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
1370
                // check WR value against the clock frequency
1371
                if (write_recovery*tck_avg < TWR)
1372
                    $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
1373
                dll_locked = 1;
1374
            end
1375
            if (|auto_precharge_bank) begin
1376
                for (i=0; i<`BANKS; i=i+1) begin
1377
                    // Write with Auto Precharge Calculation
1378
                    // 1.  Meet minimum tRAS requirement
1379
                    // 2.  Write Latency PLUS BL/2 cycles PLUS WR after Write command
1380
                    if (write_precharge_bank[i]
1381
                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
1382
                        && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
1383
 
1384
                        if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
1385
                        write_precharge_bank[i] = 0;
1386
                        active_bank[i] = 0;
1387
                        auto_precharge_bank[i] = 0;
1388
                        ck_write_ap = ck_cntr;
1389
                        tm_bank_precharge[i] = $time;
1390
                        tm_precharge = $time;
1391
                    end
1392
                    // Read with Auto Precharge Calculation
1393
                    // 1.  Meet minimum tRAS requirement
1394
                    // 2.  Additive Latency plus BL/2 cycles after Read command
1395
                    // 3.  tRTP after the last 4-bit prefetch
1396
                    if (read_precharge_bank[i]
1397
                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
1398
                        && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
1399
 
1400
                        read_precharge_bank[i] = 0;
1401
                        // In case the internal precharge is pushed out by tRTP, tRP starts at the point where
1402
                        // the internal precharge happens (not at the next rising clock edge after this event).
1403
                        if ($time - tm_bank_read_end[i] < TRTP) begin
1404
                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
1405
                            active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
1406
                            auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
1407
                            tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
1408
                            tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
1409
                        end else begin
1410
                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
1411
                            active_bank[i] = 0;
1412
                            auto_precharge_bank[i] = 0;
1413
                            tm_bank_precharge[i] = $time;
1414
                            tm_precharge = $time;
1415
                        end
1416
                    end
1417
                end
1418
            end
1419
 
1420
            // respond to incoming command
1421
            if (cke_in ^ prev_cke) begin
1422
                ck_cke <= ck_cntr;
1423
            end
1424
 
1425
            cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
1426
            if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
1427
                al_pipeline[2*additive_latency] = 1'b1;
1428
            end
1429
            if (al_pipeline[0]) begin
1430
                // check tRCD after additive latency
1431
                if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
1432
                    if (rd_pipeline[2*cas_latency - 1]) begin
1433
                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[READ]);
1434
                    end else begin
1435
                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[WRITE]);
1436
                    end
1437
                end
1438
                // check tWTR after additive latency
1439
                if (rd_pipeline[2*cas_latency - 1]) begin
1440
                    if ($time - tm_write_end < TWTR)
1441
                        $display ("%m: at time %t ERROR:  tWTR violation during %s", $time, cmd_string[READ]);
1442
                end
1443
            end
1444
            if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
1445
                tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
1446
            end
1447
            for (i=0; i<`BANKS; i=i+1) begin
1448
                if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
1449
                    tm_bank_write_end[i] <= $time;
1450
                    tm_write_end <= $time;
1451
                end
1452
            end
1453
 
1454
            // clk pin is disabled during self refresh
1455
            if (!in_self_refresh) begin
1456
                tjit_cc_time = $time - tm_ck_pos - tck_i;
1457
                tck_i   = $time - tm_ck_pos;
1458
                tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
1459
                tck_avg = tck_avg + tck_i/$itor(TDLLK);
1460
                tck_sample[ck_cntr%TDLLK] = tck_i;
1461
                tjit_per_rtime = tck_i - tck_avg;
1462
 
1463
                if (dll_locked) begin
1464
                    // check accumulated error
1465
                    terr_nper_rtime = 0;
1466
                    for (i=0; i<50; i=i+1) begin
1467
                        terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
1468
                        terr_nper_rtime = abs_value(terr_nper_rtime);
1469
                        case (i)
1470
 
1471
                                  1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
1472
                                  2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
1473
                                  3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
1474
                                  4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
1475
                          5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
1476
                            default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
1477
                        endcase
1478
                    end
1479
 
1480
                    // check tCK min/max/jitter
1481
                    if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
1482
                        $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
1483
                    if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
1484
                        $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
1485
                    if (TCK_MIN - tck_avg >= 1.0)
1486
                        $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
1487
                    if (tck_avg - TCK_MAX >= 1.0)
1488
                        $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
1489
                    if (tm_ck_pos + TCK_MIN - TJIT_PER > $time)
1490
                        $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
1491
                    if (tm_ck_pos + TCK_MAX + TJIT_PER < $time)
1492
                        $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
1493
 
1494
                    // check tCL
1495
                    if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time)
1496
                        $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
1497
                    if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time)
1498
                        $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
1499
                    if (tcl_avg < TCL_MIN*tck_avg)
1500
                        $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
1501
                    if (tcl_avg > TCL_MAX*tck_avg)
1502
                        $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
1503
                end
1504
 
1505
                // calculate the tch avg jitter
1506
                tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
1507
                tch_avg = tch_avg + tch_i/$itor(TDLLK);
1508
                tch_sample[ck_cntr%TDLLK] = tch_i;
1509
 
1510
                // update timers/counters
1511
                tcl_i <= $time - tm_ck_neg;
1512
            end
1513
 
1514
            prev_odt <= odt_in;
1515
            // update timers/counters
1516
            ck_cntr <= ck_cntr + 1;
1517
            tm_ck_pos <= $time;
1518
        end else begin
1519
            // clk pin is disabled during self refresh
1520
            if (!in_self_refresh) begin
1521
                if (dll_locked) begin
1522
                    if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time)
1523
                        $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
1524
                    if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time)
1525
                        $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
1526
                    if (tch_avg < TCH_MIN*tck_avg)
1527
                        $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
1528
                    if (tch_avg > TCH_MAX*tck_avg)
1529
                        $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
1530
                end
1531
 
1532
                // calculate the tcl avg jitter
1533
                tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
1534
                tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
1535
                tcl_sample[ck_cntr%TDLLK] = tcl_i;
1536
 
1537
                // update timers/counters
1538
                tch_i <= $time - tm_ck_pos;
1539
            end
1540
            tm_ck_neg <= $time;
1541
        end
1542
 
1543
        // on die termination
1544
        if (odt_en) begin
1545
            // clk pin is disabled during self refresh
1546
            if (!in_self_refresh && diff_ck) begin
1547
                if ($time - tm_odt < TIS) begin
1548
                    $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
1549
                end
1550
                if (prev_odt ^ odt_in) begin
1551
                    if (!dll_locked)
1552
                        $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
1553
                    if (odt_in && ($time - tm_odt_en  < TMOD))
1554
                        $display ("%m: at time %t ERROR:  tMOD violation during ODT transition", $time);
1555
                    if ($time - tm_self_refresh < TXSNR)
1556
                        $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
1557
                    if (in_self_refresh)
1558
                        $display ("%m: at time %t ERROR:  Illegal ODT transition during Self Refresh.", $time);
1559
 
1560
                    // async ODT mode applies:
1561
                    // 1.) during active power down with slow exit
1562
                    // 2.) during precharge power down
1563
                    // 3.) if tANPD has not been satisfied
1564
                    // 4.) until tAXPD has been satisfied
1565
                    if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
1566
                        if (ck_cntr - ck_slow_exit_pd < TAXPD)
1567
                            $display ("%m: at time %t WARNING: tAXPD violation during ODT transition.  Synchronous or asynchronous change in termination resistance is possible.", $time);
1568
                        if (odt_in) begin
1569
                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
1570
                            odt_state <= #(TAONPD) 1'b1;
1571
                        end else begin
1572
                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
1573
                            odt_state <= #(TAOFPD) 1'b0;
1574
                        end
1575
                    // sync ODT mode applies:
1576
                    // 1.) during normal operation
1577
                    // 2.) during active power down with fast exit
1578
                    end else begin
1579
                        if (odt_in) begin
1580
                            i = TAOND*2;
1581
                            odt_pipeline[i] = 1'b1;
1582
                        end else begin
1583
                            i = TAOFD*2;
1584
                            odt_pipeline[i] = 1'b1;
1585
                        end
1586
                    end
1587
                    ck_odt <= ck_cntr;
1588
                end
1589
            end
1590
            if (odt_pipeline[0]) begin
1591
                odt_state = ~odt_state;
1592
                if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
1593
            end
1594
        end
1595
 
1596
        // shift pipelines
1597
        if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
1598
            al_pipeline = al_pipeline>>1;
1599
            wr_pipeline = wr_pipeline>>1;
1600
            rd_pipeline = rd_pipeline>>1;
1601
            for (i=0; i<`MAX_PIPE; i=i+1) begin
1602
                ba_pipeline[i] = ba_pipeline[i+1];
1603
                row_pipeline[i] = row_pipeline[i+1];
1604
                col_pipeline[i] = col_pipeline[i+1];
1605
            end
1606
        end
1607
        if (|odt_pipeline) begin
1608
            odt_pipeline = odt_pipeline>>1;
1609
        end
1610
    end
1611
 
1612
    // receiver(s)
1613
    task dqs_even_receiver;
1614
        input [4:0] i;
1615
        reg [71:0] bit_mask;
1616
        begin
1617
            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
1618
            if (dqs_even[i]) begin
1619
                if (rdqs_en) begin // rdqs disables dm
1620
                    dm_in_pos[i] = 1'b0;
1621
                end else begin
1622
                    dm_in_pos[i] = dm_in[i];
1623
                end
1624
                dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
1625
            end
1626
        end
1627
    endtask
1628
 
1629
    always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
1630
    always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
1631
    always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
1632
    always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
1633
    always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
1634
    always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
1635
    always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
1636
    always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
1637
    always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
1638
    always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
1639
    always @(posedge dqs_even[10]) dqs_even_receiver(10);
1640
    always @(posedge dqs_even[11]) dqs_even_receiver(11);
1641
    always @(posedge dqs_even[12]) dqs_even_receiver(12);
1642
    always @(posedge dqs_even[13]) dqs_even_receiver(13);
1643
    always @(posedge dqs_even[14]) dqs_even_receiver(14);
1644
    always @(posedge dqs_even[15]) dqs_even_receiver(15);
1645
    always @(posedge dqs_even[16]) dqs_even_receiver(16);
1646
    always @(posedge dqs_even[17]) dqs_even_receiver(17);
1647
 
1648
    task dqs_odd_receiver;
1649
        input [4:0] i;
1650
        reg [71:0] bit_mask;
1651
        begin
1652
            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
1653
            if (dqs_odd[i]) begin
1654
                if (rdqs_en) begin // rdqs disables dm
1655
                    dm_in_neg[i] = 1'b0;
1656
                end else begin
1657
                    dm_in_neg[i] = dm_in[i];
1658
                end
1659
                dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
1660
            end
1661
        end
1662
    endtask
1663
 
1664
    always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
1665
    always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
1666
    always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
1667
    always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
1668
    always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
1669
    always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
1670
    always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
1671
    always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
1672
    always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
1673
    always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
1674
    always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
1675
    always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
1676
    always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
1677
    always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
1678
    always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
1679
    always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
1680
    always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
1681
    always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
1682
 
1683
    // Processes to check hold and pulse width of control signals
1684
    always @(cke_in) begin
1685
        if ($time > TIH) begin
1686
            if ($time - tm_ck_pos < TIH)
1687
                $display ("%m: at time %t ERROR:  tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
1688
        end
1689
        if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
1690
            $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
1691
        tm_cke = $time;
1692
    end
1693
    always @(odt_in) begin
1694
        if (odt_en && !in_self_refresh) begin
1695
            if ($time - tm_ck_pos < TIH)
1696
                $display ("%m: at time %t ERROR:  tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
1697
            if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
1698
                $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
1699
        end
1700
        tm_odt = $time;
1701
    end
1702
 
1703
    task cmd_addr_timing_check;
1704
    input i;
1705
    reg [4:0] i;
1706
    begin
1707
        if (prev_cke) begin
1708
            if ($time - tm_ck_pos < TIH)
1709
                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
1710
            if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
1711
                $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
1712
        end
1713
        tm_cmd_addr[i] = $time;
1714
    end
1715
    endtask
1716
 
1717
    always @(cs_n_in    ) cmd_addr_timing_check( 0);
1718
    always @(ras_n_in   ) cmd_addr_timing_check( 1);
1719
    always @(cas_n_in   ) cmd_addr_timing_check( 2);
1720
    always @(we_n_in    ) cmd_addr_timing_check( 3);
1721
    always @(ba_in  [ 0]) cmd_addr_timing_check( 4);
1722
    always @(ba_in  [ 1]) cmd_addr_timing_check( 5);
1723
    always @(ba_in  [ 2]) cmd_addr_timing_check( 6);
1724
    always @(addr_in[ 0]) cmd_addr_timing_check( 7);
1725
    always @(addr_in[ 1]) cmd_addr_timing_check( 8);
1726
    always @(addr_in[ 2]) cmd_addr_timing_check( 9);
1727
    always @(addr_in[ 3]) cmd_addr_timing_check(10);
1728
    always @(addr_in[ 4]) cmd_addr_timing_check(11);
1729
    always @(addr_in[ 5]) cmd_addr_timing_check(12);
1730
    always @(addr_in[ 6]) cmd_addr_timing_check(13);
1731
    always @(addr_in[ 7]) cmd_addr_timing_check(14);
1732
    always @(addr_in[ 8]) cmd_addr_timing_check(15);
1733
    always @(addr_in[ 9]) cmd_addr_timing_check(16);
1734
    always @(addr_in[10]) cmd_addr_timing_check(17);
1735
    always @(addr_in[11]) cmd_addr_timing_check(18);
1736
    always @(addr_in[12]) cmd_addr_timing_check(19);
1737
    always @(addr_in[13]) cmd_addr_timing_check(20);
1738
    always @(addr_in[14]) cmd_addr_timing_check(21);
1739
    always @(addr_in[15]) cmd_addr_timing_check(22);
1740
 
1741
    // Processes to check setup and hold of data signals
1742
    task dm_timing_check;
1743
    input i;
1744
    reg [4:0] i;
1745
    begin
1746
        if (dqs_in_valid) begin
1747
            if ($time - tm_dqs[i] < TDH)
1748
                $display ("%m: at time %t ERROR:   tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
1749
            if (check_dm_tdipw[i]) begin
1750
                if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
1751
                    $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
1752
            end
1753
        end
1754
        check_dm_tdipw[i] <= 1'b0;
1755
        tm_dm[i] = $time;
1756
    end
1757
    endtask
1758
 
1759
    always @(dm_in[ 0]) dm_timing_check( 0);
1760
    always @(dm_in[ 1]) dm_timing_check( 1);
1761
    always @(dm_in[ 2]) dm_timing_check( 2);
1762
    always @(dm_in[ 3]) dm_timing_check( 3);
1763
    always @(dm_in[ 4]) dm_timing_check( 4);
1764
    always @(dm_in[ 5]) dm_timing_check( 5);
1765
    always @(dm_in[ 6]) dm_timing_check( 6);
1766
    always @(dm_in[ 7]) dm_timing_check( 7);
1767
    always @(dm_in[ 8]) dm_timing_check( 8);
1768
    always @(dm_in[ 9]) dm_timing_check( 9);
1769
    always @(dm_in[10]) dm_timing_check(10);
1770
    always @(dm_in[11]) dm_timing_check(11);
1771
    always @(dm_in[12]) dm_timing_check(12);
1772
    always @(dm_in[13]) dm_timing_check(13);
1773
    always @(dm_in[14]) dm_timing_check(14);
1774
    always @(dm_in[15]) dm_timing_check(15);
1775
    always @(dm_in[16]) dm_timing_check(16);
1776
    always @(dm_in[17]) dm_timing_check(17);
1777
 
1778
    task dq_timing_check;
1779
    input i;
1780
    reg [6:0] i;
1781
    begin
1782
        if (dqs_in_valid) begin
1783
            if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
1784
                $display ("%m: at time %t ERROR:   tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
1785
            if (check_dq_tdipw[i]) begin
1786
                if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
1787
                    $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
1788
            end
1789
        end
1790
        check_dq_tdipw[i] <= 1'b0;
1791
        tm_dq[i] = $time;
1792
    end
1793
    endtask
1794
 
1795
    always @(dq_in[ 0]) dq_timing_check( 0);
1796
    always @(dq_in[ 1]) dq_timing_check( 1);
1797
    always @(dq_in[ 2]) dq_timing_check( 2);
1798
    always @(dq_in[ 3]) dq_timing_check( 3);
1799
    always @(dq_in[ 4]) dq_timing_check( 4);
1800
    always @(dq_in[ 5]) dq_timing_check( 5);
1801
    always @(dq_in[ 6]) dq_timing_check( 6);
1802
    always @(dq_in[ 7]) dq_timing_check( 7);
1803
    always @(dq_in[ 8]) dq_timing_check( 8);
1804
    always @(dq_in[ 9]) dq_timing_check( 9);
1805
    always @(dq_in[10]) dq_timing_check(10);
1806
    always @(dq_in[11]) dq_timing_check(11);
1807
    always @(dq_in[12]) dq_timing_check(12);
1808
    always @(dq_in[13]) dq_timing_check(13);
1809
    always @(dq_in[14]) dq_timing_check(14);
1810
    always @(dq_in[15]) dq_timing_check(15);
1811
    always @(dq_in[16]) dq_timing_check(16);
1812
    always @(dq_in[17]) dq_timing_check(17);
1813
    always @(dq_in[18]) dq_timing_check(18);
1814
    always @(dq_in[19]) dq_timing_check(19);
1815
    always @(dq_in[20]) dq_timing_check(20);
1816
    always @(dq_in[21]) dq_timing_check(21);
1817
    always @(dq_in[22]) dq_timing_check(22);
1818
    always @(dq_in[23]) dq_timing_check(23);
1819
    always @(dq_in[24]) dq_timing_check(24);
1820
    always @(dq_in[25]) dq_timing_check(25);
1821
    always @(dq_in[26]) dq_timing_check(26);
1822
    always @(dq_in[27]) dq_timing_check(27);
1823
    always @(dq_in[28]) dq_timing_check(28);
1824
    always @(dq_in[29]) dq_timing_check(29);
1825
    always @(dq_in[30]) dq_timing_check(30);
1826
    always @(dq_in[31]) dq_timing_check(31);
1827
    always @(dq_in[32]) dq_timing_check(32);
1828
    always @(dq_in[33]) dq_timing_check(33);
1829
    always @(dq_in[34]) dq_timing_check(34);
1830
    always @(dq_in[35]) dq_timing_check(35);
1831
    always @(dq_in[36]) dq_timing_check(36);
1832
    always @(dq_in[37]) dq_timing_check(37);
1833
    always @(dq_in[38]) dq_timing_check(38);
1834
    always @(dq_in[39]) dq_timing_check(39);
1835
    always @(dq_in[40]) dq_timing_check(40);
1836
    always @(dq_in[41]) dq_timing_check(41);
1837
    always @(dq_in[42]) dq_timing_check(42);
1838
    always @(dq_in[43]) dq_timing_check(43);
1839
    always @(dq_in[44]) dq_timing_check(44);
1840
    always @(dq_in[45]) dq_timing_check(45);
1841
    always @(dq_in[46]) dq_timing_check(46);
1842
    always @(dq_in[47]) dq_timing_check(47);
1843
    always @(dq_in[48]) dq_timing_check(48);
1844
    always @(dq_in[49]) dq_timing_check(49);
1845
    always @(dq_in[50]) dq_timing_check(50);
1846
    always @(dq_in[51]) dq_timing_check(51);
1847
    always @(dq_in[52]) dq_timing_check(52);
1848
    always @(dq_in[53]) dq_timing_check(53);
1849
    always @(dq_in[54]) dq_timing_check(54);
1850
    always @(dq_in[55]) dq_timing_check(55);
1851
    always @(dq_in[56]) dq_timing_check(56);
1852
    always @(dq_in[57]) dq_timing_check(57);
1853
    always @(dq_in[58]) dq_timing_check(58);
1854
    always @(dq_in[59]) dq_timing_check(59);
1855
    always @(dq_in[60]) dq_timing_check(60);
1856
    always @(dq_in[61]) dq_timing_check(61);
1857
    always @(dq_in[62]) dq_timing_check(62);
1858
    always @(dq_in[63]) dq_timing_check(63);
1859
    always @(dq_in[64]) dq_timing_check(64);
1860
    always @(dq_in[65]) dq_timing_check(65);
1861
    always @(dq_in[66]) dq_timing_check(66);
1862
    always @(dq_in[67]) dq_timing_check(67);
1863
    always @(dq_in[68]) dq_timing_check(68);
1864
    always @(dq_in[69]) dq_timing_check(69);
1865
    always @(dq_in[70]) dq_timing_check(70);
1866
    always @(dq_in[71]) dq_timing_check(71);
1867
 
1868
    task dqs_pos_timing_check;
1869
    input i;
1870
    reg [5:0] i;
1871
    reg [3:0] j;
1872
    begin
1873
        if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
1874
            if (dqs_in[i] ^ prev_dqs_in[i]) begin
1875
                if (dll_locked) begin
1876
                    if (check_write_preamble[i]) begin
1877
                        if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
1878
                            $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
1879
                    end else if (check_write_postamble[i]) begin
1880
                        if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
1881
                            $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
1882
                    end else begin
1883
                        if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
1884
                            $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
1885
                    end
1886
                end
1887
                if ($time - tm_dm[i%18] < TDS)
1888
                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
1889
                if (!dq_out_en) begin
1890
                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
1891
                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
1892
                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
1893
                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
1894
                    end
1895
                end
1896
                if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
1897
                    wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
1898
                end else begin
1899
                    wdqs_pos_cntr[i] <= 1;
1900
                end
1901
                check_dm_tdipw[i%18] <= 1'b1;
1902
                check_write_preamble[i] <= 1'b0;
1903
                check_write_postamble[i] <= 1'b0;
1904
                check_write_dqs_low[i] <= 1'b0;
1905
                tm_dqs[i%18] <= $time;
1906
            end else begin
1907
                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
1908
            end
1909
        end
1910
        tm_dqss_pos[i] <= $time;
1911
        tm_dqs_pos[i] = $time;
1912
        prev_dqs_in[i] <= dqs_in[i];
1913
    end
1914
    endtask
1915
 
1916
    always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
1917
    always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
1918
    always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
1919
    always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
1920
    always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
1921
    always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
1922
    always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
1923
    always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
1924
    always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
1925
    always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
1926
    always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
1927
    always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
1928
    always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
1929
    always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
1930
    always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
1931
    always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
1932
    always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
1933
    always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
1934
    always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
1935
    always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
1936
    always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
1937
    always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
1938
    always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
1939
    always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
1940
    always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
1941
    always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
1942
    always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
1943
    always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
1944
    always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
1945
    always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
1946
    always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
1947
    always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
1948
    always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
1949
    always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
1950
    always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
1951
    always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
1952
 
1953
    task dqs_neg_timing_check;
1954
    input i;
1955
    reg [5:0] i;
1956
    reg [3:0] j;
1957
    begin
1958
        if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
1959
            if (dqs_in[i] ^ prev_dqs_in[i]) begin
1960
                if (dll_locked) begin
1961
                    if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
1962
                        $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
1963
                    if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
1964
                        $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
1965
                end
1966
                if ($time - tm_dm[i%18] < TDS)
1967
                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
1968
                if (!dq_out_en) begin
1969
                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
1970
                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
1971
                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
1972
                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
1973
                    end
1974
                end
1975
                check_dm_tdipw[i%18] <= 1'b1;
1976
                check_write_dqs_high[i] <= 1'b0;
1977
                tm_dqs[i%18] <= $time;
1978
            end else begin
1979
                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
1980
            end
1981
        end
1982
        tm_dqs_neg[i] = $time;
1983
        prev_dqs_in[i] <= dqs_in[i];
1984
    end
1985
    endtask
1986
 
1987
    always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
1988
    always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
1989
    always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
1990
    always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
1991
    always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
1992
    always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
1993
    always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
1994
    always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
1995
    always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
1996
    always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
1997
    always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
1998
    always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
1999
    always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
2000
    always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
2001
    always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
2002
    always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
2003
    always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
2004
    always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
2005
    always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
2006
    always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
2007
    always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
2008
    always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
2009
    always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
2010
    always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
2011
    always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
2012
    always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
2013
    always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
2014
    always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
2015
    always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
2016
    always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
2017
    always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
2018
    always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
2019
    always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
2020
    always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
2021
    always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
2022
    always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
2023
 
2024
endmodule

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