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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_txethmac.v] - Blame information for rev 439

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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  eth_txethmac.v                                              ////
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///                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 409 julius
////  http://www.opencores.org/project,ethmac                   ////
7 6 julius
////                                                              ////
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////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45 403 julius
// $Log: not supported by cvs2svn $
46 6 julius
// Revision 1.8  2003/01/30 13:33:24  mohor
47
// When padding was enabled and crc disabled, frame was not ended correctly.
48
//
49
// Revision 1.7  2002/02/26 16:24:01  mohor
50
// RetryCntLatched was unused and removed from design
51
//
52
// Revision 1.6  2002/02/22 12:56:35  mohor
53
// Retry is not activated when a Tx Underrun occured
54
//
55
// Revision 1.5  2002/02/11 09:18:22  mohor
56
// Tx status is written back to the BD.
57
//
58
// Revision 1.4  2002/01/23 10:28:16  mohor
59
// Link in the header changed.
60
//
61
// Revision 1.3  2001/10/19 08:43:51  mohor
62
// eth_timescale.v changed to timescale.v This is done because of the
63
// simulation of the few cores in a one joined project.
64
//
65
// Revision 1.2  2001/09/11 14:17:00  mohor
66
// Few little NCSIM warnings fixed.
67
//
68
// Revision 1.1  2001/08/06 14:44:29  mohor
69
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
70
// Include files fixed to contain no path.
71
// File names and module names changed ta have a eth_ prologue in the name.
72
// File eth_timescale.v is used to define timescale
73
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
74
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
75
// and Mdo_OE. The bidirectional signal must be created on the top level. This
76
// is done due to the ASIC tools.
77
//
78
// Revision 1.1  2001/07/30 21:23:42  mohor
79
// Directory structure changed. Files checked and joind together.
80
//
81
// Revision 1.3  2001/06/19 18:16:40  mohor
82
// TxClk changed to MTxClk (as discribed in the documentation).
83
// Crc changed so only one file can be used instead of two.
84
//
85
// Revision 1.2  2001/06/19 10:38:08  mohor
86
// Minor changes in header.
87
//
88
// Revision 1.1  2001/06/19 10:27:58  mohor
89
// TxEthMAC initial release.
90
//
91
//
92
//
93
 
94
`include "timescale.v"
95
 
96
 
97
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
98
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
99
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
100
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
101
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
102
                     LateCollision, DeferIndication, StatePreamble, StateData
103
 
104
                    );
105
 
106
parameter Tp = 1;
107
 
108
 
109
input MTxClk;                   // Transmit clock (from PHY)
110
input Reset;                    // Reset
111
input TxStartFrm;               // Transmit packet start frame
112
input TxEndFrm;                 // Transmit packet end frame
113
input TxUnderRun;               // Transmit packet under-run
114
input [7:0] TxData;             // Transmit packet data byte
115
input CarrierSense;             // Carrier sense (synchronized)
116
input Collision;                // Collision (synchronized)
117
input Pad;                      // Pad enable (from register)
118
input CrcEn;                    // Crc enable (from register)
119
input FullD;                    // Full duplex (from register)
120
input HugEn;                    // Huge packets enable (from register)
121
input DlyCrcEn;                 // Delayed Crc enabled (from register)
122
input [15:0] MinFL;             // Minimum frame length (from register)
123
input [15:0] MaxFL;             // Maximum frame length (from register)
124
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
125
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
126
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
127
input [5:0] CollValid;          // Valid collision window (from register)
128
input [3:0] MaxRet;             // Maximum retry number (from register)
129
input NoBckof;                  // No backoff (from register)
130
input ExDfrEn;                  // Excessive defferal enable (from register)
131
 
132
output [3:0] MTxD;              // Transmit nibble (to PHY)
133
output MTxEn;                   // Transmit enable (to PHY)
134
output MTxErr;                  // Transmit error (to PHY)
135
output TxDone;                  // Transmit packet done (to RISC)
136
output TxRetry;                 // Transmit packet retry (to RISC)
137
output TxAbort;                 // Transmit packet abort (to RISC)
138
output TxUsedData;              // Transmit packet used data (to RISC)
139
output WillTransmit;            // Will transmit (to RxEthMAC)
140
output ResetCollision;          // Reset Collision (for synchronizing collision)
141
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
142
output StartTxDone;
143
output StartTxAbort;
144
output MaxCollisionOccured;
145
output LateCollision;
146
output DeferIndication;
147
output StatePreamble;
148
output [1:0] StateData;
149
 
150
reg [3:0] MTxD;
151
reg MTxEn;
152
reg MTxErr;
153
reg TxDone;
154
reg TxRetry;
155
reg TxAbort;
156
reg TxUsedData;
157
reg WillTransmit;
158
reg ColWindow;
159
reg StopExcessiveDeferOccured;
160
reg [3:0] RetryCnt;
161
reg [3:0] MTxD_d;
162
reg StatusLatch;
163
reg PacketFinished_q;
164
reg PacketFinished;
165
 
166
 
167
wire ExcessiveDeferOccured;
168
wire StartIPG;
169
wire StartPreamble;
170
wire [1:0] StartData;
171
wire StartFCS;
172
wire StartJam;
173
wire StartDefer;
174
wire StartBackoff;
175
wire StateDefer;
176
wire StateIPG;
177
wire StateIdle;
178
wire StatePAD;
179
wire StateFCS;
180
wire StateJam;
181
wire StateJam_q;
182
wire StateBackOff;
183
wire StateSFD;
184
wire StartTxRetry;
185
wire UnderRun;
186
wire TooBig;
187
wire [31:0] Crc;
188
wire CrcError;
189
wire [2:0] DlyCrcCnt;
190
wire [15:0] NibCnt;
191
wire NibCntEq7;
192
wire NibCntEq15;
193
wire NibbleMinFl;
194
wire ExcessiveDefer;
195
wire [15:0] ByteCnt;
196
wire MaxFrame;
197
wire RetryMax;
198
wire RandomEq0;
199
wire RandomEqByteCnt;
200
wire PacketFinished_d;
201
 
202
 
203
 
204
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
205
 
206
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
207
 
208
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
209
 
210
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
211
 
212
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
213
 
214
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
215
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
216
 
217
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
218
 
219
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
220
 
221
assign StateSFD = StatePreamble & NibCntEq15;
222
 
223
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
224
 
225
 
226
// StopExcessiveDeferOccured
227
always @ (posedge MTxClk or posedge Reset)
228
begin
229
  if(Reset)
230 403 julius
    StopExcessiveDeferOccured <=  1'b0;
231 6 julius
  else
232
    begin
233
      if(~TxStartFrm)
234 403 julius
        StopExcessiveDeferOccured <=  1'b0;
235 6 julius
      else
236
      if(ExcessiveDeferOccured)
237 403 julius
        StopExcessiveDeferOccured <=  1'b1;
238 6 julius
    end
239
end
240
 
241
 
242
// Collision Window
243
always @ (posedge MTxClk or posedge Reset)
244
begin
245
  if(Reset)
246 403 julius
    ColWindow <=  1'b1;
247 6 julius
  else
248
    begin
249
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
250 403 julius
        ColWindow <=  1'b0;
251 6 julius
      else
252
      if(StateIdle | StateIPG)
253 403 julius
        ColWindow <=  1'b1;
254 6 julius
    end
255
end
256
 
257
 
258
// Start Window
259
always @ (posedge MTxClk or posedge Reset)
260
begin
261
  if(Reset)
262 403 julius
    StatusLatch <=  1'b0;
263 6 julius
  else
264
    begin
265
      if(~TxStartFrm)
266 403 julius
        StatusLatch <=  1'b0;
267 6 julius
      else
268
      if(ExcessiveDeferOccured | StateIdle)
269 403 julius
        StatusLatch <=  1'b1;
270 6 julius
     end
271
end
272
 
273
 
274
// Transmit packet used data
275
always @ (posedge MTxClk or posedge Reset)
276
begin
277
  if(Reset)
278 403 julius
    TxUsedData <=  1'b0;
279 6 julius
  else
280 403 julius
    TxUsedData <=  |StartData;
281 6 julius
end
282
 
283
 
284
// Transmit packet done
285
always @ (posedge MTxClk or posedge Reset)
286
begin
287
  if(Reset)
288 403 julius
    TxDone <=  1'b0;
289 6 julius
  else
290
    begin
291
      if(TxStartFrm & ~StatusLatch)
292 403 julius
        TxDone <=  1'b0;
293 6 julius
      else
294
      if(StartTxDone)
295 403 julius
        TxDone <=  1'b1;
296 6 julius
    end
297
end
298
 
299
 
300
// Transmit packet retry
301
always @ (posedge MTxClk or posedge Reset)
302
begin
303
  if(Reset)
304 403 julius
    TxRetry <=  1'b0;
305 6 julius
  else
306
    begin
307
      if(TxStartFrm & ~StatusLatch)
308 403 julius
        TxRetry <=  1'b0;
309 6 julius
      else
310
      if(StartTxRetry)
311 403 julius
        TxRetry <=  1'b1;
312 6 julius
     end
313
end
314
 
315
 
316
// Transmit packet abort
317
always @ (posedge MTxClk or posedge Reset)
318
begin
319
  if(Reset)
320 403 julius
    TxAbort <=  1'b0;
321 6 julius
  else
322
    begin
323
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
324 403 julius
        TxAbort <=  1'b0;
325 6 julius
      else
326
      if(StartTxAbort)
327 403 julius
        TxAbort <=  1'b1;
328 6 julius
    end
329
end
330
 
331
 
332
// Retry counter
333
always @ (posedge MTxClk or posedge Reset)
334
begin
335
  if(Reset)
336 403 julius
    RetryCnt[3:0] <=  4'h0;
337 6 julius
  else
338
    begin
339
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
340
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
341 403 julius
        RetryCnt[3:0] <=  4'h0;
342 6 julius
      else
343
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
344 439 julius
        RetryCnt[3:0] <=  RetryCnt[3:0] + 1;
345 6 julius
    end
346
end
347
 
348
 
349
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
350
 
351
 
352
// Transmit nibble
353
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
354
          Crc or NibCntEq15)
355
begin
356
  if(StateData[0])
357
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
358
  else
359
  if(StateData[1])
360
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
361
  else
362
  if(StateFCS)
363
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
364
  else
365
  if(StateJam)
366
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
367
  else
368
  if(StatePreamble)
369
    if(NibCntEq15)
370
      MTxD_d[3:0] = 4'hd;                                       // SFD
371
    else
372
      MTxD_d[3:0] = 4'h5;                                       // Preamble
373
  else
374
    MTxD_d[3:0] = 4'h0;
375
end
376
 
377
 
378
// Transmit Enable
379
always @ (posedge MTxClk or posedge Reset)
380
begin
381
  if(Reset)
382 403 julius
    MTxEn <=  1'b0;
383 6 julius
  else
384 403 julius
    MTxEn <=  StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
385 6 julius
end
386
 
387
 
388
// Transmit nibble
389
always @ (posedge MTxClk or posedge Reset)
390
begin
391
  if(Reset)
392 403 julius
    MTxD[3:0] <=  4'h0;
393 6 julius
  else
394 403 julius
    MTxD[3:0] <=  MTxD_d[3:0];
395 6 julius
end
396
 
397
 
398
// Transmit error
399
always @ (posedge MTxClk or posedge Reset)
400
begin
401
  if(Reset)
402 403 julius
    MTxErr <=  1'b0;
403 6 julius
  else
404 403 julius
    MTxErr <=  TooBig | UnderRun;
405 6 julius
end
406
 
407
 
408
// WillTransmit
409
always @ (posedge MTxClk or posedge Reset)
410
begin
411
  if(Reset)
412 403 julius
    WillTransmit <=   1'b0;
413 6 julius
  else
414 403 julius
    WillTransmit <=  StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
415 6 julius
end
416
 
417
 
418
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
419
 
420
 
421
// Packet finished
422
always @ (posedge MTxClk or posedge Reset)
423
begin
424
  if(Reset)
425
    begin
426 403 julius
      PacketFinished <=  1'b0;
427
      PacketFinished_q  <=  1'b0;
428 6 julius
    end
429
  else
430
    begin
431 403 julius
      PacketFinished <=  PacketFinished_d;
432
      PacketFinished_q  <=  PacketFinished;
433 6 julius
    end
434
end
435
 
436
 
437
// Connecting module Counters
438
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
439
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
440
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
441
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
442
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
443
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
444
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
445
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
446
                            .DlyCrcCnt(DlyCrcCnt)
447
                           );
448
 
449
 
450
// Connecting module StateM
451
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
452
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
453
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
454
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
455
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
456
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
457
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
458
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
459
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
460
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
461
                        .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
462
                       );
463
 
464
 
465
wire Enable_Crc;
466
wire [3:0] Data_Crc;
467
wire Initialize_Crc;
468
 
469
assign Enable_Crc = ~StateFCS;
470
 
471
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
472
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
473
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
474
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
475
 
476
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
477
 
478
 
479
// Connecting module Crc
480
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
481
               .Crc(Crc), .CrcError(CrcError)
482
              );
483
 
484
 
485
// Connecting module Random
486
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
487
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
488
 
489
 
490
 
491
 
492
endmodule

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