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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 348 julius
////  http://opencores.org/project,or1k                           ////
7 6 julius
////                                                              ////
8
////  Description                                                 ////
9 348 julius
////  Defines for the OR1200 core                                 ////
10 6 julius
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_defines.v,v $
45 348 julius
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, bugs fixed. 
48 6 julius
 
49
//
50
// Dump VCD
51
//
52
//`define OR1200_VCD_DUMP
53
 
54
//
55
// Generate debug messages during simulation
56
//
57
//`define OR1200_VERBOSE
58
 
59
//  `define OR1200_ASIC
60
////////////////////////////////////////////////////////
61
//
62
// Typical configuration for an ASIC
63
//
64
`ifdef OR1200_ASIC
65
 
66
//
67
// Target ASIC memories
68
//
69
//`define OR1200_ARTISAN_SSP
70
//`define OR1200_ARTISAN_SDP
71
//`define OR1200_ARTISAN_STP
72
`define OR1200_VIRTUALSILICON_SSP
73
//`define OR1200_VIRTUALSILICON_STP_T1
74
//`define OR1200_VIRTUALSILICON_STP_T2
75
 
76
//
77
// Do not implement Data cache
78
//
79
//`define OR1200_NO_DC
80
 
81
//
82
// Do not implement Insn cache
83
//
84
//`define OR1200_NO_IC
85
 
86
//
87
// Do not implement Data MMU
88
//
89
//`define OR1200_NO_DMMU
90
 
91
//
92
// Do not implement Insn MMU
93
//
94
//`define OR1200_NO_IMMU
95
 
96
//
97
// Select between ASIC optimized and generic multiplier
98
//
99
//`define OR1200_ASIC_MULTP2_32X32
100
`define OR1200_GENERIC_MULTP2_32X32
101
 
102
//
103
// Size/type of insn/data cache if implemented
104
//
105
// `define OR1200_IC_1W_512B
106
// `define OR1200_IC_1W_4KB
107
`define OR1200_IC_1W_8KB
108
// `define OR1200_DC_1W_4KB
109
`define OR1200_DC_1W_8KB
110
 
111
`else
112
 
113
 
114
/////////////////////////////////////////////////////////
115
//
116
// Typical configuration for an FPGA
117
//
118
 
119
//
120
// Target FPGA memories
121
//
122
//`define OR1200_ALTERA_LPM
123
//`define OR1200_XILINX_RAMB16
124
//`define OR1200_XILINX_RAMB4
125
//`define OR1200_XILINX_RAM32X1D
126
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
127 348 julius
// Generic models should infer RAM blocks at synthesis time (not only effects 
128
// single port ram.)
129
`define OR1200_GENERIC
130 6 julius
 
131
//
132
// Do not implement Data cache
133
//
134 348 julius
//`define OR1200_NO_DC
135 6 julius
 
136
//
137
// Do not implement Insn cache
138
//
139
//`define OR1200_NO_IC
140
 
141
//
142
// Do not implement Data MMU
143
//
144
//`define OR1200_NO_DMMU
145
 
146
//
147
// Do not implement Insn MMU
148
//
149
//`define OR1200_NO_IMMU
150
 
151
//
152
// Select between ASIC and generic multiplier
153
//
154
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
155
//
156
//`define OR1200_ASIC_MULTP2_32X32
157
`define OR1200_GENERIC_MULTP2_32X32
158
 
159
//
160
// Size/type of insn/data cache if implemented
161
// (consider available FPGA memory resources)
162
//
163
//`define OR1200_IC_1W_512B
164 49 julius
//`define OR1200_IC_1W_4KB
165
`define OR1200_IC_1W_8KB
166 348 julius
//`define OR1200_DC_1W_4KB
167
`define OR1200_DC_1W_8KB
168 6 julius
 
169
`endif
170
 
171
 
172
//////////////////////////////////////////////////////////
173
//
174
// Do not change below unless you know what you are doing
175
//
176
 
177
//
178 358 julius
// Reset active low
179
//
180
//`define OR1200_RST_ACT_LOW
181
 
182
//
183 6 julius
// Enable RAM BIST
184
//
185
// At the moment this only works for Virtual Silicon
186
// single port RAMs. For other RAMs it has not effect.
187
// Special wrapper for VS RAMs needs to be provided
188
// with scan flops to facilitate bist scan.
189
//
190
//`define OR1200_BIST
191
 
192
//
193
// Register OR1200 WISHBONE outputs
194
// (must be defined/enabled)
195
//
196
`define OR1200_REGISTERED_OUTPUTS
197
 
198
//
199
// Register OR1200 WISHBONE inputs
200
//
201
// (must be undefined/disabled)
202
//
203
//`define OR1200_REGISTERED_INPUTS
204
 
205
//
206
// Disable bursts if they are not supported by the
207
// memory subsystem (only affect cache line fill)
208
//
209 348 julius
//`define OR1200_NO_BURSTS
210 6 julius
//
211
 
212
//
213
// WISHBONE retry counter range
214
//
215
// 2^value range for retry counter. Retry counter
216
// is activated whenever *wb_rty_i is asserted and
217
// until retry counter expires, corresponding
218
// WISHBONE interface is deactivated.
219
//
220
// To disable retry counters and *wb_rty_i all together,
221
// undefine this macro.
222
//
223
//`define OR1200_WB_RETRY 7
224
 
225
//
226
// WISHBONE Consecutive Address Burst
227
//
228
// This was used prior to WISHBONE B3 specification
229
// to identify bursts. It is no longer needed but
230
// remains enabled for compatibility with old designs.
231
//
232
// To remove *wb_cab_o ports undefine this macro.
233
//
234
//`define OR1200_WB_CAB
235
 
236
//
237
// WISHBONE B3 compatible interface
238
//
239
// This follows the WISHBONE B3 specification.
240
// It is not enabled by default because most
241
// designs still don't use WB b3.
242
//
243
// To enable *wb_cti_o/*wb_bte_o ports,
244
// define this macro.
245
//
246
`define OR1200_WB_B3
247
 
248
//
249
// LOG all WISHBONE accesses
250
//
251
`define OR1200_LOG_WB_ACCESS
252
 
253
//
254
// Enable additional synthesis directives if using
255
// _Synopsys_ synthesis tool
256
//
257
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
258
 
259
//
260
// Enables default statement in some case blocks
261
// and disables Synopsys synthesis directive full_case
262
//
263
// By default it is enabled. When disabled it
264
// can increase clock frequency.
265
//
266
`define OR1200_CASE_DEFAULT
267
 
268
//
269
// Operand width / register file address width
270
//
271
// (DO NOT CHANGE)
272
//
273
`define OR1200_OPERAND_WIDTH            32
274
`define OR1200_REGFILE_ADDR_WIDTH       5
275
 
276
//
277
// l.add/l.addi/l.and and optional l.addc/l.addic
278
// also set (compare) flag when result of their
279
// operation equals zero
280
//
281
// At the time of writing this, default or32
282
// C/C++ compiler doesn't generate code that
283
// would benefit from this optimization.
284
//
285
// By default this optimization is disabled to
286
// save area.
287
//
288
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
289
 
290
//
291
// Implement l.addc/l.addic instructions
292
//
293
// By default implementation of l.addc/l.addic
294
// instructions is enabled in case you need them.
295
// If you don't use them, then disable implementation
296
// to save area.
297
//
298 348 julius
//`define OR1200_IMPL_ADDC
299 6 julius
 
300
//
301 348 julius
// Implement l.sub instruction
302 6 julius
//
303 348 julius
// By default implementation of l.sub instructions
304
// is enabled to be compliant with the simulator.
305
// If you don't use carry bit, then disable
306
// implementation to save area.
307 6 julius
//
308 348 julius
`define OR1200_IMPL_SUB
309 6 julius
 
310
//
311 348 julius
// Implement carry bit SR[CY]
312 6 julius
//
313
//
314 348 julius
// By default implementation of SR[CY] is enabled
315
// to be compliant with the simulator. However SR[CY]
316
// is explicitly only used by l.addc/l.addic/l.sub
317
// instructions and if these three insns are not
318
// implemented there is not much point having SR[CY].
319 6 julius
//
320 348 julius
//`define OR1200_IMPL_CY
321 6 julius
 
322
//
323
// Implement rotate in the ALU
324
//
325
// At the time of writing this, or32
326
// C/C++ compiler doesn't generate rotate
327
// instructions. However or32 assembler
328
// can assemble code that uses rotate insn.
329
// This means that rotate instructions
330
// must be used manually inserted.
331
//
332
// By default implementation of rotate
333
// is disabled to save area and increase
334
// clock frequency.
335
//
336
//`define OR1200_IMPL_ALU_ROTATE
337
 
338
//
339
// Type of ALU compare to implement
340
//
341
// Try either one to find what yields
342
// higher clock frequencyin your case.
343
//
344
//`define OR1200_IMPL_ALU_COMP1
345
`define OR1200_IMPL_ALU_COMP2
346
 
347
//
348
// Implement multiplier
349
//
350
// By default multiplier is implemented
351
//
352
`define OR1200_MULT_IMPLEMENTED
353
 
354
//
355
// Implement multiply-and-accumulate
356
//
357
// By default MAC is implemented. To
358
// implement MAC, multiplier needs to be
359
// implemented.
360
//
361
`define OR1200_MAC_IMPLEMENTED
362
 
363
//
364 348 julius
// Implement optional l.div/l.divu instructions
365
//
366
// By default divide instructions are not implemented
367
// to save area and increase clock frequency. or32 C/C++
368
// compiler can use soft library for division.
369
//
370
// To implement divide, both multiplier and MAC needs to be implemented.
371
//
372
`define OR1200_DIV_IMPLEMENTED
373
 
374
//
375 6 julius
// Low power, slower multiplier
376
//
377
// Select between low-power (larger) multiplier
378
// and faster multiplier. The actual difference
379
// is only AND logic that prevents distribution
380
// of operands into the multiplier when instruction
381
// in execution is not multiply instruction
382
//
383
//`define OR1200_LOWPWR_MULT
384
 
385
//
386 58 julius
// Implement HW Single Precision FPU
387
//
388 348 julius
//`define OR1200_FPU_IMPLEMENTED
389
//
390 58 julius
 
391
//
392 6 julius
// Clock ratio RISC clock versus WB clock
393
//
394
// If you plan to run WB:RISC clock fixed to 1:1, disable
395
// both defines
396
//
397
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
398
// and use clmode to set ratio
399
//
400
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
401
// clmode to set ratio
402
//
403 348 julius
//`define OR1200_CLKDIV_2_SUPPORTED
404 6 julius
//`define OR1200_CLKDIV_4_SUPPORTED
405
 
406
//
407
// Type of register file RAM
408
//
409
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
410
//`define OR1200_RFRAM_TWOPORT
411
//
412 348 julius
// Memory macro dual port (see or1200_dpram.v)
413 6 julius
`define OR1200_RFRAM_DUALPORT
414
 
415
//
416
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
417
//`define OR1200_RFRAM_GENERIC
418
//  Generic register file supports - 16 registers 
419
`ifdef OR1200_RFRAM_GENERIC
420
//    `define OR1200_RFRAM_16REG
421
`endif
422
 
423
//
424
// Type of mem2reg aligner to implement.
425
//
426
// Once OR1200_IMPL_MEM2REG2 yielded faster
427
// circuit, however with today tools it will
428
// most probably give you slower circuit.
429
//
430
`define OR1200_IMPL_MEM2REG1
431
//`define OR1200_IMPL_MEM2REG2
432
 
433
//
434 358 julius
// Reset value and event
435
//
436
`ifdef OR1200_RST_ACT_LOW
437
  `define OR1200_RST_VALUE      (1'b0)
438
  `define OR1200_RST_EVENT      negedge
439
`else
440
  `define OR1200_RST_VALUE      (1'b1)
441
  `define OR1200_RST_EVENT      posedge
442
`endif
443
 
444
//
445 6 julius
// ALUOPs
446
//
447
`define OR1200_ALUOP_WIDTH      4
448
`define OR1200_ALUOP_NOP        4'd4
449
/* Order defined by arith insns that have two source operands both in regs
450
   (see binutils/include/opcode/or32.h) */
451
`define OR1200_ALUOP_ADD        4'd0
452
`define OR1200_ALUOP_ADDC       4'd1
453
`define OR1200_ALUOP_SUB        4'd2
454
`define OR1200_ALUOP_AND        4'd3
455
`define OR1200_ALUOP_OR         4'd4
456
`define OR1200_ALUOP_XOR        4'd5
457
`define OR1200_ALUOP_MUL        4'd6
458
`define OR1200_ALUOP_CUST5      4'd7
459
`define OR1200_ALUOP_SHROT      4'd8
460
`define OR1200_ALUOP_DIV        4'd9
461
`define OR1200_ALUOP_DIVU       4'd10
462
/* Order not specifically defined. */
463
`define OR1200_ALUOP_IMM        4'd11
464
`define OR1200_ALUOP_MOVHI      4'd12
465
`define OR1200_ALUOP_COMP       4'd13
466
`define OR1200_ALUOP_MTSR       4'd14
467
`define OR1200_ALUOP_MFSR       4'd15
468 348 julius
`define OR1200_ALUOP_CMOV       4'd14
469
`define OR1200_ALUOP_FF1        4'd15
470 6 julius
//
471
// MACOPs
472
//
473 348 julius
`define OR1200_MACOP_WIDTH      3
474
`define OR1200_MACOP_NOP        3'b000
475
`define OR1200_MACOP_MAC        3'b001
476
`define OR1200_MACOP_MSB        3'b010
477 6 julius
 
478
//
479
// Shift/rotate ops
480
//
481
`define OR1200_SHROTOP_WIDTH    2
482
`define OR1200_SHROTOP_NOP      2'd0
483
`define OR1200_SHROTOP_SLL      2'd0
484
`define OR1200_SHROTOP_SRL      2'd1
485
`define OR1200_SHROTOP_SRA      2'd2
486
`define OR1200_SHROTOP_ROR      2'd3
487
 
488
// Execution cycles per instruction
489 58 julius
`define OR1200_MULTICYCLE_WIDTH 3
490
`define OR1200_ONE_CYCLE                3'd0
491
`define OR1200_TWO_CYCLES               3'd1
492 6 julius
 
493 348 julius
// Execution control which will "wait on" a module to finish
494
`define OR1200_WAIT_ON_WIDTH 2
495
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
496
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
497
 
498 6 julius
// Operand MUX selects
499
`define OR1200_SEL_WIDTH                2
500
`define OR1200_SEL_RF                   2'd0
501
`define OR1200_SEL_IMM                  2'd1
502
`define OR1200_SEL_EX_FORW              2'd2
503
`define OR1200_SEL_WB_FORW              2'd3
504
 
505
//
506
// BRANCHOPs
507
//
508
`define OR1200_BRANCHOP_WIDTH           3
509
`define OR1200_BRANCHOP_NOP             3'd0
510
`define OR1200_BRANCHOP_J               3'd1
511
`define OR1200_BRANCHOP_JR              3'd2
512
`define OR1200_BRANCHOP_BAL             3'd3
513
`define OR1200_BRANCHOP_BF              3'd4
514
`define OR1200_BRANCHOP_BNF             3'd5
515
`define OR1200_BRANCHOP_RFE             3'd6
516
 
517
//
518
// LSUOPs
519
//
520
// Bit 0: sign extend
521
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
522
// Bit 3: 0 load, 1 store
523
`define OR1200_LSUOP_WIDTH              4
524
`define OR1200_LSUOP_NOP                4'b0000
525
`define OR1200_LSUOP_LBZ                4'b0010
526
`define OR1200_LSUOP_LBS                4'b0011
527
`define OR1200_LSUOP_LHZ                4'b0100
528
`define OR1200_LSUOP_LHS                4'b0101
529
`define OR1200_LSUOP_LWZ                4'b0110
530
`define OR1200_LSUOP_LWS                4'b0111
531 348 julius
`define OR1200_LSUOP_LD                 4'b0001
532
`define OR1200_LSUOP_SD                 4'b1000
533
`define OR1200_LSUOP_SB                 4'b1010
534
`define OR1200_LSUOP_SH                 4'b1100
535
`define OR1200_LSUOP_SW                 4'b1110
536 6 julius
 
537 348 julius
// Number of bits of load/store EA precalculated in ID stage
538
// for balancing ID and EX stages.
539
//
540
// Valid range: 2,3,...,30,31
541
`define OR1200_LSUEA_PRECALC            2
542
 
543 6 julius
// FETCHOPs
544
`define OR1200_FETCHOP_WIDTH            1
545
`define OR1200_FETCHOP_NOP              1'b0
546
`define OR1200_FETCHOP_LW               1'b1
547
 
548
//
549
// Register File Write-Back OPs
550
//
551
// Bit 0: register file write enable
552 58 julius
// Bits 3-1: write-back mux selects
553 348 julius
//
554 358 julius
`define OR1200_RFWBOP_WIDTH             4
555
`define OR1200_RFWBOP_NOP               4'b0000
556
`define OR1200_RFWBOP_ALU               3'b000
557
`define OR1200_RFWBOP_LSU               3'b001
558
`define OR1200_RFWBOP_SPRS              3'b010
559
`define OR1200_RFWBOP_LR                3'b011
560
`define OR1200_RFWBOP_FPU               3'b100
561 6 julius
 
562
// Compare instructions
563
`define OR1200_COP_SFEQ       3'b000
564
`define OR1200_COP_SFNE       3'b001
565
`define OR1200_COP_SFGT       3'b010
566
`define OR1200_COP_SFGE       3'b011
567
`define OR1200_COP_SFLT       3'b100
568
`define OR1200_COP_SFLE       3'b101
569
`define OR1200_COP_X          3'b111
570
`define OR1200_SIGNED_COMPARE 'd3
571
`define OR1200_COMPOP_WIDTH     4
572
 
573
//
574 348 julius
// FP OPs
575 58 julius
//
576
// MSbit indicates FPU operation valid
577
//
578 348 julius
`define OR1200_FPUOP_WIDTH      8
579
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
580
`define OR1200_FPUOP_CYCLES 3'd4
581
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
582
// implementation thus do not support double precision FP 
583
`define OR1200_FPUOP_DOUBLE_BIT 4
584
`define OR1200_FPUOP_ADD  8'b0000_0000
585
`define OR1200_FPUOP_SUB  8'b0000_0001
586
`define OR1200_FPUOP_MUL  8'b0000_0010
587
`define OR1200_FPUOP_DIV  8'b0000_0011
588
`define OR1200_FPUOP_ITOF 8'b0000_0100
589
`define OR1200_FPUOP_FTOI 8'b0000_0101
590
`define OR1200_FPUOP_REM  8'b0000_0110
591
`define OR1200_FPUOP_RESERVED  8'b0000_0111
592 58 julius
// FP Compare instructions
593 348 julius
`define OR1200_FPCOP_SFEQ 8'b0000_1000
594
`define OR1200_FPCOP_SFNE 8'b0000_1001
595
`define OR1200_FPCOP_SFGT 8'b0000_1010
596
`define OR1200_FPCOP_SFGE 8'b0000_1011
597
`define OR1200_FPCOP_SFLT 8'b0000_1100
598
`define OR1200_FPCOP_SFLE 8'b0000_1101
599 58 julius
 
600
//
601 6 julius
// TAGs for instruction bus
602
//
603
`define OR1200_ITAG_IDLE        4'h0    // idle bus
604
`define OR1200_ITAG_NI          4'h1    // normal insn
605
`define OR1200_ITAG_BE          4'hb    // Bus error exception
606
`define OR1200_ITAG_PE          4'hc    // Page fault exception
607
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
608
 
609
//
610
// TAGs for data bus
611
//
612
`define OR1200_DTAG_IDLE        4'h0    // idle bus
613
`define OR1200_DTAG_ND          4'h1    // normal data
614
`define OR1200_DTAG_AE          4'ha    // Alignment exception
615
`define OR1200_DTAG_BE          4'hb    // Bus error exception
616
`define OR1200_DTAG_PE          4'hc    // Page fault exception
617
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
618
 
619
 
620
//////////////////////////////////////////////
621
//
622
// ORBIS32 ISA specifics
623
//
624
 
625
// SHROT_OP position in machine word
626
`define OR1200_SHROTOP_POS              7:6
627
 
628
// ALU instructions multicycle field in machine word
629
`define OR1200_ALUMCYC_POS              9:8
630
 
631
//
632
// Instruction opcode groups (basic)
633
//
634
`define OR1200_OR32_J                 6'b000000
635
`define OR1200_OR32_JAL               6'b000001
636
`define OR1200_OR32_BNF               6'b000011
637
`define OR1200_OR32_BF                6'b000100
638
`define OR1200_OR32_NOP               6'b000101
639
`define OR1200_OR32_MOVHI             6'b000110
640
`define OR1200_OR32_XSYNC             6'b001000
641
`define OR1200_OR32_RFE               6'b001001
642
/* */
643
`define OR1200_OR32_JR                6'b010001
644
`define OR1200_OR32_JALR              6'b010010
645
`define OR1200_OR32_MACI              6'b010011
646
/* */
647
`define OR1200_OR32_LWZ               6'b100001
648
`define OR1200_OR32_LBZ               6'b100011
649
`define OR1200_OR32_LBS               6'b100100
650
`define OR1200_OR32_LHZ               6'b100101
651
`define OR1200_OR32_LHS               6'b100110
652
`define OR1200_OR32_ADDI              6'b100111
653
`define OR1200_OR32_ADDIC             6'b101000
654
`define OR1200_OR32_ANDI              6'b101001
655
`define OR1200_OR32_ORI               6'b101010
656
`define OR1200_OR32_XORI              6'b101011
657
`define OR1200_OR32_MULI              6'b101100
658
`define OR1200_OR32_MFSPR             6'b101101
659
`define OR1200_OR32_SH_ROTI           6'b101110
660
`define OR1200_OR32_SFXXI             6'b101111
661
/* */
662
`define OR1200_OR32_MTSPR             6'b110000
663
`define OR1200_OR32_MACMSB            6'b110001
664 348 julius
`define OR1200_OR32_FLOAT             6'b110010
665 6 julius
/* */
666
`define OR1200_OR32_SW                6'b110101
667
`define OR1200_OR32_SB                6'b110110
668
`define OR1200_OR32_SH                6'b110111
669
`define OR1200_OR32_ALU               6'b111000
670
`define OR1200_OR32_SFXX              6'b111001
671
//`define OR1200_OR32_CUST5             6'b111100
672
 
673 348 julius
 
674 6 julius
/////////////////////////////////////////////////////
675
//
676
// Exceptions
677
//
678
 
679
//
680
// Exception vectors per OR1K architecture:
681
// 0xPPPPP100 - reset
682
// 0xPPPPP200 - bus error
683
// ... etc
684
// where P represents exception prefix.
685
//
686
// Exception vectors can be customized as per
687
// the following formula:
688
// 0xPPPPPNVV - exception N
689
//
690
// P represents exception prefix
691
// N represents exception N
692
// VV represents length of the individual vector space,
693
//   usually it is 8 bits wide and starts with all bits zero
694
//
695
 
696
//
697
// PPPPP and VV parts
698
//
699
// Sum of these two defines needs to be 28
700
//
701
`define OR1200_EXCEPT_EPH0_P    20'h00000
702
`define OR1200_EXCEPT_EPH1_P    20'hF0000
703
`define OR1200_EXCEPT_V             8'h00
704
 
705
//
706
// N part width
707
//
708
`define OR1200_EXCEPT_WIDTH 4
709
 
710
//
711
// Definition of exception vectors
712
//
713
// To avoid implementation of a certain exception,
714
// simply comment out corresponding line
715
//
716
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
717
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
718 58 julius
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
719 6 julius
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
720
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
721
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
722
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
723
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
724
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
725
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
726
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
727
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
728
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
729
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
730
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
731
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
732
 
733
 
734
/////////////////////////////////////////////////////
735
//
736
// SPR groups
737
//
738
 
739
// Bits that define the group
740
`define OR1200_SPR_GROUP_BITS   15:11
741
 
742
// Width of the group bits
743
`define OR1200_SPR_GROUP_WIDTH  5
744
 
745
// Bits that define offset inside the group
746
`define OR1200_SPR_OFS_BITS 10:0
747
 
748
// List of groups
749
`define OR1200_SPR_GROUP_SYS    5'd00
750
`define OR1200_SPR_GROUP_DMMU   5'd01
751
`define OR1200_SPR_GROUP_IMMU   5'd02
752
`define OR1200_SPR_GROUP_DC     5'd03
753
`define OR1200_SPR_GROUP_IC     5'd04
754
`define OR1200_SPR_GROUP_MAC    5'd05
755
`define OR1200_SPR_GROUP_DU     5'd06
756
`define OR1200_SPR_GROUP_PM     5'd08
757
`define OR1200_SPR_GROUP_PIC    5'd09
758
`define OR1200_SPR_GROUP_TT     5'd10
759 348 julius
`define OR1200_SPR_GROUP_FPU    5'd11
760 6 julius
 
761
/////////////////////////////////////////////////////
762
//
763
// System group
764
//
765
 
766
//
767
// System registers
768
//
769
`define OR1200_SPR_CFGR         7'd0
770
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
771
`define OR1200_SPR_NPC          11'd16
772
`define OR1200_SPR_SR           11'd17
773
`define OR1200_SPR_PPC          11'd18
774 348 julius
`define OR1200_SPR_FPCSR        11'd20
775 6 julius
`define OR1200_SPR_EPCR         11'd32
776
`define OR1200_SPR_EEAR         11'd48
777
`define OR1200_SPR_ESR          11'd64
778
 
779
//
780
// SR bits
781
//
782 348 julius
`define OR1200_SR_WIDTH 17
783 6 julius
`define OR1200_SR_SM   0
784
`define OR1200_SR_TEE  1
785
`define OR1200_SR_IEE  2
786
`define OR1200_SR_DCE  3
787
`define OR1200_SR_ICE  4
788
`define OR1200_SR_DME  5
789
`define OR1200_SR_IME  6
790
`define OR1200_SR_LEE  7
791
`define OR1200_SR_CE   8
792
`define OR1200_SR_F    9
793
`define OR1200_SR_CY   10       // Unused
794
`define OR1200_SR_OV   11       // Unused
795
`define OR1200_SR_OVE  12       // Unused
796
`define OR1200_SR_DSX  13       // Unused
797
`define OR1200_SR_EPH  14
798
`define OR1200_SR_FO   15
799 348 julius
`define OR1200_SR_TED  16
800 6 julius
`define OR1200_SR_CID  31:28    // Unimplemented
801
 
802
//
803
// Bits that define offset inside the group
804
//
805
`define OR1200_SPROFS_BITS 10:0
806
 
807
//
808
// Default Exception Prefix
809
//
810
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
811
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
812
//
813
`define OR1200_SR_EPH_DEF       1'b0
814
 
815 348 julius
 
816 58 julius
//
817
// FPCSR bits
818
//
819
`define OR1200_FPCSR_WIDTH 12
820
`define OR1200_FPCSR_FPEE  0
821
`define OR1200_FPCSR_RM    2:1
822
`define OR1200_FPCSR_OVF   3
823
`define OR1200_FPCSR_UNF   4
824
`define OR1200_FPCSR_SNF   5
825
`define OR1200_FPCSR_QNF   6
826
`define OR1200_FPCSR_ZF    7
827
`define OR1200_FPCSR_IXF   8
828
`define OR1200_FPCSR_IVF   9
829
`define OR1200_FPCSR_INF   10
830
`define OR1200_FPCSR_DZF   11
831
`define OR1200_FPCSR_RES   31:12
832
 
833 6 julius
/////////////////////////////////////////////////////
834
//
835
// Power Management (PM)
836
//
837
 
838
// Define it if you want PM implemented
839
//`define OR1200_PM_IMPLEMENTED
840
 
841
// Bit positions inside PMR (don't change)
842
`define OR1200_PM_PMR_SDF 3:0
843
`define OR1200_PM_PMR_DME 4
844
`define OR1200_PM_PMR_SME 5
845
`define OR1200_PM_PMR_DCGE 6
846
`define OR1200_PM_PMR_UNUSED 31:7
847
 
848
// PMR offset inside PM group of registers
849
`define OR1200_PM_OFS_PMR 11'b0
850
 
851
// PM group
852
`define OR1200_SPRGRP_PM 5'd8
853
 
854
// Define if PMR can be read/written at any address inside PM group
855
`define OR1200_PM_PARTIAL_DECODING
856
 
857
// Define if reading PMR is allowed
858
`define OR1200_PM_READREGS
859
 
860
// Define if unused PMR bits should be zero
861
`define OR1200_PM_UNUSED_ZERO
862
 
863
 
864
/////////////////////////////////////////////////////
865
//
866
// Debug Unit (DU)
867
//
868
 
869
// Define it if you want DU implemented
870 363 julius
//`define OR1200_DU_IMPLEMENTED
871 6 julius
 
872
//
873
// Define if you want HW Breakpoints
874
// (if HW breakpoints are not implemented
875
// only default software trapping is
876
// possible with l.trap insn - this is
877
// however already enough for use
878
// with or32 gdb)
879
//
880 348 julius
//`define OR1200_DU_HWBKPTS
881 6 julius
 
882 348 julius
// Number of DVR/DCR pairs if HW breakpoints enabled
883
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
884
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
885
`define OR1200_DU_DVRDCR_PAIRS 8
886 6 julius
 
887
// Define if you want trace buffer
888 348 julius
//      (for now only available for Xilinx Virtex FPGAs)
889 6 julius
//`define OR1200_DU_TB_IMPLEMENTED
890
 
891 348 julius
 
892 6 julius
//
893
// Address offsets of DU registers inside DU group
894
//
895
// To not implement a register, doq not define its address
896
//
897
`ifdef OR1200_DU_HWBKPTS
898
`define OR1200_DU_DVR0          11'd0
899
`define OR1200_DU_DVR1          11'd1
900
`define OR1200_DU_DVR2          11'd2
901
`define OR1200_DU_DVR3          11'd3
902
`define OR1200_DU_DVR4          11'd4
903
`define OR1200_DU_DVR5          11'd5
904
`define OR1200_DU_DVR6          11'd6
905
`define OR1200_DU_DVR7          11'd7
906
`define OR1200_DU_DCR0          11'd8
907
`define OR1200_DU_DCR1          11'd9
908
`define OR1200_DU_DCR2          11'd10
909
`define OR1200_DU_DCR3          11'd11
910
`define OR1200_DU_DCR4          11'd12
911
`define OR1200_DU_DCR5          11'd13
912
`define OR1200_DU_DCR6          11'd14
913
`define OR1200_DU_DCR7          11'd15
914
`endif
915
`define OR1200_DU_DMR1          11'd16
916
`ifdef OR1200_DU_HWBKPTS
917
`define OR1200_DU_DMR2          11'd17
918
`define OR1200_DU_DWCR0         11'd18
919
`define OR1200_DU_DWCR1         11'd19
920
`endif
921
`define OR1200_DU_DSR           11'd20
922
`define OR1200_DU_DRR           11'd21
923
`ifdef OR1200_DU_TB_IMPLEMENTED
924
`define OR1200_DU_TBADR         11'h0ff
925 363 julius
`define OR1200_DU_TBIA          11'h1??
926
`define OR1200_DU_TBIM          11'h2??
927
`define OR1200_DU_TBAR          11'h3??
928
`define OR1200_DU_TBTS          11'h4??
929 6 julius
`endif
930
 
931
// Position of offset bits inside SPR address
932
`define OR1200_DUOFS_BITS       10:0
933
 
934
// DCR bits
935
`define OR1200_DU_DCR_DP        0
936
`define OR1200_DU_DCR_CC        3:1
937
`define OR1200_DU_DCR_SC        4
938
`define OR1200_DU_DCR_CT        7:5
939
 
940
// DMR1 bits
941
`define OR1200_DU_DMR1_CW0      1:0
942
`define OR1200_DU_DMR1_CW1      3:2
943
`define OR1200_DU_DMR1_CW2      5:4
944
`define OR1200_DU_DMR1_CW3      7:6
945
`define OR1200_DU_DMR1_CW4      9:8
946
`define OR1200_DU_DMR1_CW5      11:10
947
`define OR1200_DU_DMR1_CW6      13:12
948
`define OR1200_DU_DMR1_CW7      15:14
949
`define OR1200_DU_DMR1_CW8      17:16
950
`define OR1200_DU_DMR1_CW9      19:18
951
`define OR1200_DU_DMR1_CW10     21:20
952
`define OR1200_DU_DMR1_ST       22
953
`define OR1200_DU_DMR1_BT       23
954
`define OR1200_DU_DMR1_DXFW     24
955
`define OR1200_DU_DMR1_ETE      25
956
 
957
// DMR2 bits
958
`define OR1200_DU_DMR2_WCE0     0
959
`define OR1200_DU_DMR2_WCE1     1
960 348 julius
`define OR1200_DU_DMR2_AWTC     12:2
961
`define OR1200_DU_DMR2_WGB      23:13
962 6 julius
 
963
// DWCR bits
964
`define OR1200_DU_DWCR_COUNT    15:0
965
`define OR1200_DU_DWCR_MATCH    31:16
966
 
967
// DSR bits
968
`define OR1200_DU_DSR_WIDTH     14
969
`define OR1200_DU_DSR_RSTE      0
970
`define OR1200_DU_DSR_BUSEE     1
971
`define OR1200_DU_DSR_DPFE      2
972
`define OR1200_DU_DSR_IPFE      3
973
`define OR1200_DU_DSR_TTE       4
974
`define OR1200_DU_DSR_AE        5
975
`define OR1200_DU_DSR_IIE       6
976
`define OR1200_DU_DSR_IE        7
977
`define OR1200_DU_DSR_DME       8
978
`define OR1200_DU_DSR_IME       9
979
`define OR1200_DU_DSR_RE        10
980
`define OR1200_DU_DSR_SCE       11
981 58 julius
`define OR1200_DU_DSR_FPE       12
982 6 julius
`define OR1200_DU_DSR_TE        13
983
 
984
// DRR bits
985
`define OR1200_DU_DRR_RSTE      0
986
`define OR1200_DU_DRR_BUSEE     1
987
`define OR1200_DU_DRR_DPFE      2
988
`define OR1200_DU_DRR_IPFE      3
989
`define OR1200_DU_DRR_TTE       4
990
`define OR1200_DU_DRR_AE        5
991
`define OR1200_DU_DRR_IIE       6
992
`define OR1200_DU_DRR_IE        7
993
`define OR1200_DU_DRR_DME       8
994
`define OR1200_DU_DRR_IME       9
995
`define OR1200_DU_DRR_RE        10
996
`define OR1200_DU_DRR_SCE       11
997 58 julius
`define OR1200_DU_DRR_FPE       12
998 6 julius
`define OR1200_DU_DRR_TE        13
999
 
1000
// Define if reading DU regs is allowed
1001
`define OR1200_DU_READREGS
1002
 
1003
// Define if unused DU registers bits should be zero
1004
`define OR1200_DU_UNUSED_ZERO
1005
 
1006
// Define if IF/LSU status is not needed by devel i/f
1007
`define OR1200_DU_STATUS_UNIMPLEMENTED
1008
 
1009
/////////////////////////////////////////////////////
1010
//
1011
// Programmable Interrupt Controller (PIC)
1012
//
1013
 
1014
// Define it if you want PIC implemented
1015
`define OR1200_PIC_IMPLEMENTED
1016
 
1017
// Define number of interrupt inputs (2-31)
1018
`define OR1200_PIC_INTS 20
1019
 
1020
// Address offsets of PIC registers inside PIC group
1021
`define OR1200_PIC_OFS_PICMR 2'd0
1022
`define OR1200_PIC_OFS_PICSR 2'd2
1023
 
1024
// Position of offset bits inside SPR address
1025
`define OR1200_PICOFS_BITS 1:0
1026
 
1027
// Define if you want these PIC registers to be implemented
1028
`define OR1200_PIC_PICMR
1029
`define OR1200_PIC_PICSR
1030
 
1031
// Define if reading PIC registers is allowed
1032
`define OR1200_PIC_READREGS
1033
 
1034
// Define if unused PIC register bits should be zero
1035
`define OR1200_PIC_UNUSED_ZERO
1036
 
1037
 
1038
/////////////////////////////////////////////////////
1039
//
1040
// Tick Timer (TT)
1041
//
1042
 
1043
// Define it if you want TT implemented
1044
`define OR1200_TT_IMPLEMENTED
1045
 
1046
// Address offsets of TT registers inside TT group
1047
`define OR1200_TT_OFS_TTMR 1'd0
1048
`define OR1200_TT_OFS_TTCR 1'd1
1049
 
1050
// Position of offset bits inside SPR group
1051
`define OR1200_TTOFS_BITS 0
1052
 
1053
// Define if you want these TT registers to be implemented
1054
`define OR1200_TT_TTMR
1055
`define OR1200_TT_TTCR
1056
 
1057
// TTMR bits
1058
`define OR1200_TT_TTMR_TP 27:0
1059
`define OR1200_TT_TTMR_IP 28
1060
`define OR1200_TT_TTMR_IE 29
1061
`define OR1200_TT_TTMR_M 31:30
1062
 
1063
// Define if reading TT registers is allowed
1064
`define OR1200_TT_READREGS
1065
 
1066
 
1067
//////////////////////////////////////////////
1068
//
1069
// MAC
1070
//
1071
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1072
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1073
 
1074
//
1075
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1076
//
1077
// According to architecture manual there is no shift, so default value is 0.
1078 356 julius
// However the implementation has deviated in this from the arch manual and had
1079
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
1080
// (if using libmad fixed point library). Shifts are no longer default setup, 
1081
// but if you need to remain backward compatible, define your shift bits, which
1082
// were normally
1083 6 julius
// dest_GPR = {MACHI,MACLO}[59:28]
1084
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1085
 
1086
 
1087
//////////////////////////////////////////////
1088
//
1089
// Data MMU (DMMU)
1090
//
1091
 
1092
//
1093
// Address that selects between TLB TR and MR
1094
//
1095
`define OR1200_DTLB_TM_ADDR     7
1096
 
1097
//
1098
// DTLBMR fields
1099
//
1100
`define OR1200_DTLBMR_V_BITS    0
1101
`define OR1200_DTLBMR_CID_BITS  4:1
1102
`define OR1200_DTLBMR_RES_BITS  11:5
1103
`define OR1200_DTLBMR_VPN_BITS  31:13
1104
 
1105
//
1106
// DTLBTR fields
1107
//
1108
`define OR1200_DTLBTR_CC_BITS   0
1109
`define OR1200_DTLBTR_CI_BITS   1
1110
`define OR1200_DTLBTR_WBC_BITS  2
1111
`define OR1200_DTLBTR_WOM_BITS  3
1112
`define OR1200_DTLBTR_A_BITS    4
1113
`define OR1200_DTLBTR_D_BITS    5
1114
`define OR1200_DTLBTR_URE_BITS  6
1115
`define OR1200_DTLBTR_UWE_BITS  7
1116
`define OR1200_DTLBTR_SRE_BITS  8
1117
`define OR1200_DTLBTR_SWE_BITS  9
1118
`define OR1200_DTLBTR_RES_BITS  11:10
1119
`define OR1200_DTLBTR_PPN_BITS  31:13
1120
 
1121
//
1122
// DTLB configuration
1123
//
1124
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1125
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1126
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1127
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1128
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1129
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1130
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1131
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1132
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1133
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1134
 
1135
//
1136
// Cache inhibit while DMMU is not enabled/implemented
1137
//
1138
// cache inhibited 0GB-4GB              1'b1
1139
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1140
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1141
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1142
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1143
// cached 0GB-4GB                       1'b0
1144
//
1145 348 julius
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1146 6 julius
 
1147
 
1148
//////////////////////////////////////////////
1149
//
1150
// Insn MMU (IMMU)
1151
//
1152
 
1153
//
1154
// Address that selects between TLB TR and MR
1155
//
1156
`define OR1200_ITLB_TM_ADDR     7
1157
 
1158
//
1159
// ITLBMR fields
1160
//
1161
`define OR1200_ITLBMR_V_BITS    0
1162
`define OR1200_ITLBMR_CID_BITS  4:1
1163
`define OR1200_ITLBMR_RES_BITS  11:5
1164
`define OR1200_ITLBMR_VPN_BITS  31:13
1165
 
1166
//
1167
// ITLBTR fields
1168
//
1169
`define OR1200_ITLBTR_CC_BITS   0
1170
`define OR1200_ITLBTR_CI_BITS   1
1171
`define OR1200_ITLBTR_WBC_BITS  2
1172
`define OR1200_ITLBTR_WOM_BITS  3
1173
`define OR1200_ITLBTR_A_BITS    4
1174
`define OR1200_ITLBTR_D_BITS    5
1175
`define OR1200_ITLBTR_SXE_BITS  6
1176
`define OR1200_ITLBTR_UXE_BITS  7
1177
`define OR1200_ITLBTR_RES_BITS  11:8
1178
`define OR1200_ITLBTR_PPN_BITS  31:13
1179
 
1180
//
1181
// ITLB configuration
1182
//
1183
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1184
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1185
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1186
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1187
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1188
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1189
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1190
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1191
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1192
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1193
 
1194
//
1195
// Cache inhibit while IMMU is not enabled/implemented
1196
// Note: all combinations that use icpu_adr_i cause async loop
1197
//
1198
// cache inhibited 0GB-4GB              1'b1
1199
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1200
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1201
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1202
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1203
// cached 0GB-4GB                       1'b0
1204
//
1205
`define OR1200_IMMU_CI                  1'b0
1206
 
1207
 
1208
/////////////////////////////////////////////////
1209
//
1210
// Insn cache (IC)
1211
//
1212
 
1213
// 3 for 8 bytes, 4 for 16 bytes etc
1214
`define OR1200_ICLS             4
1215
 
1216
//
1217
// IC configurations
1218
//
1219
`ifdef OR1200_IC_1W_512B
1220
`define OR1200_ICSIZE   9     // 512
1221
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1222
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1223
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1224
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1225
`define OR1200_ICTAG_W  24
1226
`endif
1227
`ifdef OR1200_IC_1W_4KB
1228
`define OR1200_ICSIZE                   12                      // 4096
1229
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1230
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1231
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1232
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1233
`define OR1200_ICTAG_W                  21
1234
`endif
1235
`ifdef OR1200_IC_1W_8KB
1236
`define OR1200_ICSIZE                   13                      // 8192
1237
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1238
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1239
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1240
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1241
`define OR1200_ICTAG_W                  20
1242
`endif
1243
 
1244
 
1245
/////////////////////////////////////////////////
1246
//
1247
// Data cache (DC)
1248
//
1249
 
1250
// 3 for 8 bytes, 4 for 16 bytes etc
1251
`define OR1200_DCLS             4
1252
 
1253 348 julius
// Define to enable default behavior of cache as write through
1254
// Turning this off enabled write back statergy
1255
//
1256
`define OR1200_DC_WRITETHROUGH
1257 6 julius
 
1258 348 julius
// Define to enable stores from the stack not doing writethrough.
1259
// EXPERIMENTAL
1260
//`define OR1200_DC_NOSTACKWRITETHROUGH
1261
 
1262
// Data cache SPR definitions
1263
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
1264
// Data cache group SPR addresses
1265
`define OR1200_SPRGRP_DC_DCCR           3'd0 // Not implemented
1266
`define OR1200_SPRGRP_DC_DCBPR          3'd1 // Not implemented
1267
`define OR1200_SPRGRP_DC_DCBFR          3'd2
1268
`define OR1200_SPRGRP_DC_DCBIR          3'd3
1269
`define OR1200_SPRGRP_DC_DCBWR          3'd4 // Not implemented
1270
`define OR1200_SPRGRP_DC_DCBLR          3'd5 // Not implemented
1271
 
1272 6 julius
//
1273
// DC configurations
1274
//
1275
`ifdef OR1200_DC_1W_4KB
1276
`define OR1200_DCSIZE                   12                      // 4096
1277
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1278
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1279
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1280
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1281
`define OR1200_DCTAG_W                  21
1282
`endif
1283
`ifdef OR1200_DC_1W_8KB
1284
`define OR1200_DCSIZE                   13                      // 8192
1285
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1286
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1287
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1288
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1289
`define OR1200_DCTAG_W                  20
1290
`endif
1291
 
1292 348 julius
 
1293 6 julius
/////////////////////////////////////////////////
1294
//
1295
// Store buffer (SB)
1296
//
1297
 
1298
//
1299
// Store buffer
1300
//
1301
// It will improve performance by "caching" CPU stores
1302
// using store buffer. This is most important for function
1303
// prologues because DC can only work in write though mode
1304
// and all stores would have to complete external WB writes
1305
// to memory.
1306
// Store buffer is between DC and data BIU.
1307
// All stores will be stored into store buffer and immediately
1308
// completed by the CPU, even though actual external writes
1309
// will be performed later. As a consequence store buffer masks
1310
// all data bus errors related to stores (data bus errors
1311
// related to loads are delivered normally).
1312
// All pending CPU loads will wait until store buffer is empty to
1313
// ensure strict memory model. Right now this is necessary because
1314
// we don't make destinction between cached and cache inhibited
1315
// address space, so we simply empty store buffer until loads
1316
// can begin.
1317
//
1318
// It makes design a bit bigger, depending what is the number of
1319
// entries in SB FIFO. Number of entries can be changed further
1320
// down.
1321
//
1322
//`define OR1200_SB_IMPLEMENTED
1323
 
1324
//
1325
// Number of store buffer entries
1326
//
1327
// Verified number of entries are 4 and 8 entries
1328
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1329
// always match 2**OR1200_SB_LOG.
1330
// To disable store buffer, undefine
1331
// OR1200_SB_IMPLEMENTED.
1332
//
1333
`define OR1200_SB_LOG           2       // 2 or 3
1334
`define OR1200_SB_ENTRIES       4       // 4 or 8
1335
 
1336
 
1337
/////////////////////////////////////////////////
1338
//
1339
// Quick Embedded Memory (QMEM)
1340
//
1341
 
1342
//
1343
// Quick Embedded Memory
1344
//
1345
// Instantiation of dedicated insn/data memory (RAM or ROM).
1346
// Insn fetch has effective throughput 1insn / clock cycle.
1347
// Data load takes two clock cycles / access, data store
1348
// takes 1 clock cycle / access (if there is no insn fetch)).
1349
// Memory instantiation is shared between insn and data,
1350
// meaning if insn fetch are performed, data load/store
1351
// performance will be lower.
1352
//
1353
// Main reason for QMEM is to put some time critical functions
1354
// into this memory and to have predictable and fast access
1355
// to these functions. (soft fpu, context switch, exception
1356
// handlers, stack, etc)
1357
//
1358
// It makes design a bit bigger and slower. QMEM sits behind
1359
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1360
// used with QMEM and QMEM is seen by the CPU just like any other
1361
// memory in the system). IC/DC are sitting behind QMEM so the
1362
// whole design timing might be worse with QMEM implemented.
1363
//
1364
//`define OR1200_QMEM_IMPLEMENTED
1365
 
1366
//
1367
// Base address and mask of QMEM
1368
//
1369
// Base address defines first address of QMEM. Mask defines
1370
// QMEM range in address space. Actual size of QMEM is however
1371
// determined with instantiated RAM/ROM. However bigger
1372
// mask will reserve more address space for QMEM, but also
1373
// make design faster, while more tight mask will take
1374
// less address space but also make design slower. If
1375
// instantiated RAM/ROM is smaller than space reserved with
1376
// the mask, instatiated RAM/ROM will also be shadowed
1377
// at higher addresses in reserved space.
1378
//
1379
`define OR1200_QMEM_IADDR       32'h0080_0000
1380 348 julius
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1381
`define OR1200_QMEM_DADDR       32'h0080_0000
1382
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1383 6 julius
 
1384
//
1385
// QMEM interface byte-select capability
1386
//
1387
// To enable qmem_sel* ports, define this macro.
1388
//
1389
//`define OR1200_QMEM_BSEL
1390
 
1391
//
1392
// QMEM interface acknowledge
1393
//
1394
// To enable qmem_ack port, define this macro.
1395
//
1396
//`define OR1200_QMEM_ACK
1397
 
1398
/////////////////////////////////////////////////////
1399
//
1400
// VR, UPR and Configuration Registers
1401
//
1402
//
1403
// VR, UPR and configuration registers are optional. If 
1404
// implemented, operating system can automatically figure
1405
// out how to use the processor because it knows 
1406
// what units are available in the processor and how they
1407
// are configured.
1408
//
1409
// This section must be last in or1200_defines.v file so
1410
// that all units are already configured and thus
1411
// configuration registers are properly set.
1412
// 
1413
 
1414
// Define if you want configuration registers implemented
1415
`define OR1200_CFGR_IMPLEMENTED
1416
 
1417
// Define if you want full address decode inside SYS group
1418
`define OR1200_SYS_FULL_DECODE
1419
 
1420
// Offsets of VR, UPR and CFGR registers
1421
`define OR1200_SPRGRP_SYS_VR            4'h0
1422
`define OR1200_SPRGRP_SYS_UPR           4'h1
1423
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1424
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1425
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1426
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1427
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1428
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1429
 
1430
// VR fields
1431
`define OR1200_VR_REV_BITS              5:0
1432
`define OR1200_VR_RES1_BITS             15:6
1433
`define OR1200_VR_CFG_BITS              23:16
1434
`define OR1200_VR_VER_BITS              31:24
1435
 
1436
// VR values
1437 348 julius
`define OR1200_VR_REV                   6'h08
1438 6 julius
`define OR1200_VR_RES1                  10'h000
1439
`define OR1200_VR_CFG                   8'h00
1440
`define OR1200_VR_VER                   8'h12
1441
 
1442
// UPR fields
1443
`define OR1200_UPR_UP_BITS              0
1444
`define OR1200_UPR_DCP_BITS             1
1445
`define OR1200_UPR_ICP_BITS             2
1446
`define OR1200_UPR_DMP_BITS             3
1447
`define OR1200_UPR_IMP_BITS             4
1448
`define OR1200_UPR_MP_BITS              5
1449
`define OR1200_UPR_DUP_BITS             6
1450
`define OR1200_UPR_PCUP_BITS            7
1451
`define OR1200_UPR_PMP_BITS             8
1452
`define OR1200_UPR_PICP_BITS            9
1453
`define OR1200_UPR_TTP_BITS             10
1454 348 julius
`define OR1200_UPR_FPP_BITS             11
1455
`define OR1200_UPR_RES1_BITS            23:12
1456 6 julius
`define OR1200_UPR_CUP_BITS             31:24
1457
 
1458
// UPR values
1459
`define OR1200_UPR_UP                   1'b1
1460
`ifdef OR1200_NO_DC
1461
`define OR1200_UPR_DCP                  1'b0
1462
`else
1463
`define OR1200_UPR_DCP                  1'b1
1464
`endif
1465
`ifdef OR1200_NO_IC
1466
`define OR1200_UPR_ICP                  1'b0
1467
`else
1468
`define OR1200_UPR_ICP                  1'b1
1469
`endif
1470
`ifdef OR1200_NO_DMMU
1471
`define OR1200_UPR_DMP                  1'b0
1472
`else
1473
`define OR1200_UPR_DMP                  1'b1
1474
`endif
1475
`ifdef OR1200_NO_IMMU
1476
`define OR1200_UPR_IMP                  1'b0
1477
`else
1478
`define OR1200_UPR_IMP                  1'b1
1479
`endif
1480 348 julius
`ifdef OR1200_MAC_IMPLEMENTED
1481
`define OR1200_UPR_MP                   1'b1
1482
`else
1483
`define OR1200_UPR_MP                   1'b0
1484
`endif
1485 6 julius
`ifdef OR1200_DU_IMPLEMENTED
1486
`define OR1200_UPR_DUP                  1'b1
1487
`else
1488
`define OR1200_UPR_DUP                  1'b0
1489
`endif
1490
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1491 348 julius
`ifdef OR1200_PM_IMPLEMENTED
1492 6 julius
`define OR1200_UPR_PMP                  1'b1
1493
`else
1494
`define OR1200_UPR_PMP                  1'b0
1495
`endif
1496 348 julius
`ifdef OR1200_PIC_IMPLEMENTED
1497 6 julius
`define OR1200_UPR_PICP                 1'b1
1498
`else
1499
`define OR1200_UPR_PICP                 1'b0
1500
`endif
1501 348 julius
`ifdef OR1200_TT_IMPLEMENTED
1502 6 julius
`define OR1200_UPR_TTP                  1'b1
1503
`else
1504
`define OR1200_UPR_TTP                  1'b0
1505
`endif
1506 348 julius
`ifdef OR1200_FPU_IMPLEMENTED
1507
`define OR1200_UPR_FPP                  1'b1
1508
`else
1509
`define OR1200_UPR_FPP                  1'b0
1510
`endif
1511
`define OR1200_UPR_RES1                 12'h000
1512 6 julius
`define OR1200_UPR_CUP                  8'h00
1513
 
1514
// CPUCFGR fields
1515
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1516
`define OR1200_CPUCFGR_HGF_BITS     4
1517
`define OR1200_CPUCFGR_OB32S_BITS       5
1518
`define OR1200_CPUCFGR_OB64S_BITS       6
1519
`define OR1200_CPUCFGR_OF32S_BITS       7
1520
`define OR1200_CPUCFGR_OF64S_BITS       8
1521
`define OR1200_CPUCFGR_OV64S_BITS       9
1522
`define OR1200_CPUCFGR_RES1_BITS        31:10
1523
 
1524
// CPUCFGR values
1525
`define OR1200_CPUCFGR_NSGF                 4'h0
1526
`ifdef OR1200_RFRAM_16REG
1527
    `define OR1200_CPUCFGR_HGF                  1'b1
1528
`else
1529
    `define OR1200_CPUCFGR_HGF                  1'b0
1530
`endif
1531
`define OR1200_CPUCFGR_OB32S            1'b1
1532
`define OR1200_CPUCFGR_OB64S            1'b0
1533 348 julius
`ifdef OR1200_FPU_IMPLEMENTED
1534
 `define OR1200_CPUCFGR_OF32S           1'b1
1535
`else
1536
 `define OR1200_CPUCFGR_OF32S           1'b0
1537
`endif
1538
 
1539 6 julius
`define OR1200_CPUCFGR_OF64S            1'b0
1540
`define OR1200_CPUCFGR_OV64S            1'b0
1541
`define OR1200_CPUCFGR_RES1             22'h000000
1542
 
1543
// DMMUCFGR fields
1544
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1545
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1546
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1547
`define OR1200_DMMUCFGR_CRI_BITS        8
1548
`define OR1200_DMMUCFGR_PRI_BITS        9
1549
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1550
`define OR1200_DMMUCFGR_HTR_BITS        11
1551
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1552
 
1553
// DMMUCFGR values
1554
`ifdef OR1200_NO_DMMU
1555
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1556
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1557
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1558
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1559
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1560
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1561
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1562
`define OR1200_DMMUCFGR_RES1            20'h00000
1563
`else
1564
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1565
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1566
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1567
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1568
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1569
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1570
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1571
`define OR1200_DMMUCFGR_RES1            20'h00000
1572
`endif
1573
 
1574
// IMMUCFGR fields
1575
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1576
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1577
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1578
`define OR1200_IMMUCFGR_CRI_BITS        8
1579
`define OR1200_IMMUCFGR_PRI_BITS        9
1580
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1581
`define OR1200_IMMUCFGR_HTR_BITS        11
1582
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1583
 
1584
// IMMUCFGR values
1585
`ifdef OR1200_NO_IMMU
1586
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1587
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1588
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1589
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1590
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1591
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1592
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1593
`define OR1200_IMMUCFGR_RES1            20'h00000
1594
`else
1595
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1596
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1597
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1598
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1599
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1600
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1601
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1602
`define OR1200_IMMUCFGR_RES1            20'h00000
1603
`endif
1604
 
1605
// DCCFGR fields
1606
`define OR1200_DCCFGR_NCW_BITS          2:0
1607
`define OR1200_DCCFGR_NCS_BITS          6:3
1608
`define OR1200_DCCFGR_CBS_BITS          7
1609
`define OR1200_DCCFGR_CWS_BITS          8
1610
`define OR1200_DCCFGR_CCRI_BITS         9
1611
`define OR1200_DCCFGR_CBIRI_BITS        10
1612
`define OR1200_DCCFGR_CBPRI_BITS        11
1613
`define OR1200_DCCFGR_CBLRI_BITS        12
1614
`define OR1200_DCCFGR_CBFRI_BITS        13
1615
`define OR1200_DCCFGR_CBWBRI_BITS       14
1616
`define OR1200_DCCFGR_RES1_BITS 31:15
1617
 
1618
// DCCFGR values
1619
`ifdef OR1200_NO_DC
1620
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1621
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1622
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1623
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1624 348 julius
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1625
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1626 6 julius
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1627
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1628 348 julius
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1629 6 julius
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1630
`define OR1200_DCCFGR_RES1              17'h00000
1631
`else
1632
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1633
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1634 363 julius
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
1635 348 julius
`ifdef OR1200_DC_WRITETHROUGH
1636
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
1637
`else
1638
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
1639
`endif
1640 6 julius
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1641
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1642
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1643
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1644
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1645 348 julius
`ifdef OR1200_DC_WRITETHROUGH
1646
 `define OR1200_DCCFGR_CBWBRI           1'b0    // Cache block WB reg not impl.
1647
`else
1648
 `define OR1200_DCCFGR_CBWBRI           1'b1    // Cache block WB reg impl.
1649
`endif
1650 6 julius
`define OR1200_DCCFGR_RES1              17'h00000
1651
`endif
1652
 
1653
// ICCFGR fields
1654
`define OR1200_ICCFGR_NCW_BITS          2:0
1655
`define OR1200_ICCFGR_NCS_BITS          6:3
1656
`define OR1200_ICCFGR_CBS_BITS          7
1657
`define OR1200_ICCFGR_CWS_BITS          8
1658
`define OR1200_ICCFGR_CCRI_BITS         9
1659
`define OR1200_ICCFGR_CBIRI_BITS        10
1660
`define OR1200_ICCFGR_CBPRI_BITS        11
1661
`define OR1200_ICCFGR_CBLRI_BITS        12
1662
`define OR1200_ICCFGR_CBFRI_BITS        13
1663
`define OR1200_ICCFGR_CBWBRI_BITS       14
1664
`define OR1200_ICCFGR_RES1_BITS 31:15
1665
 
1666
// ICCFGR values
1667
`ifdef OR1200_NO_IC
1668
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1669
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1670
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1671
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1672
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1673
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1674
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1675
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1676
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1677
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1678
`define OR1200_ICCFGR_RES1              17'h00000
1679
`else
1680
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1681
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1682 363 julius
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
1683 6 julius
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1684
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1685
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1686
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1687
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1688
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1689
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1690
`define OR1200_ICCFGR_RES1              17'h00000
1691
`endif
1692
 
1693
// DCFGR fields
1694 348 julius
`define OR1200_DCFGR_NDP_BITS           3:0
1695
`define OR1200_DCFGR_WPCI_BITS          4
1696
`define OR1200_DCFGR_RES1_BITS          31:5
1697 6 julius
 
1698
// DCFGR values
1699
`ifdef OR1200_DU_HWBKPTS
1700 348 julius
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1701 6 julius
`ifdef OR1200_DU_DWCR0
1702
`define OR1200_DCFGR_WPCI               1'b1
1703
`else
1704
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1705
`endif
1706
`else
1707 348 julius
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1708 6 julius
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1709
`endif
1710 363 julius
`define OR1200_DCFGR_RES1               27'd0
1711 348 julius
 
1712
///////////////////////////////////////////////////////////////////////////////
1713
// Boot Address Selection                                                    //
1714
// This only changes where the initial reset occurs. EPH setting is still    //
1715
// used to determine where vectors are located.                              //
1716
///////////////////////////////////////////////////////////////////////////////
1717
 // Boot from 0xf0000100
1718
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1719
//`define OR1200_BOOT_ADR 32'hf0000100
1720
// Boot from 0x100
1721
 `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1722
 `define OR1200_BOOT_ADR 32'h00000100

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