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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 348 julius
////  http://opencores.org/project,or1k                           ////
7 6 julius
////                                                              ////
8
////  Description                                                 ////
9 348 julius
////  Defines for the OR1200 core                                 ////
10 6 julius
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_defines.v,v $
45 348 julius
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, bugs fixed. 
48 6 julius
 
49
//
50
// Dump VCD
51
//
52
//`define OR1200_VCD_DUMP
53
 
54
//
55
// Generate debug messages during simulation
56
//
57
//`define OR1200_VERBOSE
58
 
59
//  `define OR1200_ASIC
60
////////////////////////////////////////////////////////
61
//
62
// Typical configuration for an ASIC
63
//
64
`ifdef OR1200_ASIC
65
 
66
//
67
// Target ASIC memories
68
//
69
//`define OR1200_ARTISAN_SSP
70
//`define OR1200_ARTISAN_SDP
71
//`define OR1200_ARTISAN_STP
72
`define OR1200_VIRTUALSILICON_SSP
73
//`define OR1200_VIRTUALSILICON_STP_T1
74
//`define OR1200_VIRTUALSILICON_STP_T2
75
 
76
//
77
// Do not implement Data cache
78
//
79
//`define OR1200_NO_DC
80
 
81
//
82
// Do not implement Insn cache
83
//
84
//`define OR1200_NO_IC
85
 
86
//
87
// Do not implement Data MMU
88
//
89
//`define OR1200_NO_DMMU
90
 
91
//
92
// Do not implement Insn MMU
93
//
94
//`define OR1200_NO_IMMU
95
 
96
//
97
// Select between ASIC optimized and generic multiplier
98
//
99
//`define OR1200_ASIC_MULTP2_32X32
100
`define OR1200_GENERIC_MULTP2_32X32
101
 
102
//
103
// Size/type of insn/data cache if implemented
104
//
105
// `define OR1200_IC_1W_512B
106
// `define OR1200_IC_1W_4KB
107
`define OR1200_IC_1W_8KB
108
// `define OR1200_DC_1W_4KB
109
`define OR1200_DC_1W_8KB
110
 
111
`else
112
 
113
 
114
/////////////////////////////////////////////////////////
115
//
116
// Typical configuration for an FPGA
117
//
118
 
119
//
120
// Target FPGA memories
121
//
122
//`define OR1200_ALTERA_LPM
123
//`define OR1200_XILINX_RAMB16
124
//`define OR1200_XILINX_RAMB4
125
//`define OR1200_XILINX_RAM32X1D
126
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
127 348 julius
// Generic models should infer RAM blocks at synthesis time (not only effects 
128
// single port ram.)
129
`define OR1200_GENERIC
130 6 julius
 
131
//
132
// Do not implement Data cache
133
//
134 348 julius
//`define OR1200_NO_DC
135 6 julius
 
136
//
137
// Do not implement Insn cache
138
//
139
//`define OR1200_NO_IC
140
 
141
//
142
// Do not implement Data MMU
143
//
144
//`define OR1200_NO_DMMU
145
 
146
//
147
// Do not implement Insn MMU
148
//
149
//`define OR1200_NO_IMMU
150
 
151
//
152
// Select between ASIC and generic multiplier
153
//
154
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
155
//
156
//`define OR1200_ASIC_MULTP2_32X32
157
`define OR1200_GENERIC_MULTP2_32X32
158
 
159
//
160
// Size/type of insn/data cache if implemented
161
// (consider available FPGA memory resources)
162
//
163
//`define OR1200_IC_1W_512B
164 477 julius
`define OR1200_IC_1W_4KB
165 476 julius
//`define OR1200_IC_1W_8KB
166 477 julius
//`define OR1200_IC_1W_16KB
167
//`define OR1200_IC_1W_32KB
168
`define OR1200_DC_1W_4KB
169 476 julius
//`define OR1200_DC_1W_8KB
170 477 julius
//`define OR1200_DC_1W_16KB
171
//`define OR1200_DC_1W_32KB
172 6 julius
 
173
`endif
174
 
175
 
176
//////////////////////////////////////////////////////////
177
//
178
// Do not change below unless you know what you are doing
179
//
180
 
181
//
182 358 julius
// Reset active low
183
//
184
//`define OR1200_RST_ACT_LOW
185
 
186
//
187 6 julius
// Enable RAM BIST
188
//
189
// At the moment this only works for Virtual Silicon
190
// single port RAMs. For other RAMs it has not effect.
191
// Special wrapper for VS RAMs needs to be provided
192
// with scan flops to facilitate bist scan.
193
//
194
//`define OR1200_BIST
195
 
196
//
197
// Register OR1200 WISHBONE outputs
198
// (must be defined/enabled)
199
//
200
`define OR1200_REGISTERED_OUTPUTS
201
 
202
//
203
// Register OR1200 WISHBONE inputs
204
//
205
// (must be undefined/disabled)
206
//
207
//`define OR1200_REGISTERED_INPUTS
208
 
209
//
210
// Disable bursts if they are not supported by the
211
// memory subsystem (only affect cache line fill)
212
//
213 348 julius
//`define OR1200_NO_BURSTS
214 6 julius
//
215
 
216
//
217
// WISHBONE retry counter range
218
//
219
// 2^value range for retry counter. Retry counter
220
// is activated whenever *wb_rty_i is asserted and
221
// until retry counter expires, corresponding
222
// WISHBONE interface is deactivated.
223
//
224
// To disable retry counters and *wb_rty_i all together,
225
// undefine this macro.
226
//
227
//`define OR1200_WB_RETRY 7
228
 
229
//
230
// WISHBONE Consecutive Address Burst
231
//
232
// This was used prior to WISHBONE B3 specification
233
// to identify bursts. It is no longer needed but
234
// remains enabled for compatibility with old designs.
235
//
236
// To remove *wb_cab_o ports undefine this macro.
237
//
238
//`define OR1200_WB_CAB
239
 
240
//
241
// WISHBONE B3 compatible interface
242
//
243
// This follows the WISHBONE B3 specification.
244
// It is not enabled by default because most
245
// designs still don't use WB b3.
246
//
247
// To enable *wb_cti_o/*wb_bte_o ports,
248
// define this macro.
249
//
250
`define OR1200_WB_B3
251
 
252
//
253
// LOG all WISHBONE accesses
254
//
255
`define OR1200_LOG_WB_ACCESS
256
 
257
//
258
// Enable additional synthesis directives if using
259
// _Synopsys_ synthesis tool
260
//
261
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
262
 
263
//
264
// Enables default statement in some case blocks
265
// and disables Synopsys synthesis directive full_case
266
//
267
// By default it is enabled. When disabled it
268
// can increase clock frequency.
269
//
270
`define OR1200_CASE_DEFAULT
271
 
272
//
273
// Operand width / register file address width
274
//
275
// (DO NOT CHANGE)
276
//
277
`define OR1200_OPERAND_WIDTH            32
278
`define OR1200_REGFILE_ADDR_WIDTH       5
279
 
280
//
281
// l.add/l.addi/l.and and optional l.addc/l.addic
282
// also set (compare) flag when result of their
283
// operation equals zero
284
//
285
// At the time of writing this, default or32
286
// C/C++ compiler doesn't generate code that
287
// would benefit from this optimization.
288
//
289
// By default this optimization is disabled to
290
// save area.
291
//
292
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
293
 
294
//
295
// Implement l.addc/l.addic instructions
296
//
297
// By default implementation of l.addc/l.addic
298
// instructions is enabled in case you need them.
299
// If you don't use them, then disable implementation
300
// to save area.
301
//
302 348 julius
//`define OR1200_IMPL_ADDC
303 6 julius
 
304
//
305 348 julius
// Implement l.sub instruction
306 6 julius
//
307 348 julius
// By default implementation of l.sub instructions
308
// is enabled to be compliant with the simulator.
309
// If you don't use carry bit, then disable
310
// implementation to save area.
311 6 julius
//
312 348 julius
`define OR1200_IMPL_SUB
313 6 julius
 
314
//
315 348 julius
// Implement carry bit SR[CY]
316 6 julius
//
317
//
318 348 julius
// By default implementation of SR[CY] is enabled
319
// to be compliant with the simulator. However SR[CY]
320
// is explicitly only used by l.addc/l.addic/l.sub
321
// instructions and if these three insns are not
322
// implemented there is not much point having SR[CY].
323 6 julius
//
324 348 julius
//`define OR1200_IMPL_CY
325 6 julius
 
326
//
327
// Implement rotate in the ALU
328
//
329
// At the time of writing this, or32
330
// C/C++ compiler doesn't generate rotate
331
// instructions. However or32 assembler
332
// can assemble code that uses rotate insn.
333
// This means that rotate instructions
334
// must be used manually inserted.
335
//
336
// By default implementation of rotate
337
// is disabled to save area and increase
338
// clock frequency.
339
//
340
//`define OR1200_IMPL_ALU_ROTATE
341
 
342
//
343
// Type of ALU compare to implement
344
//
345
// Try either one to find what yields
346
// higher clock frequencyin your case.
347
//
348
//`define OR1200_IMPL_ALU_COMP1
349
`define OR1200_IMPL_ALU_COMP2
350
 
351
//
352 403 julius
// Implement Find First/Last '1'
353
//
354
`define OR1200_IMPL_ALU_FFL1
355
 
356
//
357 499 julius
// Implement l.cust5 ALU instruction
358
//
359
//`define OR1200_IMPL_ALU_CUST5
360
 
361
//
362
// Implement l.extXs and l.extXz instructions
363
//
364
`define OR1200_IMPL_ALU_EXT
365
 
366
//
367 6 julius
// Implement multiplier
368
//
369
// By default multiplier is implemented
370
//
371
`define OR1200_MULT_IMPLEMENTED
372
 
373
//
374
// Implement multiply-and-accumulate
375
//
376
// By default MAC is implemented. To
377 435 julius
// implement MAC, multiplier (non-serial) needs to be
378 6 julius
// implemented.
379
//
380
`define OR1200_MAC_IMPLEMENTED
381
 
382
//
383 348 julius
// Implement optional l.div/l.divu instructions
384
//
385
// By default divide instructions are not implemented
386 435 julius
// to save area.
387 348 julius
//
388
//
389
`define OR1200_DIV_IMPLEMENTED
390
 
391
//
392 435 julius
// Serial multiplier.
393 6 julius
//
394 435 julius
//`define OR1200_MULT_SERIAL
395
 
396 6 julius
//
397 435 julius
// Serial divider.
398
// Uncomment to use a serial divider, otherwise will
399
// be a generic parallel implementation.
400
//
401
//`define OR1200_DIV_SERIAL
402 6 julius
 
403
//
404 58 julius
// Implement HW Single Precision FPU
405
//
406 462 julius
`define OR1200_FPU_IMPLEMENTED
407 58 julius
 
408
//
409 6 julius
// Clock ratio RISC clock versus WB clock
410
//
411
// If you plan to run WB:RISC clock fixed to 1:1, disable
412
// both defines
413
//
414
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
415
// and use clmode to set ratio
416
//
417
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
418
// clmode to set ratio
419
//
420 348 julius
//`define OR1200_CLKDIV_2_SUPPORTED
421 6 julius
//`define OR1200_CLKDIV_4_SUPPORTED
422
 
423
//
424
// Type of register file RAM
425
//
426
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
427
//`define OR1200_RFRAM_TWOPORT
428
//
429 348 julius
// Memory macro dual port (see or1200_dpram.v)
430 6 julius
`define OR1200_RFRAM_DUALPORT
431
 
432
//
433
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
434
//`define OR1200_RFRAM_GENERIC
435
//  Generic register file supports - 16 registers 
436
`ifdef OR1200_RFRAM_GENERIC
437
//    `define OR1200_RFRAM_16REG
438
`endif
439
 
440
//
441
// Type of mem2reg aligner to implement.
442
//
443
// Once OR1200_IMPL_MEM2REG2 yielded faster
444
// circuit, however with today tools it will
445
// most probably give you slower circuit.
446
//
447
`define OR1200_IMPL_MEM2REG1
448
//`define OR1200_IMPL_MEM2REG2
449
 
450
//
451 358 julius
// Reset value and event
452
//
453
`ifdef OR1200_RST_ACT_LOW
454
  `define OR1200_RST_VALUE      (1'b0)
455
  `define OR1200_RST_EVENT      negedge
456
`else
457
  `define OR1200_RST_VALUE      (1'b1)
458
  `define OR1200_RST_EVENT      posedge
459
`endif
460
 
461
//
462 6 julius
// ALUOPs
463
//
464 499 julius
`define OR1200_ALUOP_WIDTH      5
465
`define OR1200_ALUOP_NOP        5'b0_0100
466
/* LS-nibble encodings correspond to bits [3:0] of instruction */
467
`define OR1200_ALUOP_ADD        5'b0_0000 // 0
468
`define OR1200_ALUOP_ADDC       5'b0_0001 // 1
469
`define OR1200_ALUOP_SUB        5'b0_0010 // 2
470
`define OR1200_ALUOP_AND        5'b0_0011 // 3
471
`define OR1200_ALUOP_OR         5'b0_0100 // 4
472
`define OR1200_ALUOP_XOR        5'b0_0101 // 5
473
`define OR1200_ALUOP_MUL        5'b0_0110 // 6
474
`define OR1200_ALUOP_RESERVED   5'b0_0111 // 7
475
`define OR1200_ALUOP_SHROT      5'b0_1000 // 8
476
`define OR1200_ALUOP_DIV        5'b0_1001 // 9
477
`define OR1200_ALUOP_DIVU       5'b0_1010 // a
478
`define OR1200_ALUOP_MULU       5'b0_1011 // b
479
`define OR1200_ALUOP_EXTHB      5'b0_1100 // c
480
`define OR1200_ALUOP_EXTW       5'b0_1101 // d
481
`define OR1200_ALUOP_CMOV       5'b0_1110 // e
482
`define OR1200_ALUOP_FFL1       5'b0_1111 // f
483 403 julius
 
484 499 julius
/* Values sent to ALU from decode unit - not defined by ISA */
485
`define OR1200_ALUOP_COMP       5'b1_0000 // Comparison
486
`define OR1200_ALUOP_MOVHI      5'b1_0001 // Move-high
487
`define OR1200_ALUOP_CUST5      5'b1_0010 // l.cust5
488 403 julius
 
489 499 julius
// ALU instructions second opcode field
490
`define OR1200_ALUOP2_POS       9:6
491
`define OR1200_ALUOP2_WIDTH     4
492 403 julius
 
493 6 julius
//
494
// MACOPs
495
//
496 348 julius
`define OR1200_MACOP_WIDTH      3
497
`define OR1200_MACOP_NOP        3'b000
498
`define OR1200_MACOP_MAC        3'b001
499
`define OR1200_MACOP_MSB        3'b010
500 6 julius
 
501
//
502
// Shift/rotate ops
503
//
504 499 julius
`define OR1200_SHROTOP_WIDTH    4
505
`define OR1200_SHROTOP_NOP      4'd0
506
`define OR1200_SHROTOP_SLL      4'd0
507
`define OR1200_SHROTOP_SRL      4'd1
508
`define OR1200_SHROTOP_SRA      4'd2
509
`define OR1200_SHROTOP_ROR      4'd3
510 6 julius
 
511 499 julius
//
512
// Zero/Sign Extend ops
513
//
514
`define OR1200_EXTHBOP_WIDTH      4
515
`define OR1200_EXTHBOP_BS         4'h1
516
`define OR1200_EXTHBOP_HS         4'h0
517
`define OR1200_EXTHBOP_BZ         4'h3
518
`define OR1200_EXTHBOP_HZ         4'h2
519
`define OR1200_EXTWOP_WIDTH       4
520
`define OR1200_EXTWOP_WS          4'h0
521
`define OR1200_EXTWOP_WZ          4'h1
522
 
523 6 julius
// Execution cycles per instruction
524 58 julius
`define OR1200_MULTICYCLE_WIDTH 3
525
`define OR1200_ONE_CYCLE                3'd0
526
`define OR1200_TWO_CYCLES               3'd1
527 6 julius
 
528 348 julius
// Execution control which will "wait on" a module to finish
529
`define OR1200_WAIT_ON_WIDTH 2
530 499 julius
`define OR1200_WAIT_ON_NOTHING    `OR1200_WAIT_ON_WIDTH'd0
531
`define OR1200_WAIT_ON_MULTMAC    `OR1200_WAIT_ON_WIDTH'd1
532
`define OR1200_WAIT_ON_FPU        `OR1200_WAIT_ON_WIDTH'd2
533
`define OR1200_WAIT_ON_MTSPR      `OR1200_WAIT_ON_WIDTH'd3
534 348 julius
 
535 499 julius
 
536 6 julius
// Operand MUX selects
537
`define OR1200_SEL_WIDTH                2
538
`define OR1200_SEL_RF                   2'd0
539
`define OR1200_SEL_IMM                  2'd1
540
`define OR1200_SEL_EX_FORW              2'd2
541
`define OR1200_SEL_WB_FORW              2'd3
542
 
543
//
544
// BRANCHOPs
545
//
546
`define OR1200_BRANCHOP_WIDTH           3
547
`define OR1200_BRANCHOP_NOP             3'd0
548
`define OR1200_BRANCHOP_J               3'd1
549
`define OR1200_BRANCHOP_JR              3'd2
550
`define OR1200_BRANCHOP_BAL             3'd3
551
`define OR1200_BRANCHOP_BF              3'd4
552
`define OR1200_BRANCHOP_BNF             3'd5
553
`define OR1200_BRANCHOP_RFE             3'd6
554
 
555
//
556
// LSUOPs
557
//
558
// Bit 0: sign extend
559
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
560
// Bit 3: 0 load, 1 store
561
`define OR1200_LSUOP_WIDTH              4
562
`define OR1200_LSUOP_NOP                4'b0000
563
`define OR1200_LSUOP_LBZ                4'b0010
564
`define OR1200_LSUOP_LBS                4'b0011
565
`define OR1200_LSUOP_LHZ                4'b0100
566
`define OR1200_LSUOP_LHS                4'b0101
567
`define OR1200_LSUOP_LWZ                4'b0110
568
`define OR1200_LSUOP_LWS                4'b0111
569 348 julius
`define OR1200_LSUOP_LD                 4'b0001
570
`define OR1200_LSUOP_SD                 4'b1000
571
`define OR1200_LSUOP_SB                 4'b1010
572
`define OR1200_LSUOP_SH                 4'b1100
573
`define OR1200_LSUOP_SW                 4'b1110
574 6 julius
 
575 348 julius
// Number of bits of load/store EA precalculated in ID stage
576
// for balancing ID and EX stages.
577
//
578
// Valid range: 2,3,...,30,31
579
`define OR1200_LSUEA_PRECALC            2
580
 
581 6 julius
// FETCHOPs
582
`define OR1200_FETCHOP_WIDTH            1
583
`define OR1200_FETCHOP_NOP              1'b0
584
`define OR1200_FETCHOP_LW               1'b1
585
 
586
//
587
// Register File Write-Back OPs
588
//
589
// Bit 0: register file write enable
590 58 julius
// Bits 3-1: write-back mux selects
591 348 julius
//
592 358 julius
`define OR1200_RFWBOP_WIDTH             4
593
`define OR1200_RFWBOP_NOP               4'b0000
594
`define OR1200_RFWBOP_ALU               3'b000
595
`define OR1200_RFWBOP_LSU               3'b001
596
`define OR1200_RFWBOP_SPRS              3'b010
597
`define OR1200_RFWBOP_LR                3'b011
598
`define OR1200_RFWBOP_FPU               3'b100
599 6 julius
 
600
// Compare instructions
601
`define OR1200_COP_SFEQ       3'b000
602
`define OR1200_COP_SFNE       3'b001
603
`define OR1200_COP_SFGT       3'b010
604
`define OR1200_COP_SFGE       3'b011
605
`define OR1200_COP_SFLT       3'b100
606
`define OR1200_COP_SFLE       3'b101
607
`define OR1200_COP_X          3'b111
608
`define OR1200_SIGNED_COMPARE 'd3
609
`define OR1200_COMPOP_WIDTH     4
610
 
611
//
612 348 julius
// FP OPs
613 58 julius
//
614
// MSbit indicates FPU operation valid
615
//
616 348 julius
`define OR1200_FPUOP_WIDTH      8
617
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
618
`define OR1200_FPUOP_CYCLES 3'd4
619
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
620
// implementation thus do not support double precision FP 
621
`define OR1200_FPUOP_DOUBLE_BIT 4
622
`define OR1200_FPUOP_ADD  8'b0000_0000
623
`define OR1200_FPUOP_SUB  8'b0000_0001
624
`define OR1200_FPUOP_MUL  8'b0000_0010
625
`define OR1200_FPUOP_DIV  8'b0000_0011
626
`define OR1200_FPUOP_ITOF 8'b0000_0100
627
`define OR1200_FPUOP_FTOI 8'b0000_0101
628
`define OR1200_FPUOP_REM  8'b0000_0110
629
`define OR1200_FPUOP_RESERVED  8'b0000_0111
630 58 julius
// FP Compare instructions
631 348 julius
`define OR1200_FPCOP_SFEQ 8'b0000_1000
632
`define OR1200_FPCOP_SFNE 8'b0000_1001
633
`define OR1200_FPCOP_SFGT 8'b0000_1010
634
`define OR1200_FPCOP_SFGE 8'b0000_1011
635
`define OR1200_FPCOP_SFLT 8'b0000_1100
636
`define OR1200_FPCOP_SFLE 8'b0000_1101
637 58 julius
 
638
//
639 6 julius
// TAGs for instruction bus
640
//
641
`define OR1200_ITAG_IDLE        4'h0    // idle bus
642
`define OR1200_ITAG_NI          4'h1    // normal insn
643
`define OR1200_ITAG_BE          4'hb    // Bus error exception
644
`define OR1200_ITAG_PE          4'hc    // Page fault exception
645
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
646
 
647
//
648
// TAGs for data bus
649
//
650
`define OR1200_DTAG_IDLE        4'h0    // idle bus
651
`define OR1200_DTAG_ND          4'h1    // normal data
652
`define OR1200_DTAG_AE          4'ha    // Alignment exception
653
`define OR1200_DTAG_BE          4'hb    // Bus error exception
654
`define OR1200_DTAG_PE          4'hc    // Page fault exception
655
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
656
 
657
 
658
//////////////////////////////////////////////
659
//
660
// ORBIS32 ISA specifics
661
//
662
 
663
// SHROT_OP position in machine word
664
`define OR1200_SHROTOP_POS              7:6
665
 
666
//
667
// Instruction opcode groups (basic)
668
//
669
`define OR1200_OR32_J                 6'b000000
670
`define OR1200_OR32_JAL               6'b000001
671
`define OR1200_OR32_BNF               6'b000011
672
`define OR1200_OR32_BF                6'b000100
673
`define OR1200_OR32_NOP               6'b000101
674
`define OR1200_OR32_MOVHI             6'b000110
675 499 julius
`define OR1200_OR32_MACRC             6'b000110
676 6 julius
`define OR1200_OR32_XSYNC             6'b001000
677
`define OR1200_OR32_RFE               6'b001001
678
/* */
679
`define OR1200_OR32_JR                6'b010001
680
`define OR1200_OR32_JALR              6'b010010
681
`define OR1200_OR32_MACI              6'b010011
682
/* */
683
`define OR1200_OR32_LWZ               6'b100001
684
`define OR1200_OR32_LBZ               6'b100011
685
`define OR1200_OR32_LBS               6'b100100
686
`define OR1200_OR32_LHZ               6'b100101
687
`define OR1200_OR32_LHS               6'b100110
688
`define OR1200_OR32_ADDI              6'b100111
689
`define OR1200_OR32_ADDIC             6'b101000
690
`define OR1200_OR32_ANDI              6'b101001
691
`define OR1200_OR32_ORI               6'b101010
692
`define OR1200_OR32_XORI              6'b101011
693
`define OR1200_OR32_MULI              6'b101100
694
`define OR1200_OR32_MFSPR             6'b101101
695
`define OR1200_OR32_SH_ROTI           6'b101110
696
`define OR1200_OR32_SFXXI             6'b101111
697
/* */
698
`define OR1200_OR32_MTSPR             6'b110000
699
`define OR1200_OR32_MACMSB            6'b110001
700 348 julius
`define OR1200_OR32_FLOAT             6'b110010
701 6 julius
/* */
702
`define OR1200_OR32_SW                6'b110101
703
`define OR1200_OR32_SB                6'b110110
704
`define OR1200_OR32_SH                6'b110111
705
`define OR1200_OR32_ALU               6'b111000
706
`define OR1200_OR32_SFXX              6'b111001
707 499 julius
`define OR1200_OR32_CUST5             6'b111100
708 6 julius
 
709
/////////////////////////////////////////////////////
710
//
711
// Exceptions
712
//
713
 
714
//
715
// Exception vectors per OR1K architecture:
716
// 0xPPPPP100 - reset
717
// 0xPPPPP200 - bus error
718
// ... etc
719
// where P represents exception prefix.
720
//
721
// Exception vectors can be customized as per
722
// the following formula:
723
// 0xPPPPPNVV - exception N
724
//
725
// P represents exception prefix
726
// N represents exception N
727
// VV represents length of the individual vector space,
728
//   usually it is 8 bits wide and starts with all bits zero
729
//
730
 
731
//
732
// PPPPP and VV parts
733
//
734
// Sum of these two defines needs to be 28
735
//
736
`define OR1200_EXCEPT_EPH0_P    20'h00000
737
`define OR1200_EXCEPT_EPH1_P    20'hF0000
738
`define OR1200_EXCEPT_V             8'h00
739
 
740
//
741
// N part width
742
//
743
`define OR1200_EXCEPT_WIDTH 4
744
 
745
//
746
// Definition of exception vectors
747
//
748
// To avoid implementation of a certain exception,
749
// simply comment out corresponding line
750
//
751
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
752
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
753 58 julius
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
754 6 julius
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
755
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
756
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
757
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
758
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
759
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
760
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
761
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
762
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
763
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
764
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
765
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
766
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
767
 
768
 
769
/////////////////////////////////////////////////////
770
//
771
// SPR groups
772
//
773
 
774
// Bits that define the group
775
`define OR1200_SPR_GROUP_BITS   15:11
776
 
777
// Width of the group bits
778
`define OR1200_SPR_GROUP_WIDTH  5
779
 
780
// Bits that define offset inside the group
781
`define OR1200_SPR_OFS_BITS 10:0
782
 
783
// List of groups
784
`define OR1200_SPR_GROUP_SYS    5'd00
785
`define OR1200_SPR_GROUP_DMMU   5'd01
786
`define OR1200_SPR_GROUP_IMMU   5'd02
787
`define OR1200_SPR_GROUP_DC     5'd03
788
`define OR1200_SPR_GROUP_IC     5'd04
789
`define OR1200_SPR_GROUP_MAC    5'd05
790
`define OR1200_SPR_GROUP_DU     5'd06
791
`define OR1200_SPR_GROUP_PM     5'd08
792
`define OR1200_SPR_GROUP_PIC    5'd09
793
`define OR1200_SPR_GROUP_TT     5'd10
794 348 julius
`define OR1200_SPR_GROUP_FPU    5'd11
795 6 julius
 
796
/////////////////////////////////////////////////////
797
//
798
// System group
799
//
800
 
801
//
802
// System registers
803
//
804
`define OR1200_SPR_CFGR         7'd0
805
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
806
`define OR1200_SPR_NPC          11'd16
807
`define OR1200_SPR_SR           11'd17
808
`define OR1200_SPR_PPC          11'd18
809 348 julius
`define OR1200_SPR_FPCSR        11'd20
810 6 julius
`define OR1200_SPR_EPCR         11'd32
811
`define OR1200_SPR_EEAR         11'd48
812
`define OR1200_SPR_ESR          11'd64
813
 
814
//
815
// SR bits
816
//
817 348 julius
`define OR1200_SR_WIDTH 17
818 6 julius
`define OR1200_SR_SM   0
819
`define OR1200_SR_TEE  1
820
`define OR1200_SR_IEE  2
821
`define OR1200_SR_DCE  3
822
`define OR1200_SR_ICE  4
823
`define OR1200_SR_DME  5
824
`define OR1200_SR_IME  6
825
`define OR1200_SR_LEE  7
826
`define OR1200_SR_CE   8
827
`define OR1200_SR_F    9
828
`define OR1200_SR_CY   10       // Unused
829
`define OR1200_SR_OV   11       // Unused
830
`define OR1200_SR_OVE  12       // Unused
831
`define OR1200_SR_DSX  13       // Unused
832
`define OR1200_SR_EPH  14
833
`define OR1200_SR_FO   15
834 348 julius
`define OR1200_SR_TED  16
835 6 julius
`define OR1200_SR_CID  31:28    // Unimplemented
836
 
837
//
838
// Bits that define offset inside the group
839
//
840
`define OR1200_SPROFS_BITS 10:0
841
 
842
//
843
// Default Exception Prefix
844
//
845
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
846
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
847
//
848
`define OR1200_SR_EPH_DEF       1'b0
849
 
850 348 julius
 
851 58 julius
//
852
// FPCSR bits
853
//
854
`define OR1200_FPCSR_WIDTH 12
855
`define OR1200_FPCSR_FPEE  0
856
`define OR1200_FPCSR_RM    2:1
857
`define OR1200_FPCSR_OVF   3
858
`define OR1200_FPCSR_UNF   4
859
`define OR1200_FPCSR_SNF   5
860
`define OR1200_FPCSR_QNF   6
861
`define OR1200_FPCSR_ZF    7
862
`define OR1200_FPCSR_IXF   8
863
`define OR1200_FPCSR_IVF   9
864
`define OR1200_FPCSR_INF   10
865
`define OR1200_FPCSR_DZF   11
866
`define OR1200_FPCSR_RES   31:12
867
 
868 6 julius
/////////////////////////////////////////////////////
869
//
870
// Power Management (PM)
871
//
872
 
873
// Define it if you want PM implemented
874
//`define OR1200_PM_IMPLEMENTED
875
 
876
// Bit positions inside PMR (don't change)
877
`define OR1200_PM_PMR_SDF 3:0
878
`define OR1200_PM_PMR_DME 4
879
`define OR1200_PM_PMR_SME 5
880
`define OR1200_PM_PMR_DCGE 6
881
`define OR1200_PM_PMR_UNUSED 31:7
882
 
883
// PMR offset inside PM group of registers
884
`define OR1200_PM_OFS_PMR 11'b0
885
 
886
// PM group
887
`define OR1200_SPRGRP_PM 5'd8
888
 
889
// Define if PMR can be read/written at any address inside PM group
890
`define OR1200_PM_PARTIAL_DECODING
891
 
892
// Define if reading PMR is allowed
893
`define OR1200_PM_READREGS
894
 
895
// Define if unused PMR bits should be zero
896
`define OR1200_PM_UNUSED_ZERO
897
 
898
 
899
/////////////////////////////////////////////////////
900
//
901
// Debug Unit (DU)
902
//
903
 
904
// Define it if you want DU implemented
905 403 julius
`define OR1200_DU_IMPLEMENTED
906 6 julius
 
907
//
908
// Define if you want HW Breakpoints
909
// (if HW breakpoints are not implemented
910
// only default software trapping is
911
// possible with l.trap insn - this is
912
// however already enough for use
913
// with or32 gdb)
914
//
915 348 julius
//`define OR1200_DU_HWBKPTS
916 6 julius
 
917 348 julius
// Number of DVR/DCR pairs if HW breakpoints enabled
918
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
919
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
920
`define OR1200_DU_DVRDCR_PAIRS 8
921 6 julius
 
922
// Define if you want trace buffer
923 348 julius
//      (for now only available for Xilinx Virtex FPGAs)
924 6 julius
//`define OR1200_DU_TB_IMPLEMENTED
925
 
926 348 julius
 
927 6 julius
//
928
// Address offsets of DU registers inside DU group
929
//
930
// To not implement a register, doq not define its address
931
//
932
`ifdef OR1200_DU_HWBKPTS
933
`define OR1200_DU_DVR0          11'd0
934
`define OR1200_DU_DVR1          11'd1
935
`define OR1200_DU_DVR2          11'd2
936
`define OR1200_DU_DVR3          11'd3
937
`define OR1200_DU_DVR4          11'd4
938
`define OR1200_DU_DVR5          11'd5
939
`define OR1200_DU_DVR6          11'd6
940
`define OR1200_DU_DVR7          11'd7
941
`define OR1200_DU_DCR0          11'd8
942
`define OR1200_DU_DCR1          11'd9
943
`define OR1200_DU_DCR2          11'd10
944
`define OR1200_DU_DCR3          11'd11
945
`define OR1200_DU_DCR4          11'd12
946
`define OR1200_DU_DCR5          11'd13
947
`define OR1200_DU_DCR6          11'd14
948
`define OR1200_DU_DCR7          11'd15
949
`endif
950
`define OR1200_DU_DMR1          11'd16
951
`ifdef OR1200_DU_HWBKPTS
952
`define OR1200_DU_DMR2          11'd17
953
`define OR1200_DU_DWCR0         11'd18
954
`define OR1200_DU_DWCR1         11'd19
955
`endif
956
`define OR1200_DU_DSR           11'd20
957
`define OR1200_DU_DRR           11'd21
958
`ifdef OR1200_DU_TB_IMPLEMENTED
959
`define OR1200_DU_TBADR         11'h0ff
960 363 julius
`define OR1200_DU_TBIA          11'h1??
961
`define OR1200_DU_TBIM          11'h2??
962
`define OR1200_DU_TBAR          11'h3??
963
`define OR1200_DU_TBTS          11'h4??
964 6 julius
`endif
965
 
966
// Position of offset bits inside SPR address
967
`define OR1200_DUOFS_BITS       10:0
968
 
969
// DCR bits
970
`define OR1200_DU_DCR_DP        0
971
`define OR1200_DU_DCR_CC        3:1
972
`define OR1200_DU_DCR_SC        4
973
`define OR1200_DU_DCR_CT        7:5
974
 
975
// DMR1 bits
976
`define OR1200_DU_DMR1_CW0      1:0
977
`define OR1200_DU_DMR1_CW1      3:2
978
`define OR1200_DU_DMR1_CW2      5:4
979
`define OR1200_DU_DMR1_CW3      7:6
980
`define OR1200_DU_DMR1_CW4      9:8
981
`define OR1200_DU_DMR1_CW5      11:10
982
`define OR1200_DU_DMR1_CW6      13:12
983
`define OR1200_DU_DMR1_CW7      15:14
984
`define OR1200_DU_DMR1_CW8      17:16
985
`define OR1200_DU_DMR1_CW9      19:18
986
`define OR1200_DU_DMR1_CW10     21:20
987
`define OR1200_DU_DMR1_ST       22
988
`define OR1200_DU_DMR1_BT       23
989
`define OR1200_DU_DMR1_DXFW     24
990
`define OR1200_DU_DMR1_ETE      25
991
 
992
// DMR2 bits
993
`define OR1200_DU_DMR2_WCE0     0
994
`define OR1200_DU_DMR2_WCE1     1
995 348 julius
`define OR1200_DU_DMR2_AWTC     12:2
996
`define OR1200_DU_DMR2_WGB      23:13
997 6 julius
 
998
// DWCR bits
999
`define OR1200_DU_DWCR_COUNT    15:0
1000
`define OR1200_DU_DWCR_MATCH    31:16
1001
 
1002
// DSR bits
1003
`define OR1200_DU_DSR_WIDTH     14
1004
`define OR1200_DU_DSR_RSTE      0
1005
`define OR1200_DU_DSR_BUSEE     1
1006
`define OR1200_DU_DSR_DPFE      2
1007
`define OR1200_DU_DSR_IPFE      3
1008
`define OR1200_DU_DSR_TTE       4
1009
`define OR1200_DU_DSR_AE        5
1010
`define OR1200_DU_DSR_IIE       6
1011
`define OR1200_DU_DSR_IE        7
1012
`define OR1200_DU_DSR_DME       8
1013
`define OR1200_DU_DSR_IME       9
1014
`define OR1200_DU_DSR_RE        10
1015
`define OR1200_DU_DSR_SCE       11
1016 58 julius
`define OR1200_DU_DSR_FPE       12
1017 6 julius
`define OR1200_DU_DSR_TE        13
1018
 
1019
// DRR bits
1020
`define OR1200_DU_DRR_RSTE      0
1021
`define OR1200_DU_DRR_BUSEE     1
1022
`define OR1200_DU_DRR_DPFE      2
1023
`define OR1200_DU_DRR_IPFE      3
1024
`define OR1200_DU_DRR_TTE       4
1025
`define OR1200_DU_DRR_AE        5
1026
`define OR1200_DU_DRR_IIE       6
1027
`define OR1200_DU_DRR_IE        7
1028
`define OR1200_DU_DRR_DME       8
1029
`define OR1200_DU_DRR_IME       9
1030
`define OR1200_DU_DRR_RE        10
1031
`define OR1200_DU_DRR_SCE       11
1032 58 julius
`define OR1200_DU_DRR_FPE       12
1033 6 julius
`define OR1200_DU_DRR_TE        13
1034
 
1035
// Define if reading DU regs is allowed
1036
`define OR1200_DU_READREGS
1037
 
1038
// Define if unused DU registers bits should be zero
1039
`define OR1200_DU_UNUSED_ZERO
1040
 
1041
// Define if IF/LSU status is not needed by devel i/f
1042
`define OR1200_DU_STATUS_UNIMPLEMENTED
1043
 
1044
/////////////////////////////////////////////////////
1045
//
1046
// Programmable Interrupt Controller (PIC)
1047
//
1048
 
1049
// Define it if you want PIC implemented
1050
`define OR1200_PIC_IMPLEMENTED
1051
 
1052
// Define number of interrupt inputs (2-31)
1053
`define OR1200_PIC_INTS 20
1054
 
1055
// Address offsets of PIC registers inside PIC group
1056
`define OR1200_PIC_OFS_PICMR 2'd0
1057
`define OR1200_PIC_OFS_PICSR 2'd2
1058
 
1059
// Position of offset bits inside SPR address
1060
`define OR1200_PICOFS_BITS 1:0
1061
 
1062
// Define if you want these PIC registers to be implemented
1063
`define OR1200_PIC_PICMR
1064
`define OR1200_PIC_PICSR
1065
 
1066
// Define if reading PIC registers is allowed
1067
`define OR1200_PIC_READREGS
1068
 
1069
// Define if unused PIC register bits should be zero
1070
`define OR1200_PIC_UNUSED_ZERO
1071
 
1072
 
1073
/////////////////////////////////////////////////////
1074
//
1075
// Tick Timer (TT)
1076
//
1077
 
1078
// Define it if you want TT implemented
1079
`define OR1200_TT_IMPLEMENTED
1080
 
1081
// Address offsets of TT registers inside TT group
1082
`define OR1200_TT_OFS_TTMR 1'd0
1083
`define OR1200_TT_OFS_TTCR 1'd1
1084
 
1085
// Position of offset bits inside SPR group
1086
`define OR1200_TTOFS_BITS 0
1087
 
1088
// Define if you want these TT registers to be implemented
1089
`define OR1200_TT_TTMR
1090
`define OR1200_TT_TTCR
1091
 
1092
// TTMR bits
1093
`define OR1200_TT_TTMR_TP 27:0
1094
`define OR1200_TT_TTMR_IP 28
1095
`define OR1200_TT_TTMR_IE 29
1096
`define OR1200_TT_TTMR_M 31:30
1097
 
1098
// Define if reading TT registers is allowed
1099
`define OR1200_TT_READREGS
1100
 
1101
 
1102
//////////////////////////////////////////////
1103
//
1104
// MAC
1105
//
1106
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1107
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1108
 
1109
//
1110
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1111
//
1112
// According to architecture manual there is no shift, so default value is 0.
1113 356 julius
// However the implementation has deviated in this from the arch manual and had
1114
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
1115
// (if using libmad fixed point library). Shifts are no longer default setup, 
1116
// but if you need to remain backward compatible, define your shift bits, which
1117
// were normally
1118 6 julius
// dest_GPR = {MACHI,MACLO}[59:28]
1119
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1120
 
1121
 
1122
//////////////////////////////////////////////
1123
//
1124
// Data MMU (DMMU)
1125
//
1126
 
1127
//
1128
// Address that selects between TLB TR and MR
1129
//
1130
`define OR1200_DTLB_TM_ADDR     7
1131
 
1132
//
1133
// DTLBMR fields
1134
//
1135
`define OR1200_DTLBMR_V_BITS    0
1136
`define OR1200_DTLBMR_CID_BITS  4:1
1137
`define OR1200_DTLBMR_RES_BITS  11:5
1138
`define OR1200_DTLBMR_VPN_BITS  31:13
1139
 
1140
//
1141
// DTLBTR fields
1142
//
1143
`define OR1200_DTLBTR_CC_BITS   0
1144
`define OR1200_DTLBTR_CI_BITS   1
1145
`define OR1200_DTLBTR_WBC_BITS  2
1146
`define OR1200_DTLBTR_WOM_BITS  3
1147
`define OR1200_DTLBTR_A_BITS    4
1148
`define OR1200_DTLBTR_D_BITS    5
1149
`define OR1200_DTLBTR_URE_BITS  6
1150
`define OR1200_DTLBTR_UWE_BITS  7
1151
`define OR1200_DTLBTR_SRE_BITS  8
1152
`define OR1200_DTLBTR_SWE_BITS  9
1153
`define OR1200_DTLBTR_RES_BITS  11:10
1154
`define OR1200_DTLBTR_PPN_BITS  31:13
1155
 
1156
//
1157
// DTLB configuration
1158
//
1159
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1160
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1161
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1162
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1163
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1164
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1165
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1166
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1167
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1168
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1169
 
1170
//
1171
// Cache inhibit while DMMU is not enabled/implemented
1172
//
1173
// cache inhibited 0GB-4GB              1'b1
1174
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1175
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1176
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1177
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1178
// cached 0GB-4GB                       1'b0
1179
//
1180 348 julius
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1181 6 julius
 
1182
 
1183
//////////////////////////////////////////////
1184
//
1185
// Insn MMU (IMMU)
1186
//
1187
 
1188
//
1189
// Address that selects between TLB TR and MR
1190
//
1191
`define OR1200_ITLB_TM_ADDR     7
1192
 
1193
//
1194
// ITLBMR fields
1195
//
1196
`define OR1200_ITLBMR_V_BITS    0
1197
`define OR1200_ITLBMR_CID_BITS  4:1
1198
`define OR1200_ITLBMR_RES_BITS  11:5
1199
`define OR1200_ITLBMR_VPN_BITS  31:13
1200
 
1201
//
1202
// ITLBTR fields
1203
//
1204
`define OR1200_ITLBTR_CC_BITS   0
1205
`define OR1200_ITLBTR_CI_BITS   1
1206
`define OR1200_ITLBTR_WBC_BITS  2
1207
`define OR1200_ITLBTR_WOM_BITS  3
1208
`define OR1200_ITLBTR_A_BITS    4
1209
`define OR1200_ITLBTR_D_BITS    5
1210
`define OR1200_ITLBTR_SXE_BITS  6
1211
`define OR1200_ITLBTR_UXE_BITS  7
1212
`define OR1200_ITLBTR_RES_BITS  11:8
1213
`define OR1200_ITLBTR_PPN_BITS  31:13
1214
 
1215
//
1216
// ITLB configuration
1217
//
1218
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1219
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1220
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1221
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1222
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1223
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1224
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1225
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1226
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1227
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1228
 
1229
//
1230
// Cache inhibit while IMMU is not enabled/implemented
1231
// Note: all combinations that use icpu_adr_i cause async loop
1232
//
1233
// cache inhibited 0GB-4GB              1'b1
1234
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1235
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1236
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1237
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1238
// cached 0GB-4GB                       1'b0
1239
//
1240
`define OR1200_IMMU_CI                  1'b0
1241
 
1242
 
1243
/////////////////////////////////////////////////
1244
//
1245
// Insn cache (IC)
1246
//
1247
 
1248 477 julius
// 4 for 16 byte line, 5 for 32 byte lines.
1249
`ifdef OR1200_IC_1W_32KB
1250
 `define OR1200_ICLS            5
1251
`else
1252
 `define OR1200_ICLS            4
1253
`endif
1254 6 julius
 
1255
//
1256
// IC configurations
1257
//
1258
`ifdef OR1200_IC_1W_512B
1259 477 julius
`define OR1200_ICSIZE                   9                       // 512
1260
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 7
1261
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 8
1262
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 9
1263
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS // 5
1264
`define OR1200_ICTAG_W                  24
1265 6 julius
`endif
1266
`ifdef OR1200_IC_1W_4KB
1267
`define OR1200_ICSIZE                   12                      // 4096
1268
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1269
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1270
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1271
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1272
`define OR1200_ICTAG_W                  21
1273
`endif
1274
`ifdef OR1200_IC_1W_8KB
1275
`define OR1200_ICSIZE                   13                      // 8192
1276
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1277
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1278
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1279
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1280
`define OR1200_ICTAG_W                  20
1281
`endif
1282 476 julius
`ifdef OR1200_IC_1W_16KB
1283
`define OR1200_ICSIZE                   14                      // 16384
1284
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 12
1285
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 13
1286
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 14
1287
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 10
1288
`define OR1200_ICTAG_W                  19
1289
`endif
1290 477 julius
`ifdef OR1200_IC_1W_32KB
1291
`define OR1200_ICSIZE                   15                      // 32768
1292
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 13
1293
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 14
1294
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 14
1295
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 10
1296
`define OR1200_ICTAG_W                  18
1297
`endif
1298 6 julius
 
1299
 
1300
/////////////////////////////////////////////////
1301
//
1302
// Data cache (DC)
1303
//
1304
 
1305 477 julius
// 4 for 16 bytes, 5 for 32 bytes
1306
`ifdef OR1200_DC_1W_32KB
1307
 `define OR1200_DCLS            5
1308
`else
1309
 `define OR1200_DCLS            4
1310
`endif
1311 6 julius
 
1312 348 julius
// Define to enable default behavior of cache as write through
1313
// Turning this off enabled write back statergy
1314
//
1315
`define OR1200_DC_WRITETHROUGH
1316 6 julius
 
1317 348 julius
// Define to enable stores from the stack not doing writethrough.
1318
// EXPERIMENTAL
1319
//`define OR1200_DC_NOSTACKWRITETHROUGH
1320
 
1321
// Data cache SPR definitions
1322
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
1323
// Data cache group SPR addresses
1324
`define OR1200_SPRGRP_DC_DCCR           3'd0 // Not implemented
1325
`define OR1200_SPRGRP_DC_DCBPR          3'd1 // Not implemented
1326
`define OR1200_SPRGRP_DC_DCBFR          3'd2
1327
`define OR1200_SPRGRP_DC_DCBIR          3'd3
1328
`define OR1200_SPRGRP_DC_DCBWR          3'd4 // Not implemented
1329
`define OR1200_SPRGRP_DC_DCBLR          3'd5 // Not implemented
1330
 
1331 6 julius
//
1332
// DC configurations
1333
//
1334
`ifdef OR1200_DC_1W_4KB
1335
`define OR1200_DCSIZE                   12                      // 4096
1336
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1337
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1338
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1339
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1340
`define OR1200_DCTAG_W                  21
1341
`endif
1342
`ifdef OR1200_DC_1W_8KB
1343
`define OR1200_DCSIZE                   13                      // 8192
1344
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1345
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1346
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1347
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1348
`define OR1200_DCTAG_W                  20
1349
`endif
1350 476 julius
`ifdef OR1200_DC_1W_16KB
1351
`define OR1200_DCSIZE                   14                      // 16384
1352
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 12
1353
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 13
1354
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 14
1355
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 10
1356
`define OR1200_DCTAG_W                  19
1357
`endif
1358 477 julius
`ifdef OR1200_DC_1W_32KB
1359
`define OR1200_DCSIZE                   15                      // 32768
1360
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 13
1361
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 14
1362
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 15
1363
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 10
1364
`define OR1200_DCTAG_W                  18
1365
`endif
1366 6 julius
 
1367 348 julius
 
1368 6 julius
/////////////////////////////////////////////////
1369
//
1370
// Store buffer (SB)
1371
//
1372
 
1373
//
1374
// Store buffer
1375
//
1376
// It will improve performance by "caching" CPU stores
1377
// using store buffer. This is most important for function
1378
// prologues because DC can only work in write though mode
1379
// and all stores would have to complete external WB writes
1380
// to memory.
1381
// Store buffer is between DC and data BIU.
1382
// All stores will be stored into store buffer and immediately
1383
// completed by the CPU, even though actual external writes
1384
// will be performed later. As a consequence store buffer masks
1385
// all data bus errors related to stores (data bus errors
1386
// related to loads are delivered normally).
1387
// All pending CPU loads will wait until store buffer is empty to
1388
// ensure strict memory model. Right now this is necessary because
1389
// we don't make destinction between cached and cache inhibited
1390
// address space, so we simply empty store buffer until loads
1391
// can begin.
1392
//
1393
// It makes design a bit bigger, depending what is the number of
1394
// entries in SB FIFO. Number of entries can be changed further
1395
// down.
1396
//
1397
//`define OR1200_SB_IMPLEMENTED
1398
 
1399
//
1400
// Number of store buffer entries
1401
//
1402
// Verified number of entries are 4 and 8 entries
1403
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1404
// always match 2**OR1200_SB_LOG.
1405
// To disable store buffer, undefine
1406
// OR1200_SB_IMPLEMENTED.
1407
//
1408
`define OR1200_SB_LOG           2       // 2 or 3
1409
`define OR1200_SB_ENTRIES       4       // 4 or 8
1410
 
1411
 
1412
/////////////////////////////////////////////////
1413
//
1414
// Quick Embedded Memory (QMEM)
1415
//
1416
 
1417
//
1418
// Quick Embedded Memory
1419
//
1420
// Instantiation of dedicated insn/data memory (RAM or ROM).
1421
// Insn fetch has effective throughput 1insn / clock cycle.
1422
// Data load takes two clock cycles / access, data store
1423
// takes 1 clock cycle / access (if there is no insn fetch)).
1424
// Memory instantiation is shared between insn and data,
1425
// meaning if insn fetch are performed, data load/store
1426
// performance will be lower.
1427
//
1428
// Main reason for QMEM is to put some time critical functions
1429
// into this memory and to have predictable and fast access
1430
// to these functions. (soft fpu, context switch, exception
1431
// handlers, stack, etc)
1432
//
1433
// It makes design a bit bigger and slower. QMEM sits behind
1434
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1435
// used with QMEM and QMEM is seen by the CPU just like any other
1436
// memory in the system). IC/DC are sitting behind QMEM so the
1437
// whole design timing might be worse with QMEM implemented.
1438
//
1439
//`define OR1200_QMEM_IMPLEMENTED
1440
 
1441
//
1442
// Base address and mask of QMEM
1443
//
1444
// Base address defines first address of QMEM. Mask defines
1445
// QMEM range in address space. Actual size of QMEM is however
1446
// determined with instantiated RAM/ROM. However bigger
1447
// mask will reserve more address space for QMEM, but also
1448
// make design faster, while more tight mask will take
1449
// less address space but also make design slower. If
1450
// instantiated RAM/ROM is smaller than space reserved with
1451
// the mask, instatiated RAM/ROM will also be shadowed
1452
// at higher addresses in reserved space.
1453
//
1454
`define OR1200_QMEM_IADDR       32'h0080_0000
1455 348 julius
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1456
`define OR1200_QMEM_DADDR       32'h0080_0000
1457
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1458 6 julius
 
1459
//
1460
// QMEM interface byte-select capability
1461
//
1462
// To enable qmem_sel* ports, define this macro.
1463
//
1464
//`define OR1200_QMEM_BSEL
1465
 
1466
//
1467
// QMEM interface acknowledge
1468
//
1469
// To enable qmem_ack port, define this macro.
1470
//
1471
//`define OR1200_QMEM_ACK
1472
 
1473
/////////////////////////////////////////////////////
1474
//
1475
// VR, UPR and Configuration Registers
1476
//
1477
//
1478
// VR, UPR and configuration registers are optional. If 
1479
// implemented, operating system can automatically figure
1480
// out how to use the processor because it knows 
1481
// what units are available in the processor and how they
1482
// are configured.
1483
//
1484
// This section must be last in or1200_defines.v file so
1485
// that all units are already configured and thus
1486
// configuration registers are properly set.
1487
// 
1488
 
1489
// Define if you want configuration registers implemented
1490
`define OR1200_CFGR_IMPLEMENTED
1491
 
1492
// Define if you want full address decode inside SYS group
1493
`define OR1200_SYS_FULL_DECODE
1494
 
1495
// Offsets of VR, UPR and CFGR registers
1496
`define OR1200_SPRGRP_SYS_VR            4'h0
1497
`define OR1200_SPRGRP_SYS_UPR           4'h1
1498
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1499
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1500
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1501
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1502
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1503
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1504
 
1505
// VR fields
1506
`define OR1200_VR_REV_BITS              5:0
1507
`define OR1200_VR_RES1_BITS             15:6
1508
`define OR1200_VR_CFG_BITS              23:16
1509
`define OR1200_VR_VER_BITS              31:24
1510
 
1511
// VR values
1512 348 julius
`define OR1200_VR_REV                   6'h08
1513 6 julius
`define OR1200_VR_RES1                  10'h000
1514
`define OR1200_VR_CFG                   8'h00
1515
`define OR1200_VR_VER                   8'h12
1516
 
1517
// UPR fields
1518
`define OR1200_UPR_UP_BITS              0
1519
`define OR1200_UPR_DCP_BITS             1
1520
`define OR1200_UPR_ICP_BITS             2
1521
`define OR1200_UPR_DMP_BITS             3
1522
`define OR1200_UPR_IMP_BITS             4
1523
`define OR1200_UPR_MP_BITS              5
1524
`define OR1200_UPR_DUP_BITS             6
1525
`define OR1200_UPR_PCUP_BITS            7
1526
`define OR1200_UPR_PMP_BITS             8
1527
`define OR1200_UPR_PICP_BITS            9
1528
`define OR1200_UPR_TTP_BITS             10
1529 348 julius
`define OR1200_UPR_FPP_BITS             11
1530
`define OR1200_UPR_RES1_BITS            23:12
1531 6 julius
`define OR1200_UPR_CUP_BITS             31:24
1532
 
1533
// UPR values
1534
`define OR1200_UPR_UP                   1'b1
1535
`ifdef OR1200_NO_DC
1536
`define OR1200_UPR_DCP                  1'b0
1537
`else
1538
`define OR1200_UPR_DCP                  1'b1
1539
`endif
1540
`ifdef OR1200_NO_IC
1541
`define OR1200_UPR_ICP                  1'b0
1542
`else
1543
`define OR1200_UPR_ICP                  1'b1
1544
`endif
1545
`ifdef OR1200_NO_DMMU
1546
`define OR1200_UPR_DMP                  1'b0
1547
`else
1548
`define OR1200_UPR_DMP                  1'b1
1549
`endif
1550
`ifdef OR1200_NO_IMMU
1551
`define OR1200_UPR_IMP                  1'b0
1552
`else
1553
`define OR1200_UPR_IMP                  1'b1
1554
`endif
1555 348 julius
`ifdef OR1200_MAC_IMPLEMENTED
1556
`define OR1200_UPR_MP                   1'b1
1557
`else
1558
`define OR1200_UPR_MP                   1'b0
1559
`endif
1560 6 julius
`ifdef OR1200_DU_IMPLEMENTED
1561
`define OR1200_UPR_DUP                  1'b1
1562
`else
1563
`define OR1200_UPR_DUP                  1'b0
1564
`endif
1565
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1566 348 julius
`ifdef OR1200_PM_IMPLEMENTED
1567 6 julius
`define OR1200_UPR_PMP                  1'b1
1568
`else
1569
`define OR1200_UPR_PMP                  1'b0
1570
`endif
1571 348 julius
`ifdef OR1200_PIC_IMPLEMENTED
1572 6 julius
`define OR1200_UPR_PICP                 1'b1
1573
`else
1574
`define OR1200_UPR_PICP                 1'b0
1575
`endif
1576 348 julius
`ifdef OR1200_TT_IMPLEMENTED
1577 6 julius
`define OR1200_UPR_TTP                  1'b1
1578
`else
1579
`define OR1200_UPR_TTP                  1'b0
1580
`endif
1581 348 julius
`ifdef OR1200_FPU_IMPLEMENTED
1582
`define OR1200_UPR_FPP                  1'b1
1583
`else
1584
`define OR1200_UPR_FPP                  1'b0
1585
`endif
1586
`define OR1200_UPR_RES1                 12'h000
1587 6 julius
`define OR1200_UPR_CUP                  8'h00
1588
 
1589
// CPUCFGR fields
1590
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1591
`define OR1200_CPUCFGR_HGF_BITS     4
1592
`define OR1200_CPUCFGR_OB32S_BITS       5
1593
`define OR1200_CPUCFGR_OB64S_BITS       6
1594
`define OR1200_CPUCFGR_OF32S_BITS       7
1595
`define OR1200_CPUCFGR_OF64S_BITS       8
1596
`define OR1200_CPUCFGR_OV64S_BITS       9
1597
`define OR1200_CPUCFGR_RES1_BITS        31:10
1598
 
1599
// CPUCFGR values
1600
`define OR1200_CPUCFGR_NSGF                 4'h0
1601
`ifdef OR1200_RFRAM_16REG
1602
    `define OR1200_CPUCFGR_HGF                  1'b1
1603
`else
1604
    `define OR1200_CPUCFGR_HGF                  1'b0
1605
`endif
1606
`define OR1200_CPUCFGR_OB32S            1'b1
1607
`define OR1200_CPUCFGR_OB64S            1'b0
1608 348 julius
`ifdef OR1200_FPU_IMPLEMENTED
1609
 `define OR1200_CPUCFGR_OF32S           1'b1
1610
`else
1611
 `define OR1200_CPUCFGR_OF32S           1'b0
1612
`endif
1613
 
1614 6 julius
`define OR1200_CPUCFGR_OF64S            1'b0
1615
`define OR1200_CPUCFGR_OV64S            1'b0
1616
`define OR1200_CPUCFGR_RES1             22'h000000
1617
 
1618
// DMMUCFGR fields
1619
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1620
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1621
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1622
`define OR1200_DMMUCFGR_CRI_BITS        8
1623
`define OR1200_DMMUCFGR_PRI_BITS        9
1624
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1625
`define OR1200_DMMUCFGR_HTR_BITS        11
1626
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1627
 
1628
// DMMUCFGR values
1629
`ifdef OR1200_NO_DMMU
1630
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1631
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1632
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1633
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1634
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1635
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1636
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1637
`define OR1200_DMMUCFGR_RES1            20'h00000
1638
`else
1639
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1640
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1641
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1642
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1643
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1644
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1645
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1646
`define OR1200_DMMUCFGR_RES1            20'h00000
1647
`endif
1648
 
1649
// IMMUCFGR fields
1650
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1651
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1652
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1653
`define OR1200_IMMUCFGR_CRI_BITS        8
1654
`define OR1200_IMMUCFGR_PRI_BITS        9
1655
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1656
`define OR1200_IMMUCFGR_HTR_BITS        11
1657
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1658
 
1659
// IMMUCFGR values
1660
`ifdef OR1200_NO_IMMU
1661
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1662
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1663
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1664
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1665
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1666
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1667
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1668
`define OR1200_IMMUCFGR_RES1            20'h00000
1669
`else
1670
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1671
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1672
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1673
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1674
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1675
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1676
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1677
`define OR1200_IMMUCFGR_RES1            20'h00000
1678
`endif
1679
 
1680
// DCCFGR fields
1681
`define OR1200_DCCFGR_NCW_BITS          2:0
1682
`define OR1200_DCCFGR_NCS_BITS          6:3
1683
`define OR1200_DCCFGR_CBS_BITS          7
1684
`define OR1200_DCCFGR_CWS_BITS          8
1685
`define OR1200_DCCFGR_CCRI_BITS         9
1686
`define OR1200_DCCFGR_CBIRI_BITS        10
1687
`define OR1200_DCCFGR_CBPRI_BITS        11
1688
`define OR1200_DCCFGR_CBLRI_BITS        12
1689
`define OR1200_DCCFGR_CBFRI_BITS        13
1690
`define OR1200_DCCFGR_CBWBRI_BITS       14
1691
`define OR1200_DCCFGR_RES1_BITS 31:15
1692
 
1693
// DCCFGR values
1694
`ifdef OR1200_NO_DC
1695
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1696
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1697
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1698
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1699 348 julius
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1700
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1701 6 julius
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1702
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1703 348 julius
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1704 6 julius
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1705
`define OR1200_DCCFGR_RES1              17'h00000
1706
`else
1707
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1708
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1709 363 julius
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
1710 348 julius
`ifdef OR1200_DC_WRITETHROUGH
1711
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
1712
`else
1713
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
1714
`endif
1715 6 julius
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1716
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1717
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1718
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1719
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1720 348 julius
`ifdef OR1200_DC_WRITETHROUGH
1721
 `define OR1200_DCCFGR_CBWBRI           1'b0    // Cache block WB reg not impl.
1722
`else
1723
 `define OR1200_DCCFGR_CBWBRI           1'b1    // Cache block WB reg impl.
1724
`endif
1725 6 julius
`define OR1200_DCCFGR_RES1              17'h00000
1726
`endif
1727
 
1728
// ICCFGR fields
1729
`define OR1200_ICCFGR_NCW_BITS          2:0
1730
`define OR1200_ICCFGR_NCS_BITS          6:3
1731
`define OR1200_ICCFGR_CBS_BITS          7
1732
`define OR1200_ICCFGR_CWS_BITS          8
1733
`define OR1200_ICCFGR_CCRI_BITS         9
1734
`define OR1200_ICCFGR_CBIRI_BITS        10
1735
`define OR1200_ICCFGR_CBPRI_BITS        11
1736
`define OR1200_ICCFGR_CBLRI_BITS        12
1737
`define OR1200_ICCFGR_CBFRI_BITS        13
1738
`define OR1200_ICCFGR_CBWBRI_BITS       14
1739
`define OR1200_ICCFGR_RES1_BITS 31:15
1740
 
1741
// ICCFGR values
1742
`ifdef OR1200_NO_IC
1743
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1744
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1745
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1746
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1747
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1748
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1749
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1750
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1751
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1752
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1753
`define OR1200_ICCFGR_RES1              17'h00000
1754
`else
1755
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1756
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1757 363 julius
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
1758 6 julius
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1759
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1760
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1761
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1762
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1763
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1764
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1765
`define OR1200_ICCFGR_RES1              17'h00000
1766
`endif
1767
 
1768
// DCFGR fields
1769 348 julius
`define OR1200_DCFGR_NDP_BITS           3:0
1770
`define OR1200_DCFGR_WPCI_BITS          4
1771
`define OR1200_DCFGR_RES1_BITS          31:5
1772 6 julius
 
1773
// DCFGR values
1774
`ifdef OR1200_DU_HWBKPTS
1775 348 julius
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1776 6 julius
`ifdef OR1200_DU_DWCR0
1777
`define OR1200_DCFGR_WPCI               1'b1
1778
`else
1779
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1780
`endif
1781
`else
1782 348 julius
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1783 6 julius
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1784
`endif
1785 363 julius
`define OR1200_DCFGR_RES1               27'd0
1786 348 julius
 
1787
///////////////////////////////////////////////////////////////////////////////
1788
// Boot Address Selection                                                    //
1789 485 julius
//                                                                           //
1790
// Allows a definable boot address, potentially different to the usual reset //
1791
// vector to allow for power-on code to be run, if desired.                  //
1792
//                                                                           //
1793
// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
1794
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
1795
//                                                                           //
1796
// For default reset behavior uncomment the settings under the "Boot 0x100"  //
1797
// comment below.                                                            //
1798
//                                                                           //
1799 348 julius
///////////////////////////////////////////////////////////////////////////////
1800 485 julius
// Boot from 0xf0000100
1801 348 julius
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1802
//`define OR1200_BOOT_ADR 32'hf0000100
1803
// Boot from 0x100
1804
 `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1805
 `define OR1200_BOOT_ADR 32'h00000100

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