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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////  http://www.opencores.org/projects/jtag/                     ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tap_top.v,v $
// Revision 1.6  2004/01/27 10:00:33  mohor
// Unused registers removed.
//
// Revision 1.5  2004/01/18 09:27:39  simons
// Blocking non blocking assignmenst fixed.
//
// Revision 1.4  2004/01/17 17:37:44  mohor
// capture_dr_o added to ports.
//
// Revision 1.3  2004/01/14 13:50:56  mohor
// 5 consecutive TMS=1 causes reset of TAP.
//
// Revision 1.2  2004/01/08 10:29:44  mohor
// Control signals for tdo_pad_o mux are changed to negedge.
//
// Revision 1.1  2003/12/23 14:52:14  mohor
// Directory structure changed. New version of TAP.
//
// Revision 1.10  2003/10/23 18:08:01  mohor
// MBIST chain connection fixed.
//
// Revision 1.9  2003/10/23 16:17:02  mohor
// CRC logic changed.
//
// Revision 1.8  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.7  2002/11/06 14:30:10  mohor
// Trst active high. Inverted on higher layer.
//
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "tap_defines.v"
 
// Top module
//module tap_top(
module jtag_tap( // renamed by julius
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trst_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdo_o,
 
                // TDI signals from sub-modules
                debug_tdi_i,    // from debug module
                bs_chain_tdi_i, // from Boundary Scan Chain
                mbist_tdi_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trst_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdo_o;
 
// TDI signals from sub-modules
input   debug_tdi_i;    // from debug module
input   bs_chain_tdi_i; // from Boundary Scan Chain
input   mbist_tdi_i;    // from Mbist Chain
 
// Registers
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir, shift_ir_neg;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
reg     tdo_pad_o;
reg     tdo_padoe_o;
reg     tms_q1, tms_q2, tms_q3, tms_q4;
wire    tms_reset;
 
assign tdo_o = tdi_pad_i;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
always @ (posedge tck_pad_i)
begin
  tms_q1 <=  tms_pad_i;
  tms_q2 <=  tms_q1;
  tms_q3 <=  tms_q2;
  tms_q4 <=  tms_q3;
end
 
 
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;    // 5 consecutive TMS=1 causes reset
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// test_logic_reset state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    test_logic_reset<= 1'b1;
  else if (tms_reset)
    test_logic_reset<= 1'b1;
  else
    begin
      if(tms_pad_i & (test_logic_reset | select_ir_scan))
        test_logic_reset<= 1'b1;
      else
        test_logic_reset<= 1'b0;
    end
end
 
// run_test_idle state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    run_test_idle<= 1'b0;
  else if (tms_reset)
    run_test_idle<= 1'b0;
  else
  if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
    run_test_idle<= 1'b1;
  else
    run_test_idle<= 1'b0;
end
 
// select_dr_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_dr_scan<= 1'b0;
  else if (tms_reset)
    select_dr_scan<= 1'b0;
  else
  if(tms_pad_i & (run_test_idle | update_dr | update_ir))
    select_dr_scan<= 1'b1;
  else
    select_dr_scan<= 1'b0;
end
 
// capture_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_dr<= 1'b0;
  else if (tms_reset)
    capture_dr<= 1'b0;
  else
  if(~tms_pad_i & select_dr_scan)
    capture_dr<= 1'b1;
  else
    capture_dr<= 1'b0;
end
 
// shift_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_dr<= 1'b0;
  else if (tms_reset)
    shift_dr<= 1'b0;
  else
  if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
    shift_dr<= 1'b1;
  else
    shift_dr<= 1'b0;
end
 
// exit1_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_dr<= 1'b0;
  else if (tms_reset)
    exit1_dr<= 1'b0;
  else
  if(tms_pad_i & (capture_dr | shift_dr))
    exit1_dr<= 1'b1;
  else
    exit1_dr<= 1'b0;
end
 
// pause_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_dr<= 1'b0;
  else if (tms_reset)
    pause_dr<= 1'b0;
  else
  if(~tms_pad_i & (exit1_dr | pause_dr))
    pause_dr<= 1'b1;
  else
    pause_dr<= 1'b0;
end
 
// exit2_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_dr<= 1'b0;
  else if (tms_reset)
    exit2_dr<= 1'b0;
  else
  if(tms_pad_i & pause_dr)
    exit2_dr<= 1'b1;
  else
    exit2_dr<= 1'b0;
end
 
// update_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_dr<= 1'b0;
  else if (tms_reset)
    update_dr<= 1'b0;
  else
  if(tms_pad_i & (exit1_dr | exit2_dr))
    update_dr<= 1'b1;
  else
    update_dr<= 1'b0;
end
 
// select_ir_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_ir_scan<= 1'b0;
  else if (tms_reset)
    select_ir_scan<= 1'b0;
  else
  if(tms_pad_i & select_dr_scan)
    select_ir_scan<= 1'b1;
  else
    select_ir_scan<= 1'b0;
end
 
// capture_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_ir<= 1'b0;
  else if (tms_reset)
    capture_ir<= 1'b0;
  else
  if(~tms_pad_i & select_ir_scan)
    capture_ir<= 1'b1;
  else
    capture_ir<= 1'b0;
end
 
// shift_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_ir<= 1'b0;
  else if (tms_reset)
    shift_ir<= 1'b0;
  else
  if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
    shift_ir<= 1'b1;
  else
    shift_ir<= 1'b0;
end
 
// exit1_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_ir<= 1'b0;
  else if (tms_reset)
    exit1_ir<= 1'b0;
  else
  if(tms_pad_i & (capture_ir | shift_ir))
    exit1_ir<= 1'b1;
  else
    exit1_ir<= 1'b0;
end
 
// pause_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_ir<= 1'b0;
  else if (tms_reset)
    pause_ir<= 1'b0;
  else
  if(~tms_pad_i & (exit1_ir | pause_ir))
    pause_ir<= 1'b1;
  else
    pause_ir<= 1'b0;
end
 
// exit2_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_ir<= 1'b0;
  else if (tms_reset)
    exit2_ir<= 1'b0;
  else
  if(tms_pad_i & pause_ir)
    exit2_ir<= 1'b1;
  else
    exit2_ir<= 1'b0;
end
 
// update_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_ir<= 1'b0;
  else if (tms_reset)
    update_ir<= 1'b0;
  else
  if(tms_pad_i & (exit1_ir | exit2_ir))
    update_ir<= 1'b1;
  else
    update_ir<= 1'b0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir, latched_jtag_ir_neg;
reg                   instruction_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_ir[`IR_LENGTH-1:0] <=  `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <=  4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <=  {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  instruction_tdo <=  jtag_ir[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
reg        idcode_tdo;
 
always @ (posedge tck_pad_i)
begin
  if(idcode_select & shift_dr)
    idcode_reg <=  {tdi_pad_i, idcode_reg[31:1]};
  else
    idcode_reg <=  `IDCODE_VALUE;
end
 
always @ (negedge tck_pad_i)
begin
    idcode_tdo <=  idcode_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg  bypassed_tdo;
reg  bypass_reg;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if (trst_pad_i)
    bypass_reg<= 1'b0;
  else if(shift_dr)
    bypass_reg<= tdi_pad_i;
end
 
always @ (negedge tck_pad_i)
begin
  bypassed_tdo <= bypass_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
// Updating jtag_ir (Instruction Register)
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    latched_jtag_ir <= `IDCODE;   // IDCODE selected after reset
  else if (tms_reset)
    latched_jtag_ir <= `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <= jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating jtag_ir (Instruction Register)
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
          bypassed_tdo)
begin
  if(shift_ir_neg)
    tdo_pad_o = instruction_tdo;
  else
    begin
      case(latched_jtag_ir_neg)    // synthesis parallel_case
        `IDCODE:            tdo_pad_o = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_pad_o = debug_tdi_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o = bs_chain_tdi_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o = bs_chain_tdi_i;   // External test
        `MBIST:             tdo_pad_o = mbist_tdi_i;      // Mbist test
        default:            tdo_pad_o = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// Tristate control for tdo_pad_o pin
always @ (negedge tck_pad_i)
begin
  tdo_padoe_o <=  shift_ir | shift_dr | (pause_dr & debug_select);
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
 
always @ (negedge tck_pad_i)
begin
  shift_ir_neg <=  shift_ir;
  latched_jtag_ir_neg <=  latched_jtag_ir;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// http://www.opencores.org/projects/jtag/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: tap_top.v,v $`
46			`// Revision 1.6 2004/01/27 10:00:33 mohor`
47			`// Unused registers removed.`
48			`//`
49			`// Revision 1.5 2004/01/18 09:27:39 simons`
50			`// Blocking non blocking assignmenst fixed.`
51			`//`
52			`// Revision 1.4 2004/01/17 17:37:44 mohor`
53			`// capture_dr_o added to ports.`
54			`//`
55			`// Revision 1.3 2004/01/14 13:50:56 mohor`
56			`// 5 consecutive TMS=1 causes reset of TAP.`
57			`//`
58			`// Revision 1.2 2004/01/08 10:29:44 mohor`
59			`// Control signals for tdo_pad_o mux are changed to negedge.`
60			`//`
61			`// Revision 1.1 2003/12/23 14:52:14 mohor`
62			`// Directory structure changed. New version of TAP.`
63			`//`
64			`// Revision 1.10 2003/10/23 18:08:01 mohor`
65			`// MBIST chain connection fixed.`
66			`//`
67			`// Revision 1.9 2003/10/23 16:17:02 mohor`
68			`// CRC logic changed.`
69			`//`
70			`// Revision 1.8 2003/10/21 09:48:31 simons`
71			`// Mbist support added.`
72			`//`
73			`// Revision 1.7 2002/11/06 14:30:10 mohor`
74			`// Trst active high. Inverted on higher layer.`
75			`//`
76			`// Revision 1.6 2002/04/22 12:55:56 mohor`
77			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
78			`//`
79			`// Revision 1.5 2002/03/26 14:23:38 mohor`
80			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
81			`//`
82			`// Revision 1.4 2002/03/25 13:16:15 mohor`
83			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
84			`// not named correctly.`
85			`//`
86			`// Revision 1.3 2002/03/12 14:30:05 mohor`
87			`// Few outputs for boundary scan chain added.`
88			`//`
89			`// Revision 1.2 2002/03/12 10:31:53 mohor`
90			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
91			`// contains only tap state machine and related logic. dbg_top contains all`
92			`// logic necessery for debugging.`
93			`//`
94			`// Revision 1.1 2002/03/08 15:28:16 mohor`
95			`// Structure changed. Hooks for jtag chain added.`
96			`//`
97			`//`
98			`//`
99			`//`
100
101			`// synopsys translate_off`
102			`include "timescale.v"
103			`// synopsys translate_on`
104			`include "tap_defines.v"
105
106			`// Top module`
107	360	julius	`//module tap_top(`
108			`module jtag_tap( // renamed by julius`
109	6	julius	`// JTAG pads`
110			`tms_pad_i,`
111			`tck_pad_i,`
112			`trst_pad_i,`
113			`tdi_pad_i,`
114			`tdo_pad_o,`
115			`tdo_padoe_o,`
116
117			`// TAP states`
118			`shift_dr_o,`
119			`pause_dr_o,`
120			`update_dr_o,`
121			`capture_dr_o,`
122
123			`// Select signals for boundary scan or mbist`
124			`extest_select_o,`
125			`sample_preload_select_o,`
126			`mbist_select_o,`
127			`debug_select_o,`
128
129			`// TDO signal that is connected to TDI of sub-modules.`
130			`tdo_o,`
131
132			`// TDI signals from sub-modules`
133			`debug_tdi_i, // from debug module`
134			`bs_chain_tdi_i, // from Boundary Scan Chain`
135			`mbist_tdi_i // from Mbist Chain`
136			`);`
137
138
139			`// JTAG pins`
140			`input tms_pad_i; // JTAG test mode select pad`
141			`input tck_pad_i; // JTAG test clock pad`
142			`input trst_pad_i; // JTAG test reset pad`
143			`input tdi_pad_i; // JTAG test data input pad`
144			`output tdo_pad_o; // JTAG test data output pad`
145			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
146
147			`// TAP states`
148			`output shift_dr_o;`
149			`output pause_dr_o;`
150			`output update_dr_o;`
151			`output capture_dr_o;`
152
153			`// Select signals for boundary scan or mbist`
154			`output extest_select_o;`
155			`output sample_preload_select_o;`
156			`output mbist_select_o;`
157			`output debug_select_o;`
158
159			`// TDO signal that is connected to TDI of sub-modules.`
160			`output tdo_o;`
161
162			`// TDI signals from sub-modules`
163			`input debug_tdi_i; // from debug module`
164			`input bs_chain_tdi_i; // from Boundary Scan Chain`
165			`input mbist_tdi_i; // from Mbist Chain`
166
167			`// Registers`
168			`reg test_logic_reset;`
169			`reg run_test_idle;`
170			`reg select_dr_scan;`
171			`reg capture_dr;`
172			`reg shift_dr;`
173			`reg exit1_dr;`
174			`reg pause_dr;`
175			`reg exit2_dr;`
176			`reg update_dr;`
177			`reg select_ir_scan;`
178			`reg capture_ir;`
179			`reg shift_ir, shift_ir_neg;`
180			`reg exit1_ir;`
181			`reg pause_ir;`
182			`reg exit2_ir;`
183			`reg update_ir;`
184			`reg extest_select;`
185			`reg sample_preload_select;`
186			`reg idcode_select;`
187			`reg mbist_select;`
188			`reg debug_select;`
189			`reg bypass_select;`
190			`reg tdo_pad_o;`
191			`reg tdo_padoe_o;`
192			`reg tms_q1, tms_q2, tms_q3, tms_q4;`
193			`wire tms_reset;`
194
195			`assign tdo_o = tdi_pad_i;`
196			`assign shift_dr_o = shift_dr;`
197			`assign pause_dr_o = pause_dr;`
198			`assign update_dr_o = update_dr;`
199			`assign capture_dr_o = capture_dr;`
200
201			`assign extest_select_o = extest_select;`
202			`assign sample_preload_select_o = sample_preload_select;`
203			`assign mbist_select_o = mbist_select;`
204			`assign debug_select_o = debug_select;`
205
206
207			`always @ (posedge tck_pad_i)`
208			`begin`
209	360	julius	`tms_q1 <= tms_pad_i;`
210			`tms_q2 <= tms_q1;`
211			`tms_q3 <= tms_q2;`
212			`tms_q4 <= tms_q3;`
213	6	julius	`end`
214
215
216			`assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset`
217
218
219			`/**********************************************************************************`
220			`* *`
221			`* TAP State Machine: Fully JTAG compliant *`
222			`* *`
223			`**********************************************************************************/`
224
225			`// test_logic_reset state`
226			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
227			`begin`
228			`if(trst_pad_i)`
229	360	julius	`test_logic_reset<= 1'b1;`
230	6	julius	`else if (tms_reset)`
231	360	julius	`test_logic_reset<= 1'b1;`
232	6	julius	`else`
233			`begin`
234			`if(tms_pad_i & (test_logic_reset \| select_ir_scan))`
235	360	julius	`test_logic_reset<= 1'b1;`
236	6	julius	`else`
237	360	julius	`test_logic_reset<= 1'b0;`
238	6	julius	`end`
239			`end`
240
241			`// run_test_idle state`
242			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
243			`begin`
244			`if(trst_pad_i)`
245	360	julius	`run_test_idle<= 1'b0;`
246	6	julius	`else if (tms_reset)`
247	360	julius	`run_test_idle<= 1'b0;`
248	6	julius	`else`
249			`if(~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
250	360	julius	`run_test_idle<= 1'b1;`
251	6	julius	`else`
252	360	julius	`run_test_idle<= 1'b0;`
253	6	julius	`end`
254
255			`// select_dr_scan state`
256			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
257			`begin`
258			`if(trst_pad_i)`
259	360	julius	`select_dr_scan<= 1'b0;`
260	6	julius	`else if (tms_reset)`
261	360	julius	`select_dr_scan<= 1'b0;`
262	6	julius	`else`
263			`if(tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
264	360	julius	`select_dr_scan<= 1'b1;`
265	6	julius	`else`
266	360	julius	`select_dr_scan<= 1'b0;`
267	6	julius	`end`
268
269			`// capture_dr state`
270			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
271			`begin`
272			`if(trst_pad_i)`
273	360	julius	`capture_dr<= 1'b0;`
274	6	julius	`else if (tms_reset)`
275	360	julius	`capture_dr<= 1'b0;`
276	6	julius	`else`
277			`if(~tms_pad_i & select_dr_scan)`
278	360	julius	`capture_dr<= 1'b1;`
279	6	julius	`else`
280	360	julius	`capture_dr<= 1'b0;`
281	6	julius	`end`
282
283			`// shift_dr state`
284			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
285			`begin`
286			`if(trst_pad_i)`
287	360	julius	`shift_dr<= 1'b0;`
288	6	julius	`else if (tms_reset)`
289	360	julius	`shift_dr<= 1'b0;`
290	6	julius	`else`
291			`if(~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
292	360	julius	`shift_dr<= 1'b1;`
293	6	julius	`else`
294	360	julius	`shift_dr<= 1'b0;`
295	6	julius	`end`
296
297			`// exit1_dr state`
298			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
299			`begin`
300			`if(trst_pad_i)`
301	360	julius	`exit1_dr<= 1'b0;`
302	6	julius	`else if (tms_reset)`
303	360	julius	`exit1_dr<= 1'b0;`
304	6	julius	`else`
305			`if(tms_pad_i & (capture_dr \| shift_dr))`
306	360	julius	`exit1_dr<= 1'b1;`
307	6	julius	`else`
308	360	julius	`exit1_dr<= 1'b0;`
309	6	julius	`end`
310
311			`// pause_dr state`
312			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
313			`begin`
314			`if(trst_pad_i)`
315	360	julius	`pause_dr<= 1'b0;`
316	6	julius	`else if (tms_reset)`
317	360	julius	`pause_dr<= 1'b0;`
318	6	julius	`else`
319			`if(~tms_pad_i & (exit1_dr \| pause_dr))`
320	360	julius	`pause_dr<= 1'b1;`
321	6	julius	`else`
322	360	julius	`pause_dr<= 1'b0;`
323	6	julius	`end`
324
325			`// exit2_dr state`
326			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
327			`begin`
328			`if(trst_pad_i)`
329	360	julius	`exit2_dr<= 1'b0;`
330	6	julius	`else if (tms_reset)`
331	360	julius	`exit2_dr<= 1'b0;`
332	6	julius	`else`
333			`if(tms_pad_i & pause_dr)`
334	360	julius	`exit2_dr<= 1'b1;`
335	6	julius	`else`
336	360	julius	`exit2_dr<= 1'b0;`
337	6	julius	`end`
338
339			`// update_dr state`
340			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
341			`begin`
342			`if(trst_pad_i)`
343	360	julius	`update_dr<= 1'b0;`
344	6	julius	`else if (tms_reset)`
345	360	julius	`update_dr<= 1'b0;`
346	6	julius	`else`
347			`if(tms_pad_i & (exit1_dr \| exit2_dr))`
348	360	julius	`update_dr<= 1'b1;`
349	6	julius	`else`
350	360	julius	`update_dr<= 1'b0;`
351	6	julius	`end`
352
353			`// select_ir_scan state`
354			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
355			`begin`
356			`if(trst_pad_i)`
357	360	julius	`select_ir_scan<= 1'b0;`
358	6	julius	`else if (tms_reset)`
359	360	julius	`select_ir_scan<= 1'b0;`
360	6	julius	`else`
361			`if(tms_pad_i & select_dr_scan)`
362	360	julius	`select_ir_scan<= 1'b1;`
363	6	julius	`else`
364	360	julius	`select_ir_scan<= 1'b0;`
365	6	julius	`end`
366
367			`// capture_ir state`
368			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
369			`begin`
370			`if(trst_pad_i)`
371	360	julius	`capture_ir<= 1'b0;`
372	6	julius	`else if (tms_reset)`
373	360	julius	`capture_ir<= 1'b0;`
374	6	julius	`else`
375			`if(~tms_pad_i & select_ir_scan)`
376	360	julius	`capture_ir<= 1'b1;`
377	6	julius	`else`
378	360	julius	`capture_ir<= 1'b0;`
379	6	julius	`end`
380
381			`// shift_ir state`
382			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
383			`begin`
384			`if(trst_pad_i)`
385	360	julius	`shift_ir<= 1'b0;`
386	6	julius	`else if (tms_reset)`
387	360	julius	`shift_ir<= 1'b0;`
388	6	julius	`else`
389			`if(~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
390	360	julius	`shift_ir<= 1'b1;`
391	6	julius	`else`
392	360	julius	`shift_ir<= 1'b0;`
393	6	julius	`end`
394
395			`// exit1_ir state`
396			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
397			`begin`
398			`if(trst_pad_i)`
399	360	julius	`exit1_ir<= 1'b0;`
400	6	julius	`else if (tms_reset)`
401	360	julius	`exit1_ir<= 1'b0;`
402	6	julius	`else`
403			`if(tms_pad_i & (capture_ir \| shift_ir))`
404	360	julius	`exit1_ir<= 1'b1;`
405	6	julius	`else`
406	360	julius	`exit1_ir<= 1'b0;`
407	6	julius	`end`
408
409			`// pause_ir state`
410			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
411			`begin`
412			`if(trst_pad_i)`
413	360	julius	`pause_ir<= 1'b0;`
414	6	julius	`else if (tms_reset)`
415	360	julius	`pause_ir<= 1'b0;`
416	6	julius	`else`
417			`if(~tms_pad_i & (exit1_ir \| pause_ir))`
418	360	julius	`pause_ir<= 1'b1;`
419	6	julius	`else`
420	360	julius	`pause_ir<= 1'b0;`
421	6	julius	`end`
422
423			`// exit2_ir state`
424			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
425			`begin`
426			`if(trst_pad_i)`
427	360	julius	`exit2_ir<= 1'b0;`
428	6	julius	`else if (tms_reset)`
429	360	julius	`exit2_ir<= 1'b0;`
430	6	julius	`else`
431			`if(tms_pad_i & pause_ir)`
432	360	julius	`exit2_ir<= 1'b1;`
433	6	julius	`else`
434	360	julius	`exit2_ir<= 1'b0;`
435	6	julius	`end`
436
437			`// update_ir state`
438			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
439			`begin`
440			`if(trst_pad_i)`
441	360	julius	`update_ir<= 1'b0;`
442	6	julius	`else if (tms_reset)`
443	360	julius	`update_ir<= 1'b0;`
444	6	julius	`else`
445			`if(tms_pad_i & (exit1_ir \| exit2_ir))`
446	360	julius	`update_ir<= 1'b1;`
447	6	julius	`else`
448	360	julius	`update_ir<= 1'b0;`
449	6	julius	`end`
450
451			`/**********************************************************************************`
452			`* *`
453			`* End: TAP State Machine *`
454			`* *`
455			`**********************************************************************************/`
456
457
458
459			`/**********************************************************************************`
460			`* *`
461			`* jtag_ir: JTAG Instruction Register *`
462			`* *`
463			`**********************************************************************************/`
464			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
465			reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
466			`reg instruction_tdo;`
467
468			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
469			`begin`
470			`if(trst_pad_i)`
471	360	julius	jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
472	6	julius	`else if(capture_ir)`
473	360	julius	`jtag_ir <= 4'b0101; // This value is fixed for easier fault detection`
474	6	julius	`else if(shift_ir)`
475	360	julius	jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
476	6	julius	`end`
477
478			`always @ (negedge tck_pad_i)`
479			`begin`
480	360	julius	`instruction_tdo <= jtag_ir[0];`
481	6	julius	`end`
482			`/**********************************************************************************`
483			`* *`
484			`* End: jtag_ir *`
485			`* *`
486			`**********************************************************************************/`
487
488
489
490			`/**********************************************************************************`
491			`* *`
492			`* idcode logic *`
493			`* *`
494			`**********************************************************************************/`
495			`reg [31:0] idcode_reg;`
496			`reg idcode_tdo;`
497
498			`always @ (posedge tck_pad_i)`
499			`begin`
500			`if(idcode_select & shift_dr)`

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