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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_tag.v] - Blame information for rev 476

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC TAG RAMs                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of data cache tag rams.                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_dc_tag.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_tag(
        // Clock and reset
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, tag_v, tag, dirty
);
 
parameter dw = `OR1200_DCTAG_W+1;
parameter aw = `OR1200_DCTAG;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input                           we;
input   [dw-1:0]         datain;
output                          tag_v;
output  [dw-3:0]         tag;
output                          dirty;
 
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// Instantiation of TAG RAM block
//
// Data widths are tag width plus one for valid
`ifdef OR1200_DC_1W_4KB
   or1200_spram #
     (
      .aw(8),
      .dw(`OR1200_DCTAG_W + 1)
      )
`endif
`ifdef OR1200_DC_1W_8KB
   or1200_spram #
     (
      .aw(9),
      .dw(`OR1200_DCTAG_W + 1)
      )
`endif
`ifdef OR1200_DC_1W_16KB
   or1200_spram #
     (
      .aw(10),
      .dw(`OR1200_DCTAG_W + 1)
      )
`endif
   dc_tag0
     (
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_si_i),
      .mbist_so_o(mbist_so_o),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .clk(clk),
      .ce(en),
      .we(we),
      .addr(addr),
      .di(datain),
      .doq({tag, tag_v, dirty})
      );
`endif
 
endmodule // or1200_dc_tag

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC TAG RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instatiation of data cache tag rams. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_dc_tag.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Coding style changed.`
48			`//`
49
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53			`include "or1200_defines.v"
54
55			`module or1200_dc_tag(`
56			`// Clock and reset`
57			`clk, rst,`
58
59			`ifdef OR1200_BIST
60			`// RAM BIST`
61			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
62			`endif
63
64			`// Internal i/f`
65			`addr, en, we, datain, tag_v, tag, dirty`
66			`);`
67
68			parameter dw = `OR1200_DCTAG_W+1;
69			parameter aw = `OR1200_DCTAG;
70
71			`//`
72			`// I/O`
73			`//`
74			`input clk;`
75			`input rst;`
76			`input [aw-1:0] addr;`
77			`input en;`
78			`input we;`
79			`input [dw-1:0] datain;`
80			`output tag_v;`
81			`output [dw-3:0] tag;`
82			`output dirty;`
83
84
85			`ifdef OR1200_BIST
86			`//`
87			`// RAM BIST`
88			`//`
89			`input mbist_si_i;`
90			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
91			`output mbist_so_o;`
92			`endif
93
94			`ifdef OR1200_NO_DC
95
96			`//`
97			`// Data cache not implemented`
98			`//`
99			`assign tag = {dw-1{1'b0}};`
100			`assign tag_v = 1'b0;`
101			`ifdef OR1200_BIST
102			`assign mbist_so_o = mbist_si_i;`
103			`endif
104
105			`else
106
107			`//`
108			`// Instantiation of TAG RAM block`
109			`//`
110	476	julius	`// Data widths are tag width plus one for valid`
111	350	julius	`ifdef OR1200_DC_1W_4KB
112			`or1200_spram #`
113			`(`
114			`.aw(8),`
115	476	julius	.dw(`OR1200_DCTAG_W + 1)
116	350	julius	`)`
117			`endif
118			`ifdef OR1200_DC_1W_8KB
119			`or1200_spram #`
120			`(`
121			`.aw(9),`
122	476	julius	.dw(`OR1200_DCTAG_W + 1)
123	350	julius	`)`
124			`endif
125	476	julius	`ifdef OR1200_DC_1W_16KB
126			`or1200_spram #`
127			`(`
128			`.aw(10),`
129			.dw(`OR1200_DCTAG_W + 1)
130			`)`
131			`endif
132	350	julius	`dc_tag0`
133			`(`
134			`ifdef OR1200_BIST
135			`// RAM BIST`
136			`.mbist_si_i(mbist_si_i),`
137			`.mbist_so_o(mbist_so_o),`
138			`.mbist_ctrl_i(mbist_ctrl_i),`
139			`endif
140			`.clk(clk),`
141			`.ce(en),`
142			`.we(we),`
143			`.addr(addr),`
144			`.di(datain),`
145			`.doq({tag, tag_v, dirty})`
146			`);`
147			`endif
148
149			`endmodule // or1200_dc_tag`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_tag.v] - Blame information for rev 476