URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_except.v] - Blame information for rev 502

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Exception logic                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Handles all OR1K exceptions inside CPU block.               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_except.v,v $
//
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
 
//
// Exception recognition and sequencing
//
 
module or1200_except
  (
   // Clock and reset
   clk, rst,
 
   // Internal i/f
   sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
   sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
   sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
   if_stall,  if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
   extend_flush, except_flushpipe, except_type, except_start, except_started,
   except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
   spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
   du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
   abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee
 
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           sig_ibuserr;
input                           sig_dbuserr;
input                           sig_illegal;
input                           sig_align;
input                           sig_range;
input                           sig_dtlbmiss;
input                           sig_dmmufault;
input                           sig_int;
input                           sig_syscall;
input                           sig_trap;
input                           sig_itlbmiss;
input                           sig_immufault;
input                           sig_tick;
input                           sig_fp;
input                           fpcsr_fpee;
input                           ex_branch_taken;
input                           genpc_freeze;
input                           id_freeze;
input                           ex_freeze;
input                           wb_freeze;
input                           if_stall;
input   [31:0]           if_pc;
output  [31:0]           id_pc;
output  [31:0]      ex_pc;
output  [31:0]      wb_pc;
input   [31:0]           datain;
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
input   [24:0]                       du_dmr1;
input                   du_hwbkpt;
input                   du_hwbkpt_ls_r;
input                           epcr_we;
input                           eear_we;
input                           esr_we;
input                           pc_we;
output  [31:0]                   epcr;
output  [31:0]                   eear;
output  [`OR1200_SR_WIDTH-1:0]   esr;
input   [`OR1200_SR_WIDTH-1:0]   to_sr;
input                           sr_we;
input   [`OR1200_SR_WIDTH-1:0]   sr;
input   [31:0]                   lsu_addr;
input                   id_flushpipe;
input                   ex_flushpipe;
output                          except_flushpipe;
output                          extend_flush;
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
output                          except_start;
output                          except_started;
output  [13:0]           except_stop;
output  [13:0]           except_trig;
input                           ex_void;
input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
output  [31:0]                   spr_dat_ppc;
output  [31:0]                   spr_dat_npc;
output                          abort_ex;
output              abort_mvspr;
input                           icpu_ack_i;
input                           icpu_err_i;
input                           dcpu_ack_i;
input                           dcpu_err_i;
 
//
// Internal regs and wires
//
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type /* verilator public */;
reg     [31:0]                   id_pc /* verilator public */;
reg                 id_pc_val;
reg     [31:0]                   ex_pc /* verilator public */;
reg                 ex_pc_val;
reg     [31:0]                   wb_pc /* verilator public */;
reg [31:0]          dl_pc;
reg     [31:0]                   epcr;
reg     [31:0]                   eear;
reg     [`OR1200_SR_WIDTH-1:0]           esr;
reg     [2:0]                    id_exceptflags;
reg     [2:0]                    ex_exceptflags;
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
reg                             extend_flush;
reg                             extend_flush_last;
reg                             ex_dslot /* verilator public */;
reg                             delayed1_ex_dslot;
reg                             delayed2_ex_dslot;
wire                            except_started;
wire                            except_flushpipe /* verilator public */;
reg     [2:0]                    delayed_iee;
reg     [2:0]                    delayed_tee;
wire                            int_pending;
wire                            tick_pending;
wire                            fp_pending;
wire                            range_pending;
 
reg trace_trap      ;
reg ex_freeze_prev;
reg sr_ted_prev;
reg dsr_te_prev;
reg dmr1_st_prev    ;
reg dmr1_bt_prev    ;
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
 
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
 
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
 
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
                                (sr_we & to_sr[`OR1200_SR_IEE]))
                    & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
                     & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
 
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
                                  (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
                      & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
                      & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
 
assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
                    & ~ex_dslot;
 
`ifdef OR1200_IMPL_OVE
assign range_pending =  sig_range & sr[`OR1200_SR_OVE] & ~ex_freeze &
                       ~ex_branch_taken & ~ex_dslot;
`else
assign range_pending = 0;
`endif
 
// Abort write into RF by load & other instructions   
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
                  sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
                                 & !sr_ted & !dsr_te);
 
// abort spr read/writes   
assign abort_mvspr  = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
                                     & !sr_ted & !dsr_te) ;
assign spr_dat_ppc = wb_pc;
 
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
 
//
// Order defines exception detection priority
//
assign except_trig = {
                      ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
                      ex_exceptflags[0]  & ~du_dsr[`OR1200_DU_DSR_IPFE],
                      ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                      sig_illegal       & ~du_dsr[`OR1200_DU_DSR_IIE],
                      sig_align         & ~du_dsr[`OR1200_DU_DSR_AE],
                      sig_dtlbmiss      & ~du_dsr[`OR1200_DU_DSR_DME],
                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],
                      sig_syscall       & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
                      sig_dmmufault     & ~du_dsr[`OR1200_DU_DSR_DPFE],
                      sig_dbuserr       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                      range_pending     & ~du_dsr[`OR1200_DU_DSR_RE],
                      fp_pending        & ~du_dsr[`OR1200_DU_DSR_FPE],
                      int_pending       & ~du_dsr[`OR1200_DU_DSR_IE],
                      tick_pending      & ~du_dsr[`OR1200_DU_DSR_TTE]
                      };
 
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
`ifdef OR1200_DU_DMR1_ST
    ||  dmr1_st
`endif
`ifdef OR1200_DU_DMR1_BT
    ||  ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
`endif
    );
 
assign except_stop = {
                        tick_pending            & du_dsr[`OR1200_DU_DSR_TTE],
                        int_pending             & du_dsr[`OR1200_DU_DSR_IE],
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
                        range_pending           & du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],
                        fp_pending              & du_dsr[`OR1200_DU_DSR_FPE],
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                trace_trap  <=  1'b0 ;
        end
        else if (!(trace_trap && !ex_pc_val)) begin
                trace_trap  <=  trace_cond & !dsr_te & !sr_ted ;
        end
end
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
        ex_freeze_prev  <=  1'b0 ;
        sr_ted_prev     <=  1'b0 ;
        dsr_te_prev     <=  1'b0 ;
        dmr1_st_prev    <=  1'b0 ;
        dmr1_bt_prev    <=  1'b0 ;
    end
    else begin
        ex_freeze_prev  <=  ex_freeze ;
        if (!ex_freeze_prev || ex_void) begin
            sr_ted_prev     <=  sr     [`OR1200_SR_TED    ] ;
            dsr_te_prev     <=  du_dsr [`OR1200_DU_DSR_TE ] ;
            dmr1_st_prev    <=  du_dmr1[`OR1200_DU_DMR1_ST] ;
            dmr1_bt_prev    <=  du_dmr1[`OR1200_DU_DMR1_BT] ;
        end
    end
end
 
`ifdef verilator
   // Function to access wb_pc (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [31:0] get_wb_pc;
      // verilator public
      get_wb_pc = wb_pc;
   endfunction // get_wb_pc
 
   // Function to access id_pc (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [31:0] get_id_pc;
      // verilator public
      get_id_pc = id_pc;
   endfunction // get_id_pc
 
   // Function to access ex_pc (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [31:0] get_ex_pc;
      // verilator public
      get_ex_pc = ex_pc;
   endfunction // get_ex_pc
   // Function to access except_type[3:0] (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [3:0] get_except_type;
      // verilator public
      get_except_type = except_type;
   endfunction // get_except_type
 
`endif
 
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                id_pc <=  32'd0;
        id_pc_val <=  1'b0 ;
                id_exceptflags <=  3'b000;
        end
        else if (id_flushpipe) begin
        id_pc_val <=  1'b0 ;
                id_exceptflags <=  3'b000;
        end
        else if (!id_freeze) begin
                id_pc <=  if_pc;
        id_pc_val <=  1'b1 ;
                id_exceptflags <=  { sig_ibuserr, sig_itlbmiss, sig_immufault };
        end
end
 
//
// delayed_iee
//
// SR[IEE] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_iee
// together with SR[IEE] enables interrupts once
// pipeline is again ready.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
        if (rst == `OR1200_RST_VALUE)
                delayed_iee <=  3'b000;
        else if (!sr[`OR1200_SR_IEE])
                delayed_iee <=  3'b000;
        else
                delayed_iee <=  {delayed_iee[1:0], 1'b1};
 
//
// delayed_tee
//
// SR[TEE] should not enable tick exceptions right away
// when it is restored with l.rfe. Instead delayed_tee
// together with SR[TEE] enables tick exceptions once
// pipeline is again ready.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
        if (rst == `OR1200_RST_VALUE)
                delayed_tee <=  3'b000;
        else if (!sr[`OR1200_SR_TEE])
                delayed_tee <=  3'b000;
        else
                delayed_tee <=  {delayed_tee[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                ex_dslot <=  1'b0;
                ex_pc <=  32'd0;
                ex_pc_val <=  1'b0 ;
                ex_exceptflags <=  3'b000;
                delayed1_ex_dslot <=  1'b0;
                delayed2_ex_dslot <=  1'b0;
        end
        else if (ex_flushpipe) begin
                ex_dslot <=  1'b0;
                ex_pc_val <=  1'b0 ;
                ex_exceptflags <=  3'b000;
                delayed1_ex_dslot <=  1'b0;
                delayed2_ex_dslot <=  1'b0;
        end
        else if (!ex_freeze & id_freeze) begin
                ex_dslot <=  1'b0;
                ex_pc <=  id_pc;
                ex_pc_val <=  id_pc_val ;
                ex_exceptflags <=  3'b000;
                delayed1_ex_dslot <=  ex_dslot;
                delayed2_ex_dslot <=  delayed1_ex_dslot;
        end
        else if (!ex_freeze) begin
                ex_dslot <=  ex_branch_taken;
                ex_pc <=  id_pc;
                ex_pc_val <=  id_pc_val ;
                ex_exceptflags <=  id_exceptflags;
                delayed1_ex_dslot <=  ex_dslot;
                delayed2_ex_dslot <=  delayed1_ex_dslot;
        end
end
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                wb_pc <=  32'd0;
        dl_pc <=  32'd0;
        end
        else if (!wb_freeze) begin
                wb_pc <=  ex_pc;
        dl_pc <=  wb_pc;
        end
end
 
//
// We have started execution of exception handler:
//  1. Asserted for 3 clock cycles
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & ~|state;
 
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
//  1. Asserted in next clock cycle after exception is recognized
//
   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
         state <=  `OR1200_EXCEPTFSM_IDLE;
         except_type <=  `OR1200_EXCEPT_NONE;
         extend_flush <=  1'b0;
         epcr <=  32'b0;
         eear <=  32'b0;
         esr <=  {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
         extend_flush_last <=  1'b0;
      end
      else begin
`ifdef OR1200_CASE_DEFAULT
         case (state)   // synopsys parallel_case
`else
           case (state) // synopsys full_case parallel_case
`endif
             `OR1200_EXCEPTFSM_IDLE:
               if (except_flushpipe) begin
                  state <=  `OR1200_EXCEPTFSM_FLU1;
                  extend_flush <=  1'b1;
                  esr <=  sr_we ? to_sr : sr;
                  casez (except_trig)
`ifdef OR1200_EXCEPT_ITLBMISS
                    14'b1?_????_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ITLBMISS;
                       eear <=  ex_dslot ?
                               ex_pc : ex_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_IPF
                    14'b01_????_????_????: begin
                       except_type <=  `OR1200_EXCEPT_IPF;
                       eear <=  ex_dslot ?
                               ex_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_BUSERR
                    14'b00_1???_????_????: begin        // Insn. Bus Error
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       eear <=  ex_dslot ?
                               wb_pc : ex_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
                    14'b00_01??_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ILLEGAL;
                       eear <=  ex_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_ALIGN
                    14'b00_001?_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ALIGN;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
                    14'b00_0001_????_????: begin
                       except_type <=  `OR1200_EXCEPT_DTLBMISS;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_TRAP
                    14'b00_0000_1???_????: begin
                       except_type <=  `OR1200_EXCEPT_TRAP;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
                    14'b00_0000_01??_????: begin
                       except_type <=  `OR1200_EXCEPT_SYSCALL;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_DPF
                    14'b00_0000_001?_????: begin
                       except_type <=  `OR1200_EXCEPT_DPF;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_BUSERR
                    14'b00_0000_0001_????: begin        // Data Bus Error
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_RANGE
                    14'b00_0000_0000_1???: begin
                       except_type <=  `OR1200_EXCEPT_RANGE;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_FLOAT
                    14'b00_0000_0000_01??: begin
                       except_type <=  `OR1200_EXCEPT_FLOAT;
                       epcr <=  id_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_INT
                    14'b00_0000_0000_001?: begin
                       except_type <=  `OR1200_EXCEPT_INT;
                       epcr <=  id_pc;
                    end
`endif
`ifdef OR1200_EXCEPT_TICK
                    14'b00_0000_0000_0001: begin
                       except_type <=  `OR1200_EXCEPT_TICK;
                       epcr <=  id_pc;
                    end
`endif
                    default:
                      except_type <=  `OR1200_EXCEPT_NONE;
                  endcase
               end
               else if (pc_we) begin
                  state <=  `OR1200_EXCEPTFSM_FLU1;
                  extend_flush <=  1'b1;
               end
               else begin
                  if (epcr_we)
                    epcr <=  datain;
                  if (eear_we)
                    eear <=  datain;
                  if (esr_we)
                    esr <=  {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
               end
             `OR1200_EXCEPTFSM_FLU1:
               if (icpu_ack_i | icpu_err_i | genpc_freeze)
                 state <=  `OR1200_EXCEPTFSM_FLU2;
             `OR1200_EXCEPTFSM_FLU2:
`ifdef OR1200_EXCEPT_TRAP
               if (except_type == `OR1200_EXCEPT_TRAP) begin
                  state <=  `OR1200_EXCEPTFSM_IDLE;
                  extend_flush <=  1'b0;
                  extend_flush_last <=  1'b0;
                  except_type <=  `OR1200_EXCEPT_NONE;
               end
               else
`endif
                 state <=  `OR1200_EXCEPTFSM_FLU3;
             `OR1200_EXCEPTFSM_FLU3:
               begin
                  state <=  `OR1200_EXCEPTFSM_FLU4;
               end
             `OR1200_EXCEPTFSM_FLU4: begin
                state <=  `OR1200_EXCEPTFSM_FLU5;
                extend_flush <=  1'b0;
                extend_flush_last <=  1'b0; // damjan
             end
`ifdef OR1200_CASE_DEFAULT
             default: begin
`else
                `OR1200_EXCEPTFSM_FLU5: begin
`endif
                   if (!if_stall && !id_freeze) begin
                      state <=  `OR1200_EXCEPTFSM_IDLE;
                      except_type <=  `OR1200_EXCEPT_NONE;
                      extend_flush_last <=  1'b0;
                   end
                end
           endcase
         end
   end
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Exception logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Handles all OR1K exceptions inside CPU block. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_except.v,v $`
45			`//`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// Major update:`
48			`// Structure reordered and bugs fixed.`
49
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53			`include "or1200_defines.v"
54
55			`define OR1200_EXCEPTFSM_WIDTH 3
56			`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
57			`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
58			`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
59			`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
60			`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
61			`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
62
63			`//`
64			`// Exception recognition and sequencing`
65			`//`
66
67			`module or1200_except`
68			`(`
69			`// Clock and reset`
70			`clk, rst,`
71
72			`// Internal i/f`
73			`sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,`
74			`sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,`
75			`sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,`
76			`if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,`
77			`extend_flush, except_flushpipe, except_type, except_start, except_started,`
78			`except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,`
79			`spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,`
80			`du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,`
81			`abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee`
82
83			`);`
84
85			`//`
86			`// I/O`
87			`//`
88			`input clk;`
89			`input rst;`
90			`input sig_ibuserr;`
91			`input sig_dbuserr;`
92			`input sig_illegal;`
93			`input sig_align;`
94			`input sig_range;`
95			`input sig_dtlbmiss;`
96			`input sig_dmmufault;`
97			`input sig_int;`
98			`input sig_syscall;`
99			`input sig_trap;`
100			`input sig_itlbmiss;`
101			`input sig_immufault;`
102			`input sig_tick;`
103			`input sig_fp;`
104			`input fpcsr_fpee;`
105			`input ex_branch_taken;`
106			`input genpc_freeze;`
107			`input id_freeze;`
108			`input ex_freeze;`
109			`input wb_freeze;`
110			`input if_stall;`
111			`input [31:0] if_pc;`
112			`output [31:0] id_pc;`
113			`output [31:0] ex_pc;`
114			`output [31:0] wb_pc;`
115			`input [31:0] datain;`
116			input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
117			`input [24:0] du_dmr1;`
118			`input du_hwbkpt;`
119			`input du_hwbkpt_ls_r;`
120			`input epcr_we;`
121			`input eear_we;`
122			`input esr_we;`
123			`input pc_we;`
124			`output [31:0] epcr;`
125			`output [31:0] eear;`
126			output [`OR1200_SR_WIDTH-1:0] esr;
127			input [`OR1200_SR_WIDTH-1:0] to_sr;
128			`input sr_we;`
129			input [`OR1200_SR_WIDTH-1:0] sr;
130			`input [31:0] lsu_addr;`
131			`input id_flushpipe;`
132			`input ex_flushpipe;`
133			`output except_flushpipe;`
134			`output extend_flush;`
135			output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
136			`output except_start;`
137			`output except_started;`
138			`output [13:0] except_stop;`
139			`output [13:0] except_trig;`
140			`input ex_void;`
141			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
142			`output [31:0] spr_dat_ppc;`
143			`output [31:0] spr_dat_npc;`
144			`output abort_ex;`
145			`output abort_mvspr;`
146			`input icpu_ack_i;`
147			`input icpu_err_i;`
148			`input dcpu_ack_i;`
149			`input dcpu_err_i;`
150
151			`//`
152			`// Internal regs and wires`
153			`//`
154	353	julius	reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
155			`reg [31:0] id_pc /* verilator public */;`
156	350	julius	`reg id_pc_val;`
157	353	julius	`reg [31:0] ex_pc /* verilator public */;`
158	350	julius	`reg ex_pc_val;`
159	353	julius	`reg [31:0] wb_pc /* verilator public */;`
160	350	julius	`reg [31:0] dl_pc;`
161			`reg [31:0] epcr;`
162			`reg [31:0] eear;`
163			reg [`OR1200_SR_WIDTH-1:0] esr;
164			`reg [2:0] id_exceptflags;`
165			`reg [2:0] ex_exceptflags;`
166			reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
167			`reg extend_flush;`
168			`reg extend_flush_last;`
169	353	julius	`reg ex_dslot /* verilator public */;`
170	350	julius	`reg delayed1_ex_dslot;`
171			`reg delayed2_ex_dslot;`
172			`wire except_started;`
173	353	julius	`wire except_flushpipe /* verilator public */;`
174	350	julius	`reg [2:0] delayed_iee;`
175			`reg [2:0] delayed_tee;`
176			`wire int_pending;`
177			`wire tick_pending;`
178			`wire fp_pending;`
179	502	julius	`wire range_pending;`
180
181	350	julius	`reg trace_trap ;`
182			`reg ex_freeze_prev;`
183			`reg sr_ted_prev;`
184			`reg dsr_te_prev;`
185			`reg dmr1_st_prev ;`
186			`reg dmr1_bt_prev ;`
187			wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
188			wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
189			wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
190			wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
191
192			`//`
193			`// Simple combinatorial logic`
194			`//`
195			`assign except_started = extend_flush & except_start;`
196
197			assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
198
199			assign int_pending = sig_int & (sr[`OR1200_SR_IEE] \|
200			(sr_we & to_sr[`OR1200_SR_IEE]))
201			`& id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken`
202			& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
203
204			assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] \|
205			(sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
206			`& delayed_tee[2] & ~ex_freeze & ~ex_branch_taken`
207			& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
208
209			`assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken`
210			`& ~ex_dslot;`
211	502	julius
212			`ifdef OR1200_IMPL_OVE
213			assign range_pending = sig_range & sr[`OR1200_SR_OVE] & ~ex_freeze &
214			`~ex_branch_taken & ~ex_dslot;`
215			`else
216			`assign range_pending = 0;`
217			`endif
218	350	julius
219			`// Abort write into RF by load & other instructions`
220			`assign abort_ex = sig_dbuserr \| sig_dmmufault \| sig_dtlbmiss \| sig_align \|`
221			`sig_illegal \| ((du_hwbkpt \| trace_trap) & ex_pc_val`
222			`& !sr_ted & !dsr_te);`
223
224			`// abort spr read/writes`
225			`assign abort_mvspr = sig_illegal \| ((du_hwbkpt \| trace_trap) & ex_pc_val`
226			`& !sr_ted & !dsr_te) ;`
227			`assign spr_dat_ppc = wb_pc;`
228
229			`assign spr_dat_npc = ex_void ? id_pc : ex_pc;`
230
231			`//`
232			`// Order defines exception detection priority`
233			`//`
234			`assign except_trig = {`
235			ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
236			ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
237			ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
238			sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
239			sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
240			sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
241			sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
242			sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
243			sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
244			sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
245	502	julius	range_pending & ~du_dsr[`OR1200_DU_DSR_RE],
246	350	julius	fp_pending & ~du_dsr[`OR1200_DU_DSR_FPE],
247			int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
248			tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
249			`};`
250
251			`wire trace_cond = !ex_freeze && !ex_void && (1'b0`
252			`ifdef OR1200_DU_DMR1_ST
253			`\|\| dmr1_st`
254			`endif
255			`ifdef OR1200_DU_DMR1_BT
256			\|\| ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
257			`endif
258			`);`
259
260			`assign except_stop = {`
261			tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
262			int_pending & du_dsr[`OR1200_DU_DSR_IE],
263			ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
264			ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
265			ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
266			sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
267			sig_align & du_dsr[`OR1200_DU_DSR_AE],
268			sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
269			sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
270			sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
271	502	julius	range_pending & du_dsr[`OR1200_DU_DSR_RE],
272	350	julius	sig_trap & du_dsr[`OR1200_DU_DSR_TE],
273			fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
274			sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
275			`};`
276
277	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
278			if (rst == `OR1200_RST_VALUE) begin
279	350	julius	`trace_trap <= 1'b0 ;`
280			`end`
281			`else if (!(trace_trap && !ex_pc_val)) begin`
282			`trace_trap <= trace_cond & !dsr_te & !sr_ted ;`
283			`end`
284			`end`
285
286	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
287			if (rst == `OR1200_RST_VALUE) begin
288	350	julius	`ex_freeze_prev <= 1'b0 ;`
289			`sr_ted_prev <= 1'b0 ;`
290			`dsr_te_prev <= 1'b0 ;`
291			`dmr1_st_prev <= 1'b0 ;`
292			`dmr1_bt_prev <= 1'b0 ;`
293			`end`
294			`else begin`
295			`ex_freeze_prev <= ex_freeze ;`
296			`if (!ex_freeze_prev \|\| ex_void) begin`
297			sr_ted_prev <= sr [`OR1200_SR_TED ] ;
298			dsr_te_prev <= du_dsr [`OR1200_DU_DSR_TE ] ;
299			dmr1_st_prev <= du_dmr1[`OR1200_DU_DMR1_ST] ;
300			dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
301			`end`
302			`end`
303			`end`
304
305	353	julius	`ifdef verilator
306			`// Function to access wb_pc (for Verilator). Have to hide this from`
307			`// simulator, since functions with no inputs are not allowed in IEEE`
308			`// 1364-2001.`
309			`function [31:0] get_wb_pc;`
310			`// verilator public`
311			`get_wb_pc = wb_pc;`
312			`endfunction // get_wb_pc`
313
314			`// Function to access id_pc (for Verilator). Have to hide this from`
315			`// simulator, since functions with no inputs are not allowed in IEEE`
316			`// 1364-2001.`
317			`function [31:0] get_id_pc;`
318			`// verilator public`
319			`get_id_pc = id_pc;`
320			`endfunction // get_id_pc`
321
322			`// Function to access ex_pc (for Verilator). Have to hide this from`
323			`// simulator, since functions with no inputs are not allowed in IEEE`
324			`// 1364-2001.`
325			`function [31:0] get_ex_pc;`
326			`// verilator public`
327			`get_ex_pc = ex_pc;`
328			`endfunction // get_ex_pc`
329			`// Function to access except_type[3:0] (for Verilator). Have to hide this from`
330			`// simulator, since functions with no inputs are not allowed in IEEE`
331			`// 1364-2001.`
332			`function [3:0] get_except_type;`
333			`// verilator public`
334			`get_except_type = except_type;`
335			`endfunction // get_except_type`
336
337			`endif
338
339
340	350	julius	`//`
341			`// PC and Exception flags pipelines`
342			`//`
343	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
344			if (rst == `OR1200_RST_VALUE) begin
345	350	julius	`id_pc <= 32'd0;`
346			`id_pc_val <= 1'b0 ;`
347			`id_exceptflags <= 3'b000;`
348			`end`
349			`else if (id_flushpipe) begin`
350			`id_pc_val <= 1'b0 ;`
351			`id_exceptflags <= 3'b000;`
352			`end`
353			`else if (!id_freeze) begin`
354			`id_pc <= if_pc;`
355			`id_pc_val <= 1'b1 ;`
356			`id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault };`
357			`end`
358			`end`
359
360			`//`
361			`// delayed_iee`
362			`//`
363			`// SR[IEE] should not enable interrupts right away`
364			`// when it is restored with l.rfe. Instead delayed_iee`
365			`// together with SR[IEE] enables interrupts once`
366			`// pipeline is again ready.`
367			`//`
368	358	julius	always @(`OR1200_RST_EVENT rst or posedge clk)
369			if (rst == `OR1200_RST_VALUE)
370	350	julius	`delayed_iee <= 3'b000;`
371			else if (!sr[`OR1200_SR_IEE])
372			`delayed_iee <= 3'b000;`
373			`else`
374			`delayed_iee <= {delayed_iee[1:0], 1'b1};`
375
376			`//`
377			`// delayed_tee`
378			`//`
379			`// SR[TEE] should not enable tick exceptions right away`
380			`// when it is restored with l.rfe. Instead delayed_tee`
381			`// together with SR[TEE] enables tick exceptions once`
382			`// pipeline is again ready.`
383			`//`
384	358	julius	always @(`OR1200_RST_EVENT rst or posedge clk)
385			if (rst == `OR1200_RST_VALUE)
386	350	julius	`delayed_tee <= 3'b000;`
387			else if (!sr[`OR1200_SR_TEE])
388			`delayed_tee <= 3'b000;`
389			`else`
390			`delayed_tee <= {delayed_tee[1:0], 1'b1};`
391
392			`//`
393			`// PC and Exception flags pipelines`
394			`//`
395	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
396			if (rst == `OR1200_RST_VALUE) begin
397	350	julius	`ex_dslot <= 1'b0;`
398			`ex_pc <= 32'd0;`
399			`ex_pc_val <= 1'b0 ;`
400			`ex_exceptflags <= 3'b000;`
401			`delayed1_ex_dslot <= 1'b0;`
402			`delayed2_ex_dslot <= 1'b0;`
403			`end`
404			`else if (ex_flushpipe) begin`
405			`ex_dslot <= 1'b0;`
406			`ex_pc_val <= 1'b0 ;`
407			`ex_exceptflags <= 3'b000;`
408			`delayed1_ex_dslot <= 1'b0;`
409			`delayed2_ex_dslot <= 1'b0;`
410			`end`
411			`else if (!ex_freeze & id_freeze) begin`
412			`ex_dslot <= 1'b0;`
413			`ex_pc <= id_pc;`
414			`ex_pc_val <= id_pc_val ;`
415			`ex_exceptflags <= 3'b000;`
416			`delayed1_ex_dslot <= ex_dslot;`
417			`delayed2_ex_dslot <= delayed1_ex_dslot;`
418			`end`
419			`else if (!ex_freeze) begin`
420			`ex_dslot <= ex_branch_taken;`
421			`ex_pc <= id_pc;`
422			`ex_pc_val <= id_pc_val ;`
423			`ex_exceptflags <= id_exceptflags;`
424			`delayed1_ex_dslot <= ex_dslot;`
425			`delayed2_ex_dslot <= delayed1_ex_dslot;`
426			`end`
427			`end`
428
429			`//`
430			`// PC and Exception flags pipelines`
431			`//`
432	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
433			if (rst == `OR1200_RST_VALUE) begin
434	350	julius	`wb_pc <= 32'd0;`
435			`dl_pc <= 32'd0;`
436			`end`
437			`else if (!wb_freeze) begin`
438			`wb_pc <= ex_pc;`
439			`dl_pc <= wb_pc;`
440			`end`
441			`end`
442
443			`//`
444			`// We have started execution of exception handler:`
445			`// 1. Asserted for 3 clock cycles`
446			`// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler`
447			`//`
448			`assign except_flushpipe = \|except_trig & ~\|state;`
449
450			`//`
451			`// Exception FSM that sequences execution of exception handler`
452			`//`
453			`// except_type signals which exception handler we start fetching in:`
454			`// 1. Asserted in next clock cycle after exception is recognized`
455			`//`
456	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
457			if (rst == `OR1200_RST_VALUE) begin
458	350	julius	state <= `OR1200_EXCEPTFSM_IDLE;
459			except_type <= `OR1200_EXCEPT_NONE;
460			`extend_flush <= 1'b0;`
461			`epcr <= 32'b0;`
462			`eear <= 32'b0;`
463			esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
464			`extend_flush_last <= 1'b0;`
465			`end`
466			`else begin`
467			`ifdef OR1200_CASE_DEFAULT
468			`case (state) // synopsys parallel_case`
469			`else
470			`case (state) // synopsys full_case parallel_case`
471			`endif
472			`OR1200_EXCEPTFSM_IDLE:
473			`if (except_flushpipe) begin`
474			state <= `OR1200_EXCEPTFSM_FLU1;
475			`extend_flush <= 1'b1;`
476			`esr <= sr_we ? to_sr : sr;`
477	363	julius	`casez (except_trig)`
478	350	julius	`ifdef OR1200_EXCEPT_ITLBMISS
479	363	julius	`14'b1?_????_????_????: begin`
480	350	julius	except_type <= `OR1200_EXCEPT_ITLBMISS;
481			`eear <= ex_dslot ?`
482			`ex_pc : ex_pc;`
483			`epcr <= ex_dslot ?`
484			`wb_pc : ex_pc;`
485			`end`
486			`endif
487			`ifdef OR1200_EXCEPT_IPF
488	363	julius	`14'b01_????_????_????: begin`
489	350	julius	except_type <= `OR1200_EXCEPT_IPF;
490			`eear <= ex_dslot ?`
491			`ex_pc : delayed1_ex_dslot ?`
492			`id_pc : delayed2_ex_dslot ?`
493			`id_pc : id_pc;`
494			`epcr <= ex_dslot ?`
495			`wb_pc : delayed1_ex_dslot ?`
496			`id_pc : delayed2_ex_dslot ?`
497			`id_pc : id_pc;`
498			`end`
499			`endif
500			`ifdef OR1200_EXCEPT_BUSERR

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_except.v] - Blame information for rev 502