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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [raminfr.v] - Blame information for rev 360

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1 6 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  raminfr.v                                                   ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  Inferrable Distributed RAM for FIFOs                        ////
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////                                                              ////
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////  Known problems (limits):                                    ////
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////  None                .                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Nothing so far.                                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////                                                              ////
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////  Created:        2002/07/22                                  ////
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////  Last Updated:   2002/07/22                                  ////
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////                  (See log for the revision history)          ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2002/07/22 23:02:23  gorban
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// Bug Fixes:
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//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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//   Problem reported by Kenny.Tung.
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//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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//  * Made FIFO's as general inferrable memory where possible.
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//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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//  * Added optional baudrate output (baud_o).
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//  This is identical to BAUDOUT* signal on 16550 chip.
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//  It outputs 16xbit_clock_rate - the divided clock.
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//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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//Following is the Verilog code for a dual-port RAM with asynchronous read. 
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module raminfr
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        (clk, we, a, dpra, di, dpo);
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parameter addr_width = 4;
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parameter data_width = 8;
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parameter depth = 16;
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input clk;
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input we;
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input  [addr_width-1:0] a;
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input  [addr_width-1:0] dpra;
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input  [data_width-1:0] di;
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//output [data_width-1:0] spo;   
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output [data_width-1:0] dpo;
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reg    [data_width-1:0] ram [depth-1:0];
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wire [data_width-1:0] dpo;
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wire  [data_width-1:0] di;
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wire  [addr_width-1:0] a;
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wire  [addr_width-1:0] dpra;
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  always @(posedge clk) begin
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    if (we)
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      ram[a] <= di;
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  end
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//  assign spo = ram[a];   
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  assign dpo = ram[dpra];
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endmodule
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