OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [HCTxPortArbiter.v] - Blame information for rev 408

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
 
2
// File        : ../RTL/hostController/hctxportarbiter.v
3
// Generated   : 11/10/06 05:37:22
4
// From        : ../RTL/hostController/hctxportarbiter.asf
5
// By          : FSM2VHDL ver. 5.0.0.9
6
 
7
//////////////////////////////////////////////////////////////////////
8
////                                                              ////
9
//// hctxPortArbiter
10
////                                                              ////
11
//// This file is part of the usbhostslave opencores effort.
12
//// http://www.opencores.org/cores/usbhostslave/                 ////
13
////                                                              ////
14
//// Module Description:                                          ////
15
//// 
16
////                                                              ////
17
//// To Do:                                                       ////
18
//// 
19
////                                                              ////
20
//// Author(s):                                                   ////
21
//// - Steve Fielding, sfielding@base2designs.com                 ////
22
////                                                              ////
23
//////////////////////////////////////////////////////////////////////
24
////                                                              ////
25
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
26
////                                                              ////
27
//// This source file may be used and distributed without         ////
28
//// restriction provided that this copyright statement is not    ////
29
//// removed from the file and that any derivative work contains  ////
30
//// the original copyright notice and the associated disclaimer. ////
31
////                                                              ////
32
//// This source file is free software; you can redistribute it   ////
33
//// and/or modify it under the terms of the GNU Lesser General   ////
34
//// Public License as published by the Free Software Foundation; ////
35
//// either version 2.1 of the License, or (at your option) any   ////
36
//// later version.                                               ////
37
////                                                              ////
38
//// This source is distributed in the hope that it will be       ////
39
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
40
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
41
//// PURPOSE. See the GNU Lesser General Public License for more  ////
42
//// details.                                                     ////
43
////                                                              ////
44
//// You should have received a copy of the GNU Lesser General    ////
45
//// Public License along with this source; if not, download it   ////
46
//// from http://www.opencores.org/lgpl.shtml                     ////
47
////                                                              ////
48
//////////////////////////////////////////////////////////////////////
49
//
50
`include "timescale.v"
51
 
52
module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
53
input   [7:0] SOFCntlCntl;
54
input   [7:0] SOFCntlData;
55
input   SOFCntlReq;
56
input   SOFCntlWEn;
57
input   clk;
58
input   [7:0] directCntlCntl;
59
input   [7:0] directCntlData;
60
input   directCntlReq;
61
input   directCntlWEn;
62
input   rst;
63
input   [7:0] sendPacketCntl;
64
input   [7:0] sendPacketData;
65
input   sendPacketReq;
66
input   sendPacketWEn;
67
output  [7:0] HCTxPortCntl;
68
output  [7:0] HCTxPortData;
69
output  HCTxPortWEnable;
70
output  SOFCntlGnt;
71
output  directCntlGnt;
72
output  sendPacketGnt;
73
 
74
reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
75
reg     [7:0] HCTxPortData, next_HCTxPortData;
76
reg     HCTxPortWEnable, next_HCTxPortWEnable;
77
wire    [7:0] SOFCntlCntl;
78
wire    [7:0] SOFCntlData;
79
reg     SOFCntlGnt, next_SOFCntlGnt;
80
wire    SOFCntlReq;
81
wire    SOFCntlWEn;
82
wire    clk;
83
wire    [7:0] directCntlCntl;
84
wire    [7:0] directCntlData;
85
reg     directCntlGnt, next_directCntlGnt;
86
wire    directCntlReq;
87
wire    directCntlWEn;
88
wire    rst;
89
wire    [7:0] sendPacketCntl;
90
wire    [7:0] sendPacketData;
91
reg     sendPacketGnt, next_sendPacketGnt;
92
wire    sendPacketReq;
93
wire    sendPacketWEn;
94
 
95
 
96
// Constants
97
`define DIRECT_CTRL_MUX 2'b10
98
`define SEND_PACKET_MUX 2'b00
99
`define SOF_CTRL_MUX 2'b01
100
// diagram signals declarations
101
reg  [1:0]muxCntl, next_muxCntl;
102
 
103
// BINARY ENCODED state machine: HCTxArb
104
// State codes definitions:
105
`define START_HARB 3'b000
106
`define WAIT_REQ 3'b001
107
`define SEND_SOF 3'b010
108
`define SEND_PACKET 3'b011
109
`define DIRECT_CONTROL 3'b100
110
 
111
reg [2:0] CurrState_HCTxArb;
112
reg [2:0] NextState_HCTxArb;
113
 
114
// Diagram actions (continuous assignments allowed only: assign ...)
115
 
116
// SOFController/directContol/sendPacket mux
117
always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
118
                                 directCntlWEn or directCntlData or directCntlCntl or
119
                  directCntlWEn or directCntlData or directCntlCntl or
120
                                 sendPacketWEn or sendPacketData or sendPacketCntl)
121
begin
122
case (muxCntl)
123
    `SOF_CTRL_MUX :
124
    begin
125
        HCTxPortWEnable <= SOFCntlWEn;
126
        HCTxPortData <= SOFCntlData;
127
        HCTxPortCntl <= SOFCntlCntl;
128
    end
129
    `DIRECT_CTRL_MUX :
130
    begin
131
        HCTxPortWEnable <= directCntlWEn;
132
        HCTxPortData <= directCntlData;
133
        HCTxPortCntl <= directCntlCntl;
134
    end
135
    `SEND_PACKET_MUX :
136
    begin
137
        HCTxPortWEnable <= sendPacketWEn;
138
        HCTxPortData <= sendPacketData;
139
        HCTxPortCntl <= sendPacketCntl;
140
    end
141
    default :
142
    begin
143
        HCTxPortWEnable <= 1'b0;
144
        HCTxPortData <= 8'h00;
145
        HCTxPortCntl <= 8'h00;
146
    end
147
endcase
148
end
149
 
150
//--------------------------------------------------------------------
151
// Machine: HCTxArb
152
//--------------------------------------------------------------------
153
//----------------------------------
154
// Next State Logic (combinatorial)
155
//----------------------------------
156
always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb)
157
begin : HCTxArb_NextState
158
  NextState_HCTxArb <= CurrState_HCTxArb;
159
  // Set default values for outputs and signals
160
  next_SOFCntlGnt <= SOFCntlGnt;
161
  next_muxCntl <= muxCntl;
162
  next_sendPacketGnt <= sendPacketGnt;
163
  next_directCntlGnt <= directCntlGnt;
164
  case (CurrState_HCTxArb)
165
    `START_HARB:
166
      NextState_HCTxArb <= `WAIT_REQ;
167
    `WAIT_REQ:
168
      if (SOFCntlReq == 1'b1)
169
      begin
170
        NextState_HCTxArb <= `SEND_SOF;
171
        next_SOFCntlGnt <= 1'b1;
172
        next_muxCntl <= `SOF_CTRL_MUX;
173
      end
174
      else if (sendPacketReq == 1'b1)
175
      begin
176
        NextState_HCTxArb <= `SEND_PACKET;
177
        next_sendPacketGnt <= 1'b1;
178
        next_muxCntl <= `SEND_PACKET_MUX;
179
      end
180
      else if (directCntlReq == 1'b1)
181
      begin
182
        NextState_HCTxArb <= `DIRECT_CONTROL;
183
        next_directCntlGnt <= 1'b1;
184
        next_muxCntl <= `DIRECT_CTRL_MUX;
185
      end
186
    `SEND_SOF:
187
      if (SOFCntlReq == 1'b0)
188
      begin
189
        NextState_HCTxArb <= `WAIT_REQ;
190
        next_SOFCntlGnt <= 1'b0;
191
      end
192
    `SEND_PACKET:
193
      if (sendPacketReq == 1'b0)
194
      begin
195
        NextState_HCTxArb <= `WAIT_REQ;
196
        next_sendPacketGnt <= 1'b0;
197
      end
198
    `DIRECT_CONTROL:
199
      if (directCntlReq == 1'b0)
200
      begin
201
        NextState_HCTxArb <= `WAIT_REQ;
202
        next_directCntlGnt <= 1'b0;
203
      end
204
  endcase
205
end
206
 
207
//----------------------------------
208
// Current State Logic (sequential)
209
//----------------------------------
210
always @ (posedge clk)
211
begin : HCTxArb_CurrentState
212
  if (rst)
213
    CurrState_HCTxArb <= `START_HARB;
214
  else
215
    CurrState_HCTxArb <= NextState_HCTxArb;
216
end
217
 
218
//----------------------------------
219
// Registered outputs logic
220
//----------------------------------
221
always @ (posedge clk)
222
begin : HCTxArb_RegOutput
223
  if (rst)
224
  begin
225
    muxCntl <= 2'b00;
226
    SOFCntlGnt <= 1'b0;
227
    sendPacketGnt <= 1'b0;
228
    directCntlGnt <= 1'b0;
229
  end
230
  else
231
  begin
232
    muxCntl <= next_muxCntl;
233
    SOFCntlGnt <= next_SOFCntlGnt;
234
    sendPacketGnt <= next_sendPacketGnt;
235
    directCntlGnt <= next_directCntlGnt;
236
  end
237
end
238
 
239
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.