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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [hostSlaveMux.v] - Blame information for rev 408

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// hostSlaveMux.v                                               ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// Controls the select line for the mux that enables the sharing
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//// of a single SerialInterfaceEgine between the hostController
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//// and slaveController
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//// Also a dumping area for any features common to host and slave 
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//// operation. That is reset control and version number report.
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module hostSlaveMux (
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  SIEPortCtrlInToSIE,
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  SIEPortCtrlInFromHost,
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  SIEPortCtrlInFromSlave,
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  SIEPortDataInToSIE,
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  SIEPortDataInFromHost,
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  SIEPortDataInFromSlave,
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  SIEPortWEnToSIE,
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  SIEPortWEnFromHost,
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  SIEPortWEnFromSlave,
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  fullSpeedPolarityToSIE,
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  fullSpeedPolarityFromHost,
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  fullSpeedPolarityFromSlave,
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  fullSpeedBitRateToSIE,
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  fullSpeedBitRateFromHost,
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  fullSpeedBitRateFromSlave,
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  noActivityTimeOutEnableToSIE,
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  noActivityTimeOutEnableFromHost,
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  noActivityTimeOutEnableFromSlave,
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  dataIn,
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  dataOut,
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  address,
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  writeEn,
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  strobe_i,
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  busClk,
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  usbClk,
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  hostSlaveMuxSel,
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  rstFromWire,
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  rstSyncToBusClkOut,
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  rstSyncToUsbClkOut
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);
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output [7:0] SIEPortCtrlInToSIE;
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input [7:0] SIEPortCtrlInFromHost;
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input [7:0] SIEPortCtrlInFromSlave;
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output [7:0] SIEPortDataInToSIE;
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input [7:0] SIEPortDataInFromHost;
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input [7:0] SIEPortDataInFromSlave;
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output SIEPortWEnToSIE;
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input SIEPortWEnFromHost;
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input SIEPortWEnFromSlave;
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output fullSpeedPolarityToSIE;
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input fullSpeedPolarityFromHost;
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input fullSpeedPolarityFromSlave;
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output fullSpeedBitRateToSIE;
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input fullSpeedBitRateFromHost;
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input fullSpeedBitRateFromSlave;
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output noActivityTimeOutEnableToSIE;
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input noActivityTimeOutEnableFromHost;
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input noActivityTimeOutEnableFromSlave;
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//hostSlaveMuxBI
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input [7:0] dataIn;
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input address;
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input writeEn;
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input strobe_i;
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input busClk;
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input usbClk;
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input rstFromWire;
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output rstSyncToBusClkOut;
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output rstSyncToUsbClkOut;
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output [7:0] dataOut;
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input hostSlaveMuxSel;
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reg [7:0] SIEPortCtrlInToSIE;
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wire [7:0] SIEPortCtrlInFromHost;
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wire [7:0] SIEPortCtrlInFromSlave;
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reg [7:0] SIEPortDataInToSIE;
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wire [7:0] SIEPortDataInFromHost;
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wire [7:0] SIEPortDataInFromSlave;
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reg SIEPortWEnToSIE;
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wire SIEPortWEnFromHost;
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wire SIEPortWEnFromSlave;
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reg fullSpeedPolarityToSIE;
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wire fullSpeedPolarityFromHost;
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wire fullSpeedPolarityFromSlave;
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reg fullSpeedBitRateToSIE;
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wire fullSpeedBitRateFromHost;
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wire fullSpeedBitRateFromSlave;
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reg noActivityTimeOutEnableToSIE;
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wire noActivityTimeOutEnableFromHost;
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wire noActivityTimeOutEnableFromSlave;
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//hostSlaveMuxBI
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wire [7:0] dataIn;
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wire address;
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wire writeEn;
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wire strobe_i;
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wire busClk;
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wire usbClk;
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wire rstSyncToBusClkOut;
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wire rstSyncToUsbClkOut;
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wire rstFromWire;
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wire [7:0] dataOut;
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wire hostSlaveMuxSel;
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//internal wires and regs
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wire hostMode;
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always @(hostMode or
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  SIEPortCtrlInFromHost or
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  SIEPortCtrlInFromSlave or
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  SIEPortDataInFromHost or
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  SIEPortDataInFromSlave or
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  SIEPortWEnFromHost or
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  SIEPortWEnFromSlave or
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  fullSpeedPolarityFromHost or
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  fullSpeedPolarityFromSlave or
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  fullSpeedBitRateFromHost or
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  fullSpeedBitRateFromSlave or
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  noActivityTimeOutEnableFromHost or
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  noActivityTimeOutEnableFromSlave)
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begin
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  if (hostMode == 1'b1)
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  begin
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    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
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    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
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    SIEPortWEnToSIE <= SIEPortWEnFromHost;
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    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
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    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
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    noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromHost;
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  end
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  else
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  begin
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    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
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    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
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    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
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    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
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    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
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    noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromSlave;
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  end
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end
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hostSlaveMuxBI u_hostSlaveMuxBI (
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  .dataIn(dataIn),
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  .dataOut(dataOut),
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  .address(address),
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  .writeEn(writeEn),
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  .strobe_i(strobe_i),
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  .busClk(busClk),
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  .usbClk(usbClk),
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  .hostMode(hostMode),
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  .hostSlaveMuxSel(hostSlaveMuxSel),
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  .rstFromWire(rstFromWire),
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  .rstSyncToBusClkOut(rstSyncToBusClkOut),
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  .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
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endmodule

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