OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [hostSlaveMuxBI.v] - Blame information for rev 408

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// hostSlaveMuxBI.v                                             ////
4
////                                                              ////
5
//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
7
////                                                              ////
8
//// Module Description:                                          ////
9
//// 
10
////                                                              ////
11
//// To Do:                                                       ////
12
//// 
13
////                                                              ////
14
//// Author(s):                                                   ////
15
//// - Steve Fielding, sfielding@base2designs.com                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from <http://www.opencores.org/lgpl.shtml>                   ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
`include "usbhostslave_hostslave_h.v"
46
 
47
module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
48
  hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
49
 
50
input [7:0] dataIn;
51
input address;
52
input writeEn;
53
input strobe_i;
54
input busClk;
55
input usbClk;
56
output [7:0] dataOut;
57
input hostSlaveMuxSel;
58
output hostMode;
59
input rstFromWire;
60
output rstSyncToBusClkOut;
61
output rstSyncToUsbClkOut;
62
 
63
wire [7:0] dataIn;
64
wire address;
65
wire writeEn;
66
wire strobe_i;
67
wire busClk;
68
wire usbClk;
69
reg [7:0] dataOut;
70
wire hostSlaveMuxSel;
71
reg hostMode;
72
wire rstFromWire;
73
reg rstSyncToBusClkOut;
74
reg rstSyncToUsbClkOut;
75
 
76
//internal wire and regs
77
reg [5:0] rstShift;
78
reg rstFromBus;
79
reg rstSyncToUsbClkFirst;
80
 
81
//sync write demux
82
always @(posedge busClk)
83
begin
84
  if (rstSyncToBusClkOut == 1'b1)
85
    hostMode <= 1'b0;
86
  else begin
87
    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
88
      hostMode <= dataIn[0];
89
    end
90
    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
91
      rstFromBus <= 1'b1;
92
    else
93
      rstFromBus <= 1'b0;
94
end
95
 
96
// async read mux
97
always @(address or hostMode)
98
begin
99
  case (address)
100
    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
101
    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
102
  endcase
103
end
104
 
105
// reset control
106
//generate 'rstSyncToBusClk'
107
//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
108
always @(posedge busClk) begin
109
  if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
110
    rstShift <= 6'b111111;
111
  else
112
    rstShift <= {1'b0, rstShift[5:1]};
113
end
114
 
115
always @(rstShift)
116
  rstSyncToBusClkOut <= rstShift[0];
117
 
118
// double sync across clock domains to generate 'forceEmptySyncToWrClk'
119
always @(posedge usbClk) begin
120
    rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
121
    rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
122
end
123
 
124
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.