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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [processTxByte.v] - Blame information for rev 408

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2
// File        : ../RTL/serialInterfaceEngine/processTxByte.v
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// Generated   : 11/10/06 05:37:23
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// From        : ../RTL/serialInterfaceEngine/processTxByte.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// processTxByte
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbhostslave_serialinterfaceengine_h.v"
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`include "usbhostslave_constants_h.v"
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module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
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input   [1:0] JBit;
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input   [1:0] KBit;
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input   [7:0] TxByteCtrlIn;
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input   TxByteFullSpeedRateIn;
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input   [7:0] TxByteIn;
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input   USBWireGnt;
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input   USBWireRdy;
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input   clk;
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input   processTxByteWEn;
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input   rst;
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output  USBWireCtrl;
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output  [1:0] USBWireData;
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output  USBWireFullSpeedRate;
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output  USBWireReq;
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output  USBWireWEn;
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output  processTxByteRdy;
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wire    [1:0] JBit;
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wire    [1:0] KBit;
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wire    [7:0] TxByteCtrlIn;
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wire    TxByteFullSpeedRateIn;
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wire    [7:0] TxByteIn;
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reg     USBWireCtrl, next_USBWireCtrl;
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reg     [1:0] USBWireData, next_USBWireData;
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reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
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wire    USBWireGnt;
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wire    USBWireRdy;
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reg     USBWireReq, next_USBWireReq;
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reg     USBWireWEn, next_USBWireWEn;
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wire    clk;
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reg     processTxByteRdy, next_processTxByteRdy;
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wire    processTxByteWEn;
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wire    rst;
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89
// diagram signals declarations
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reg  [1:0]TXLineState, next_TXLineState;
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reg  [3:0]TXOneCount, next_TXOneCount;
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reg  [7:0]TxByteCtrl, next_TxByteCtrl;
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reg  TxByteFullSpeedRate, next_TxByteFullSpeedRate;
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reg  [7:0]TxByte, next_TxByte;
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reg  [3:0]i, next_i;
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97
// BINARY ENCODED state machine: prcTxB
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// State codes definitions:
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`define START_PTBY 5'b00000
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`define PTBY_WAIT_EN 5'b00001
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`define SEND_BYTE_UPDATE_BYTE 5'b00010
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`define SEND_BYTE_WAIT_RDY 5'b00011
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`define SEND_BYTE_CHK 5'b00100
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`define SEND_BYTE_BIT_STUFF 5'b00101
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`define SEND_BYTE_WAIT_RDY2 5'b00110
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`define SEND_BYTE_CHK_FIN 5'b00111
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`define PTBY_WAIT_GNT 5'b01000
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`define STOP_SND_SE0_2 5'b01001
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`define STOP_SND_SE0_1 5'b01010
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`define STOP_CHK 5'b01011
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`define STOP_SND_J 5'b01100
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`define STOP_SND_IDLE 5'b01101
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`define STOP_FIN 5'b01110
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`define WAIT_RDY_WIRE 5'b01111
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`define WAIT_RDY_PKT 5'b10000
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`define LS_START_SND_IDLE3 5'b10001
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`define LS_START_SND_J1 5'b10010
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`define LS_START_SND_IDLE1 5'b10011
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`define LS_START_SND_IDLE2 5'b10100
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`define LS_START_FIN 5'b10101
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`define LS_START_W_RDY1 5'b10110
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`define LS_START_W_RDY2 5'b10111
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`define LS_START_W_RDY3 5'b11000
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`define STOP_W_RDY1 5'b11001
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`define STOP_W_RDY2 5'b11010
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`define STOP_W_RDY3 5'b11011
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`define STOP_W_RDY4 5'b11100
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129
reg [4:0] CurrState_prcTxB;
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reg [4:0] NextState_prcTxB;
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//--------------------------------------------------------------------
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// Machine: prcTxB
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
139
always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
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begin : prcTxB_NextState
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  NextState_prcTxB <= CurrState_prcTxB;
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  // Set default values for outputs and signals
143
  next_processTxByteRdy <= processTxByteRdy;
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  next_USBWireData <= USBWireData;
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  next_USBWireCtrl <= USBWireCtrl;
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  next_USBWireReq <= USBWireReq;
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  next_USBWireWEn <= USBWireWEn;
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  next_i <= i;
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  next_TxByte <= TxByte;
150
  next_TxByteCtrl <= TxByteCtrl;
151
  next_TXLineState <= TXLineState;
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  next_TXOneCount <= TXOneCount;
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  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
154
  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
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  case (CurrState_prcTxB)
156
    `START_PTBY:
157
    begin
158
      next_processTxByteRdy <= 1'b0;
159
      next_USBWireData <= 2'b00;
160
      next_USBWireCtrl <= `TRI_STATE;
161
      next_USBWireReq <= 1'b0;
162
      next_USBWireWEn <= 1'b0;
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      next_i <= 4'h0;
164
      next_TxByte <= 8'h00;
165
      next_TxByteCtrl <= 8'h00;
166
      next_TXLineState <= 2'b0;
167
      next_TXOneCount <= 4'h0;
168
      next_USBWireFullSpeedRate <= 1'b0;
169
      next_TxByteFullSpeedRate <= 1'b0;
170
      NextState_prcTxB <= `PTBY_WAIT_EN;
171
    end
172
    `PTBY_WAIT_EN:
173
    begin
174
      next_processTxByteRdy <= 1'b1;
175
      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
176
      begin
177
        NextState_prcTxB <= `PTBY_WAIT_GNT;
178
        next_processTxByteRdy <= 1'b0;
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        next_TxByte <= TxByteIn;
180
        next_TxByteCtrl <= TxByteCtrlIn;
181
        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
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        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
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        next_TXOneCount <= 4'h0;
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        next_TXLineState <= JBit;
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        next_USBWireReq <= 1'b1;
186
      end
187
      else if (processTxByteWEn == 1'b1)
188
      begin
189
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
190
        next_processTxByteRdy <= 1'b0;
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        next_TxByte <= TxByteIn;
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        next_TxByteCtrl <= TxByteCtrlIn;
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        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
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        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
195
        next_i <= 4'h0;
196
      end
197
    end
198
    `PTBY_WAIT_GNT:
199
      if (USBWireGnt == 1'b1)
200
        NextState_prcTxB <= `WAIT_RDY_WIRE;
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    `WAIT_RDY_WIRE:
202
      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))
203
        NextState_prcTxB <= `LS_START_SND_IDLE1;
204
      else if (USBWireRdy == 1'b1)
205
      begin
206
        NextState_prcTxB <= `WAIT_RDY_PKT;
207
        //actively drive the first J bit
208
        next_USBWireData <= JBit;
209
        next_USBWireCtrl <= `DRIVE;
210
        next_USBWireWEn <= 1'b1;
211
      end
212
    `WAIT_RDY_PKT:
213
    begin
214
      next_USBWireWEn <= 1'b0;
215
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
216
      next_i <= 4'h0;
217
    end
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    `SEND_BYTE_UPDATE_BYTE:
219
    begin
220
      next_i <= i + 1'b1;
221
      next_TxByte <= {1'b0, TxByte[7:1] };
222
      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
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        next_TXOneCount <= TXOneCount + 1'b1;
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          //increment 'TXOneCount'
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      else                                        //else this is a zero bit
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      begin
227
        next_TXOneCount <= 4'h0;
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          //reset 'TXOneCount'
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          if (TXLineState == JBit)
230
          next_TXLineState <= KBit;
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              //toggle the line state
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          else
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          next_TXLineState <= JBit;
234
      end
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      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
236
    end
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    `SEND_BYTE_WAIT_RDY:
238
      if (USBWireRdy == 1'b1)
239
      begin
240
        NextState_prcTxB <= `SEND_BYTE_CHK;
241
        next_USBWireWEn <= 1'b1;
242
        next_USBWireData <= TXLineState;
243
        next_USBWireCtrl <= `DRIVE;
244
      end
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    `SEND_BYTE_CHK:
246
    begin
247
      next_USBWireWEn <= 1'b0;
248
      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
249
        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
250
      else if (i != 4'h8)
251
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
252
      else
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        NextState_prcTxB <= `STOP_CHK;
254
    end
255
    `SEND_BYTE_BIT_STUFF:
256
    begin
257
      next_TXOneCount <= 4'h0;
258
      //reset 'TXOneCount'
259
      if (TXLineState == JBit)
260
        next_TXLineState <= KBit;
261
          //toggle the line state
262
      else
263
        next_TXLineState <= JBit;
264
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
265
    end
266
    `SEND_BYTE_WAIT_RDY2:
267
      if (USBWireRdy == 1'b1)
268
      begin
269
        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
270
        next_USBWireWEn <= 1'b1;
271
        next_USBWireData <= TXLineState;
272
        next_USBWireCtrl <= `DRIVE;
273
      end
274
    `SEND_BYTE_CHK_FIN:
275
    begin
276
      next_USBWireWEn <= 1'b0;
277
      if (i == 4'h8)
278
        NextState_prcTxB <= `STOP_CHK;
279
      else
280
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
281
    end
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    `STOP_SND_SE0_2:
283
    begin
284
      next_USBWireWEn <= 1'b0;
285
      NextState_prcTxB <= `STOP_W_RDY2;
286
    end
287
    `STOP_SND_SE0_1:
288
      NextState_prcTxB <= `STOP_W_RDY1;
289
    `STOP_CHK:
290
      if (TxByteCtrl == `DATA_STOP)
291
        NextState_prcTxB <= `STOP_SND_SE0_1;
292
      else
293
        NextState_prcTxB <= `PTBY_WAIT_EN;
294
    `STOP_SND_J:
295
    begin
296
      next_USBWireWEn <= 1'b0;
297
      NextState_prcTxB <= `STOP_W_RDY3;
298
    end
299
    `STOP_SND_IDLE:
300
    begin
301
      next_USBWireWEn <= 1'b0;
302
      NextState_prcTxB <= `STOP_W_RDY4;
303
    end
304
    `STOP_FIN:
305
    begin
306
      next_USBWireWEn <= 1'b0;
307
      next_USBWireReq <= 1'b0;
308
      //release the wire
309
      NextState_prcTxB <= `PTBY_WAIT_EN;
310
    end
311
    `STOP_W_RDY1:
312
      if (USBWireRdy == 1'b1)
313
      begin
314
        NextState_prcTxB <= `STOP_SND_SE0_2;
315
        next_USBWireWEn <= 1'b1;
316
        next_USBWireData <= `SE0;
317
        next_USBWireCtrl <= `DRIVE;
318
      end
319
    `STOP_W_RDY2:
320
      if (USBWireRdy == 1'b1)
321
      begin
322
        NextState_prcTxB <= `STOP_SND_J;
323
        next_USBWireWEn <= 1'b1;
324
        next_USBWireData <= `SE0;
325
        next_USBWireCtrl <= `DRIVE;
326
      end
327
    `STOP_W_RDY3:
328
      if (USBWireRdy == 1'b1)
329
      begin
330
        NextState_prcTxB <= `STOP_SND_IDLE;
331
        next_USBWireWEn <= 1'b1;
332
        next_USBWireData <= JBit;
333
        next_USBWireCtrl <= `DRIVE;
334
      end
335
    `STOP_W_RDY4:
336
      if (USBWireRdy == 1'b1)
337
      begin
338
        NextState_prcTxB <= `STOP_FIN;
339
        next_USBWireWEn <= 1'b1;
340
        next_USBWireData <= JBit;
341
        next_USBWireCtrl <= `TRI_STATE;
342
      end
343
    `LS_START_SND_IDLE3:
344
    begin
345
      next_USBWireWEn <= 1'b0;
346
      NextState_prcTxB <= `LS_START_W_RDY2;
347
    end
348
    `LS_START_SND_J1:
349
    begin
350
      next_USBWireWEn <= 1'b0;
351
      NextState_prcTxB <= `LS_START_W_RDY3;
352
    end
353
    `LS_START_SND_IDLE1:
354
      if (USBWireRdy == 1'b1)
355
      begin
356
        NextState_prcTxB <= `LS_START_SND_IDLE2;
357
        next_USBWireWEn <= 1'b1;
358
        next_USBWireData <= JBit;
359
        next_USBWireCtrl <= `TRI_STATE;
360
      end
361
    `LS_START_SND_IDLE2:
362
    begin
363
      next_USBWireWEn <= 1'b0;
364
      NextState_prcTxB <= `LS_START_W_RDY1;
365
    end
366
    `LS_START_FIN:
367
    begin
368
      next_USBWireWEn <= 1'b0;
369
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
370
      next_i <= 4'h0;
371
    end
372
    `LS_START_W_RDY1:
373
      if (USBWireRdy == 1'b1)
374
      begin
375
        NextState_prcTxB <= `LS_START_SND_IDLE3;
376
        next_USBWireWEn <= 1'b1;
377
        next_USBWireData <= JBit;
378
        next_USBWireCtrl <= `TRI_STATE;
379
      end
380
    `LS_START_W_RDY2:
381
      if (USBWireRdy == 1'b1)
382
      begin
383
        NextState_prcTxB <= `LS_START_SND_J1;
384
        next_USBWireWEn <= 1'b1;
385
        next_USBWireData <= JBit;
386
        next_USBWireCtrl <= `TRI_STATE;
387
      end
388
    `LS_START_W_RDY3:
389
      if (USBWireRdy == 1'b1)
390
      begin
391
        NextState_prcTxB <= `LS_START_FIN;
392
        //Drive the first JBit
393
        next_USBWireWEn <= 1'b1;
394
        next_USBWireData <= JBit;
395
        next_USBWireCtrl <= `DRIVE;
396
      end
397
  endcase
398
end
399
 
400
//----------------------------------
401
// Current State Logic (sequential)
402
//----------------------------------
403
always @ (posedge clk)
404
begin : prcTxB_CurrentState
405
  if (rst)
406
    CurrState_prcTxB <= `START_PTBY;
407
  else
408
    CurrState_prcTxB <= NextState_prcTxB;
409
end
410
 
411
//----------------------------------
412
// Registered outputs logic
413
//----------------------------------
414
always @ (posedge clk)
415
begin : prcTxB_RegOutput
416
  if (rst)
417
  begin
418
    i <= 4'h0;
419
    TxByte <= 8'h00;
420
    TxByteCtrl <= 8'h00;
421
    TXLineState <= 2'b0;
422
    TXOneCount <= 4'h0;
423
    TxByteFullSpeedRate <= 1'b0;
424
    processTxByteRdy <= 1'b0;
425
    USBWireData <= 2'b00;
426
    USBWireCtrl <= `TRI_STATE;
427
    USBWireReq <= 1'b0;
428
    USBWireWEn <= 1'b0;
429
    USBWireFullSpeedRate <= 1'b0;
430
  end
431
  else
432
  begin
433
    i <= next_i;
434
    TxByte <= next_TxByte;
435
    TxByteCtrl <= next_TxByteCtrl;
436
    TXLineState <= next_TXLineState;
437
    TXOneCount <= next_TXOneCount;
438
    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
439
    processTxByteRdy <= next_processTxByteRdy;
440
    USBWireData <= next_USBWireData;
441
    USBWireCtrl <= next_USBWireCtrl;
442
    USBWireReq <= next_USBWireReq;
443
    USBWireWEn <= next_USBWireWEn;
444
    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
445
  end
446
end
447
 
448
endmodule

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