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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [slaveGetPacket.v] - Blame information for rev 408

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1 408 julius
 
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// File        : ../RTL/slaveController/slaveGetpacket.v
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// Generated   : 11/10/06 05:37:25
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// From        : ../RTL/slaveController/slaveGetpacket.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// slaveGetPacket
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbhostslave_serialinterfaceengine_h.v"
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`include "usbhostslave_constants_h.v"
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module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
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input   [7:0] RXDataIn;
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input   RXDataValid;
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input   RXFifoFull;
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input   [7:0] RXStreamStatusIn;
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input   SIERxTimeOut;           // Single cycle pulse
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input   clk;
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input   endPointReady;
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input   getPacketEn;
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input   rst;
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output  ACKRxed;
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output  CRCError;
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output  [7:0] RXFifoData;
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output  RXFifoWEn;
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output  RXOverflow;
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output  RXPacketRdy;
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output  RXTimeOut;
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output  [3:0] RxPID;
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output  SIERxTimeOutEn;
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output  bitStuffError;
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output  dataSequence;
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reg     ACKRxed, next_ACKRxed;
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reg     CRCError, next_CRCError;
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wire    [7:0] RXDataIn;
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wire    RXDataValid;
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reg     [7:0] RXFifoData, next_RXFifoData;
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wire    RXFifoFull;
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reg     RXFifoWEn, next_RXFifoWEn;
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reg     RXOverflow, next_RXOverflow;
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reg     RXPacketRdy, next_RXPacketRdy;
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wire    [7:0] RXStreamStatusIn;
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reg     RXTimeOut, next_RXTimeOut;
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reg     [3:0] RxPID, next_RxPID;
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wire    SIERxTimeOut;
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reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
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reg     bitStuffError, next_bitStuffError;
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wire    clk;
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reg     dataSequence, next_dataSequence;
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wire    endPointReady;
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wire    getPacketEn;
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wire    rst;
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// diagram signals declarations
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reg  [7:0]RXByteOld, next_RXByteOld;
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reg  [7:0]RXByteOldest, next_RXByteOldest;
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reg  [7:0]RXByte, next_RXByte;
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reg  [7:0]RXStreamStatus, next_RXStreamStatus;
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// BINARY ENCODED state machine: slvGetPkt
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// State codes definitions:
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`define PROC_PKT_CHK_PID 5'b00000
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`define PROC_PKT_HS 5'b00001
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`define PROC_PKT_DATA_W_D1 5'b00010
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`define PROC_PKT_DATA_CHK_D1 5'b00011
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`define PROC_PKT_DATA_W_D2 5'b00100
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`define PROC_PKT_DATA_FIN 5'b00101
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`define PROC_PKT_DATA_CHK_D2 5'b00110
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`define PROC_PKT_DATA_W_D3 5'b00111
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`define PROC_PKT_DATA_CHK_D3 5'b01000
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`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
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`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
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`define PROC_PKT_DATA_LOOP_W_D 5'b01011
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`define START_GP 5'b01100
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`define WAIT_PKT 5'b01101
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`define CHK_PKT_START 5'b01110
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`define WAIT_EN 5'b01111
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`define PKT_RDY 5'b10000
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`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
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`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
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reg [4:0] CurrState_slvGetPkt;
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reg [4:0] NextState_slvGetPkt;
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//--------------------------------------------------------------------
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// Machine: slvGetPkt
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
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begin : slvGetPkt_NextState
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  NextState_slvGetPkt <= CurrState_slvGetPkt;
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  // Set default values for outputs and signals
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  next_CRCError <= CRCError;
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  next_bitStuffError <= bitStuffError;
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  next_RXOverflow <= RXOverflow;
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  next_RXTimeOut <= RXTimeOut;
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  next_ACKRxed <= ACKRxed;
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  next_dataSequence <= dataSequence;
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  next_SIERxTimeOutEn <= SIERxTimeOutEn;
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  next_RXByte <= RXByte;
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  next_RXStreamStatus <= RXStreamStatus;
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  next_RxPID <= RxPID;
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  next_RXPacketRdy <= RXPacketRdy;
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  next_RXByteOldest <= RXByteOldest;
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  next_RXByteOld <= RXByteOld;
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  next_RXFifoWEn <= RXFifoWEn;
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  next_RXFifoData <= RXFifoData;
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  case (CurrState_slvGetPkt)
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    `START_GP:
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      NextState_slvGetPkt <= `WAIT_EN;
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    `WAIT_PKT:
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    begin
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      next_CRCError <= 1'b0;
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      next_bitStuffError <= 1'b0;
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      next_RXOverflow <= 1'b0;
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      next_RXTimeOut <= 1'b0;
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      next_ACKRxed <= 1'b0;
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      next_dataSequence <= 1'b0;
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      next_SIERxTimeOutEn <= 1'b1;
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      if (RXDataValid == 1'b1)
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      begin
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        NextState_slvGetPkt <= `CHK_PKT_START;
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        next_RXByte <= RXDataIn;
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        next_RXStreamStatus <= RXStreamStatusIn;
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      end
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      else if (SIERxTimeOut == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PKT_RDY;
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        next_RXTimeOut <= 1'b1;
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      end
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    end
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    `CHK_PKT_START:
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      if (RXStreamStatus == `RX_PACKET_START)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
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        next_RxPID <= RXByte[3:0];
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      end
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      else
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      begin
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        NextState_slvGetPkt <= `PKT_RDY;
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        next_RXTimeOut <= 1'b1;
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      end
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    `WAIT_EN:
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    begin
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      next_RXPacketRdy <= 1'b0;
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      next_SIERxTimeOutEn <= 1'b0;
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      if (getPacketEn == 1'b1)
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        NextState_slvGetPkt <= `WAIT_PKT;
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    end
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    `PKT_RDY:
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    begin
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      next_RXPacketRdy <= 1'b1;
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      NextState_slvGetPkt <= `WAIT_EN;
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    end
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    `PROC_PKT_CHK_PID:
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      if (RXByte[1:0] == `HANDSHAKE)
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        NextState_slvGetPkt <= `PROC_PKT_HS;
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      else if (RXByte[1:0] == `DATA)
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        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
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      else
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        NextState_slvGetPkt <= `PKT_RDY;
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    `PROC_PKT_HS:
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      if (RXDataValid == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PKT_RDY;
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        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
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        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
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      end
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    `PROC_PKT_DATA_W_D1:
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      if (RXDataValid == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
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        next_RXByte <= RXDataIn;
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        next_RXStreamStatus <= RXStreamStatusIn;
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      end
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    `PROC_PKT_DATA_CHK_D1:
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      if (RXStreamStatus == `RX_PACKET_STREAM)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
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        next_RXByteOldest <= RXByte;
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      end
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      else
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        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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    `PROC_PKT_DATA_W_D2:
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      if (RXDataValid == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
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        next_RXByte <= RXDataIn;
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        next_RXStreamStatus <= RXStreamStatusIn;
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      end
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    `PROC_PKT_DATA_FIN:
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    begin
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      next_CRCError <= RXByte[`CRC_ERROR_BIT];
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      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
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      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
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      NextState_slvGetPkt <= `PKT_RDY;
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    end
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    `PROC_PKT_DATA_CHK_D2:
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      if (RXStreamStatus == `RX_PACKET_STREAM)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
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        next_RXByteOld <= RXByte;
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      end
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      else
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        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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    `PROC_PKT_DATA_W_D3:
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      if (RXDataValid == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
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        next_RXByte <= RXDataIn;
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        next_RXStreamStatus <= RXStreamStatusIn;
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      end
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    `PROC_PKT_DATA_CHK_D3:
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      if (RXStreamStatus == `RX_PACKET_STREAM)
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        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
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      else
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        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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    `PROC_PKT_DATA_LOOP_CHK_FIFO:
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      if (endPointReady == 1'b0)
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        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
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      else if (RXFifoFull == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
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        next_RXOverflow <= 1'b1;
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      end
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      else
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
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        next_RXFifoWEn <= 1'b1;
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        next_RXFifoData <= RXByteOldest;
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        next_RXByteOldest <= RXByteOld;
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        next_RXByteOld <= RXByte;
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      end
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    `PROC_PKT_DATA_LOOP_FIFO_FULL:
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      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
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    `PROC_PKT_DATA_LOOP_W_D:
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    begin
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      next_RXFifoWEn <= 1'b0;
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      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
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        next_RXByte <= RXDataIn;
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      end
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      else if (RXDataValid == 1'b1)
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      begin
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        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
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        next_RXByte <= RXDataIn;
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      end
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    end
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    `PROC_PKT_DATA_LOOP_DELAY:
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      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
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    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
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      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : slvGetPkt_CurrentState
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  if (rst)
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    CurrState_slvGetPkt <= `START_GP;
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  else
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    CurrState_slvGetPkt <= NextState_slvGetPkt;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : slvGetPkt_RegOutput
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  if (rst)
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  begin
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    RXByteOld <= 8'h00;
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    RXByteOldest <= 8'h00;
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    RXByte <= 8'h00;
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    RXStreamStatus <= 8'h00;
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    RXPacketRdy <= 1'b0;
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    RXFifoWEn <= 1'b0;
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    RXFifoData <= 8'h00;
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    CRCError <= 1'b0;
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    bitStuffError <= 1'b0;
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    RXOverflow <= 1'b0;
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    RXTimeOut <= 1'b0;
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    ACKRxed <= 1'b0;
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    dataSequence <= 1'b0;
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    SIERxTimeOutEn <= 1'b0;
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    RxPID <= 4'h0;
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  end
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  else
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  begin
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    RXByteOld <= next_RXByteOld;
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    RXByteOldest <= next_RXByteOldest;
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    RXByte <= next_RXByte;
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    RXStreamStatus <= next_RXStreamStatus;
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    RXPacketRdy <= next_RXPacketRdy;
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    RXFifoWEn <= next_RXFifoWEn;
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    RXFifoData <= next_RXFifoData;
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    CRCError <= next_CRCError;
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    bitStuffError <= next_bitStuffError;
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    RXOverflow <= next_RXOverflow;
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    RXTimeOut <= next_RXTimeOut;
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    ACKRxed <= next_ACKRxed;
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    dataSequence <= next_dataSequence;
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    SIERxTimeOutEn <= next_SIERxTimeOutEn;
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    RxPID <= next_RxPID;
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  end
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end
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endmodule

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