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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [usbslave.v] - Blame information for rev 408

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1 408 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// usbSlave.v                                                   ////
4
////                                                              ////
5
//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
7
////                                                              ////
8
//// Module Description:                                          ////
9
////   Top level module
10
////                                                              ////
11
//// To Do:                                                       ////
12
//// 
13
////                                                              ////
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//// Author(s):                                                   ////
15
//// - Steve Fielding, sfielding@base2designs.com                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
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////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
 
46
module usbslave(
47
  clk_i,
48
  rst_i,
49
  address_i,
50
  data_i,
51
  data_o,
52
  we_i,
53
  strobe_i,
54
  ack_o,
55
  usbClk,
56
  slaveVBusDetIntOut,
57
  slaveNAKSentIntOut,
58
  slaveSOFRxedIntOut,
59
  slaveResetEventIntOut,
60
  slaveResumeIntOut,
61
  slaveTransDoneIntOut,
62
  USBWireDataIn,
63
  USBWireDataInTick,
64
  USBWireDataOut,
65
  USBWireDataOutTick,
66
  USBWireCtrlOut,
67
  USBFullSpeed,
68
  USBDPlusPullup,
69
  USBDMinusPullup,
70
  vBusDetect
71
   );
72
  parameter EP0_FIFO_DEPTH = 64;
73
  parameter EP0_FIFO_ADDR_WIDTH = 6;
74
  parameter EP1_FIFO_DEPTH = 64;
75
  parameter EP1_FIFO_ADDR_WIDTH = 6;
76
  parameter EP2_FIFO_DEPTH = 64;
77
  parameter EP2_FIFO_ADDR_WIDTH = 6;
78
  parameter EP3_FIFO_DEPTH = 64;
79
  parameter EP3_FIFO_ADDR_WIDTH = 6;
80
 
81
input clk_i;               //Wishbone bus clock. Maximum 5*usbClk=240MHz
82
input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
83
input [7:0] address_i;     //Wishbone bus address in
84
input [7:0] data_i;        //Wishbone bus data in
85
output [7:0] data_o;       //Wishbone bus data out
86
input we_i;                //Wishbone bus write enable in
87
input strobe_i;            //Wishbone bus strobe in
88
output ack_o;              //Wishbone bus acknowledge out
89
input usbClk;              //usb clock. 48Mhz +/-0.25%
90
output slaveSOFRxedIntOut;
91
output slaveResetEventIntOut;
92
output slaveResumeIntOut;
93
output slaveTransDoneIntOut;
94
output slaveNAKSentIntOut;
95
output slaveVBusDetIntOut;
96
input [1:0] USBWireDataIn;
97
output [1:0] USBWireDataOut;
98
output USBWireDataOutTick;
99
output USBWireDataInTick;
100
output USBWireCtrlOut;
101
output USBFullSpeed;
102
output USBDPlusPullup;
103
output USBDMinusPullup;
104
input vBusDetect;
105
 
106
wire clk_i;
107
wire rst_i;
108
wire [7:0] address_i;
109
wire [7:0] data_i;
110
wire [7:0] data_o;
111
wire we_i;
112
wire strobe_i;
113
wire ack_o;
114
wire usbClk;
115
wire slaveSOFRxedIntOut;
116
wire slaveResetEventIntOut;
117
wire slaveResumeIntOut;
118
wire slaveTransDoneIntOut;
119
wire slaveNAKSentIntOut;
120
wire slaveVBusDetIntOut;
121
wire [1:0] USBWireDataIn;
122
wire [1:0] USBWireDataOut;
123
wire USBWireDataOutTick;
124
wire USBWireDataInTick;
125
wire USBWireCtrlOut;
126
wire USBFullSpeed;
127
wire USBDPlusPullup;
128
wire USBDMinusPullup;
129
wire vBusDetect;
130
 
131
//internal wiring
132
wire slaveControlSel;
133
wire hostSlaveMuxSel;
134
wire [7:0] dataFromSlaveControl;
135
wire [7:0] dataFromHostSlaveMux;
136
wire [7:0] RxCtrlOut;
137
wire [7:0] RxDataFromSIE;
138
wire RxDataOutWEn;
139
wire fullSpeedBitRateFromSlave;
140
wire fullSpeedPolarityFromSlave;
141
wire SIEPortWEnFromSlave;
142
wire SIEPortTxRdy;
143
wire [7:0] SIEPortDataInFromSlave;
144
wire [7:0] SIEPortCtrlInFromSlave;
145
wire [1:0] connectState;
146
wire resumeDetected;
147
wire [7:0] SIEPortDataInToSIE;
148
wire SIEPortWEnToSIE;
149
wire [7:0] SIEPortCtrlInToSIE;
150
wire fullSpeedPolarityToSIE;
151
wire fullSpeedBitRateToSIE;
152
wire connectSlaveToHost;
153
wire noActivityTimeOut;
154
wire TxFifoEP0REn;
155
wire TxFifoEP1REn;
156
wire TxFifoEP2REn;
157
wire TxFifoEP3REn;
158
wire [7:0] TxFifoEP0Data;
159
wire [7:0] TxFifoEP1Data;
160
wire [7:0] TxFifoEP2Data;
161
wire [7:0] TxFifoEP3Data;
162
wire TxFifoEP0Empty;
163
wire TxFifoEP1Empty;
164
wire TxFifoEP2Empty;
165
wire TxFifoEP3Empty;
166
wire RxFifoEP0WEn;
167
wire RxFifoEP1WEn;
168
wire RxFifoEP2WEn;
169
wire RxFifoEP3WEn;
170
wire RxFifoEP0Full;
171
wire RxFifoEP1Full;
172
wire RxFifoEP2Full;
173
wire RxFifoEP3Full;
174
wire [7:0] slaveRxFifoData;
175
wire [7:0] dataFromEP0RxFifo;
176
wire [7:0] dataFromEP1RxFifo;
177
wire [7:0] dataFromEP2RxFifo;
178
wire [7:0] dataFromEP3RxFifo;
179
wire [7:0] dataFromEP0TxFifo;
180
wire [7:0] dataFromEP1TxFifo;
181
wire [7:0] dataFromEP2TxFifo;
182
wire [7:0] dataFromEP3TxFifo;
183
wire slaveEP0RxFifoSel;
184
wire slaveEP1RxFifoSel;
185
wire slaveEP2RxFifoSel;
186
wire slaveEP3RxFifoSel;
187
wire slaveEP0TxFifoSel;
188
wire slaveEP1TxFifoSel;
189
wire slaveEP2TxFifoSel;
190
wire slaveEP3TxFifoSel;
191
wire rstSyncToBusClk;
192
wire rstSyncToUsbClk;
193
wire noActivityTimeOutEnableToSIE;
194
wire noActivityTimeOutEnableFromHost;
195
wire noActivityTimeOutEnableFromSlave;
196
 
197
assign USBFullSpeed = fullSpeedBitRateToSIE;
198
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
199
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
200
 
201
usbSlaveControl u_usbSlaveControl(
202
  .busClk(clk_i),
203
  .rstSyncToBusClk(rstSyncToBusClk),
204
  .usbClk(usbClk),
205
  .rstSyncToUsbClk(rstSyncToUsbClk),
206
  .RxByteStatus(RxCtrlOut),
207
  .RxData(RxDataFromSIE),
208
  .RxDataValid(RxDataOutWEn),
209
  .SIERxTimeOut(noActivityTimeOut),
210
  .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
211
  .RxFifoData(slaveRxFifoData),
212
  .connectSlaveToHost(connectSlaveToHost),
213
  .fullSpeedRate(fullSpeedBitRateFromSlave),
214
  .fullSpeedPol(fullSpeedPolarityFromSlave),
215
  .SCTxPortEn(SIEPortWEnFromSlave),
216
  .SCTxPortRdy(SIEPortTxRdy),
217
  .SCTxPortData(SIEPortDataInFromSlave),
218
  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
219
  .vBusDetect(vBusDetect),
220
  .connectStateIn(connectState),
221
  .resumeDetectedIn(resumeDetected),
222
  .busAddress(address_i[4:0]),
223
  .busDataIn(data_i),
224
  .busDataOut(dataFromSlaveControl),
225
  .busWriteEn(we_i),
226
  .busStrobe_i(strobe_i),
227
  .SOFRxedIntOut(slaveSOFRxedIntOut),
228
  .resetEventIntOut(slaveResetEventIntOut),
229
  .resumeIntOut(slaveResumeIntOut),
230
  .transDoneIntOut(slaveTransDoneIntOut),
231
  .NAKSentIntOut(slaveNAKSentIntOut),
232
  .vBusDetIntOut(slaveVBusDetIntOut),
233
  .slaveControlSelect(slaveControlSel),
234
  .TxFifoEP0REn(TxFifoEP0REn),
235
  .TxFifoEP1REn(TxFifoEP1REn),
236
  .TxFifoEP2REn(TxFifoEP2REn),
237
  .TxFifoEP3REn(TxFifoEP3REn),
238
  .TxFifoEP0Data(TxFifoEP0Data),
239
  .TxFifoEP1Data(TxFifoEP1Data),
240
  .TxFifoEP2Data(TxFifoEP2Data),
241
  .TxFifoEP3Data(TxFifoEP3Data),
242
  .TxFifoEP0Empty(TxFifoEP0Empty),
243
  .TxFifoEP1Empty(TxFifoEP1Empty),
244
  .TxFifoEP2Empty(TxFifoEP2Empty),
245
  .TxFifoEP3Empty(TxFifoEP3Empty),
246
  .RxFifoEP0WEn(RxFifoEP0WEn),
247
  .RxFifoEP1WEn(RxFifoEP1WEn),
248
  .RxFifoEP2WEn(RxFifoEP2WEn),
249
  .RxFifoEP3WEn(RxFifoEP3WEn),
250
  .RxFifoEP0Full(RxFifoEP0Full),
251
  .RxFifoEP1Full(RxFifoEP1Full),
252
  .RxFifoEP2Full(RxFifoEP2Full),
253
  .RxFifoEP3Full(RxFifoEP3Full)
254
  );
255
 
256
 
257
wishBoneBI u_wishBoneBI (
258
  .address(address_i),
259
  .dataIn(data_i),
260
  .dataOut(data_o),
261
  .writeEn(we_i),
262
  .strobe_i(strobe_i),
263
  .ack_o(ack_o),
264
  .clk(clk_i),
265
  .rst(rstSyncToBusClk),
266
  .hostControlSel(),
267
  .hostRxFifoSel(),
268
  .hostTxFifoSel(),
269
  .slaveControlSel(slaveControlSel),
270
  .slaveEP0RxFifoSel(slaveEP0RxFifoSel),
271
  .slaveEP1RxFifoSel(slaveEP1RxFifoSel),
272
  .slaveEP2RxFifoSel(slaveEP2RxFifoSel),
273
  .slaveEP3RxFifoSel(slaveEP3RxFifoSel),
274
  .slaveEP0TxFifoSel(slaveEP0TxFifoSel),
275
  .slaveEP1TxFifoSel(slaveEP1TxFifoSel),
276
  .slaveEP2TxFifoSel(slaveEP2TxFifoSel),
277
  .slaveEP3TxFifoSel(slaveEP3TxFifoSel),
278
  .hostSlaveMuxSel(hostSlaveMuxSel),
279
  .dataFromHostControl(8'h00),
280
  .dataFromHostRxFifo(8'h00),
281
  .dataFromHostTxFifo(8'h00),
282
  .dataFromSlaveControl(dataFromSlaveControl),
283
  .dataFromEP0RxFifo(dataFromEP0RxFifo),
284
  .dataFromEP1RxFifo(dataFromEP1RxFifo),
285
  .dataFromEP2RxFifo(dataFromEP2RxFifo),
286
  .dataFromEP3RxFifo(dataFromEP3RxFifo),
287
  .dataFromEP0TxFifo(dataFromEP0TxFifo),
288
  .dataFromEP1TxFifo(dataFromEP1TxFifo),
289
  .dataFromEP2TxFifo(dataFromEP2TxFifo),
290
  .dataFromEP3TxFifo(dataFromEP3TxFifo),
291
  .dataFromHostSlaveMux(dataFromHostSlaveMux)
292
   );
293
 
294
 
295
 
296
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
297
assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
298
assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
299
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
300
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
301
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
302
 
303
hostSlaveMuxBI u_hostSlaveMuxBI (
304
  .dataIn(data_i),
305
  .dataOut(dataFromHostSlaveMux),
306
  .address(address_i[0]),
307
  .writeEn(we_i),
308
  .strobe_i(strobe_i),
309
  .usbClk(usbClk),
310
  .busClk(clk_i),
311
  .hostSlaveMuxSel(hostSlaveMuxSel),
312
  .hostMode(),
313
  .rstFromWire(rst_i),
314
  .rstSyncToBusClkOut(rstSyncToBusClk),
315
  .rstSyncToUsbClkOut(rstSyncToUsbClk)
316
);
317
 
318
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
319
  .clk(usbClk),
320
  .rst(rstSyncToUsbClk),
321
  .USBWireDataIn(USBWireDataIn),
322
  .USBWireDataOut(USBWireDataOut),
323
  .USBWireDataInTick(USBWireDataInTick),
324
  .USBWireDataOutTick(USBWireDataOutTick),
325
  .USBWireCtrlOut(USBWireCtrlOut),
326
  .connectState(connectState),
327
  .resumeDetected(resumeDetected),
328
  .RxCtrlOut(RxCtrlOut),
329
  .RxDataOutWEn(RxDataOutWEn),
330
  .RxDataOut(RxDataFromSIE),
331
  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
332
  .SIEPortDataIn(SIEPortDataInToSIE),
333
  .SIEPortTxRdy(SIEPortTxRdy),
334
  .SIEPortWEn(SIEPortWEnToSIE),
335
  .fullSpeedPolarity(fullSpeedPolarityToSIE),
336
  .fullSpeedBitRate(fullSpeedBitRateToSIE),
337
  .noActivityTimeOut(noActivityTimeOut),
338
  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
339
);
340
 
341
 
342
 
343
//---Slave fifos
344
 
345
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
346
  .usbClk(usbClk),
347
  .busClk(clk_i),
348
  .rstSyncToBusClk(rstSyncToBusClk),
349
  .rstSyncToUsbClk(rstSyncToUsbClk),
350
  .fifoREn(TxFifoEP0REn),
351
  .fifoEmpty(TxFifoEP0Empty),
352
  .busAddress(address_i[2:0]),
353
  .busWriteEn(we_i),
354
  .busStrobe_i(strobe_i),
355
  .busFifoSelect(slaveEP0TxFifoSel),
356
  .busDataIn(data_i),
357
  .busDataOut(dataFromEP0TxFifo),
358
  .fifoDataOut(TxFifoEP0Data) );
359
 
360
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
361
  .usbClk(usbClk),
362
  .busClk(clk_i),
363
  .rstSyncToBusClk(rstSyncToBusClk),
364
  .rstSyncToUsbClk(rstSyncToUsbClk),
365
  .fifoREn(TxFifoEP1REn),
366
  .fifoEmpty(TxFifoEP1Empty),
367
  .busAddress(address_i[2:0]),
368
  .busWriteEn(we_i),
369
  .busStrobe_i(strobe_i),
370
  .busFifoSelect(slaveEP1TxFifoSel),
371
  .busDataIn(data_i),
372
  .busDataOut(dataFromEP1TxFifo),
373
  .fifoDataOut(TxFifoEP1Data) );
374
 
375
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
376
  .usbClk(usbClk),
377
  .busClk(clk_i),
378
  .rstSyncToBusClk(rstSyncToBusClk),
379
  .rstSyncToUsbClk(rstSyncToUsbClk),
380
  .fifoREn(TxFifoEP2REn),
381
  .fifoEmpty(TxFifoEP2Empty),
382
  .busAddress(address_i[2:0]),
383
  .busWriteEn(we_i),
384
  .busStrobe_i(strobe_i),
385
  .busFifoSelect(slaveEP2TxFifoSel),
386
  .busDataIn(data_i),
387
  .busDataOut(dataFromEP2TxFifo),
388
  .fifoDataOut(TxFifoEP2Data) );
389
 
390
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
391
  .usbClk(usbClk),
392
  .busClk(clk_i),
393
  .rstSyncToBusClk(rstSyncToBusClk),
394
  .rstSyncToUsbClk(rstSyncToUsbClk),
395
  .fifoREn(TxFifoEP3REn),
396
  .fifoEmpty(TxFifoEP3Empty),
397
  .busAddress(address_i[2:0]),
398
  .busWriteEn(we_i),
399
  .busStrobe_i(strobe_i),
400
  .busFifoSelect(slaveEP3TxFifoSel),
401
  .busDataIn(data_i),
402
  .busDataOut(dataFromEP3TxFifo),
403
  .fifoDataOut(TxFifoEP3Data) );
404
 
405
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
406
  .usbClk(usbClk),
407
  .busClk(clk_i),
408
  .rstSyncToBusClk(rstSyncToBusClk),
409
  .rstSyncToUsbClk(rstSyncToUsbClk),
410
  .fifoWEn(RxFifoEP0WEn),
411
  .fifoFull(RxFifoEP0Full),
412
  .busAddress(address_i[2:0]),
413
  .busWriteEn(we_i),
414
  .busStrobe_i(strobe_i),
415
  .busFifoSelect(slaveEP0RxFifoSel),
416
  .busDataIn(data_i),
417
  .busDataOut(dataFromEP0RxFifo),
418
  .fifoDataIn(slaveRxFifoData)  );
419
 
420
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
421
  .usbClk(usbClk),
422
  .busClk(clk_i),
423
  .rstSyncToBusClk(rstSyncToBusClk),
424
  .rstSyncToUsbClk(rstSyncToUsbClk),
425
  .fifoWEn(RxFifoEP1WEn),
426
  .fifoFull(RxFifoEP1Full),
427
  .busAddress(address_i[2:0]),
428
  .busWriteEn(we_i),
429
  .busStrobe_i(strobe_i),
430
  .busFifoSelect(slaveEP1RxFifoSel),
431
  .busDataIn(data_i),
432
  .busDataOut(dataFromEP1RxFifo),
433
  .fifoDataIn(slaveRxFifoData)  );
434
 
435
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
436
  .usbClk(usbClk),
437
  .busClk(clk_i),
438
  .rstSyncToBusClk(rstSyncToBusClk),
439
  .rstSyncToUsbClk(rstSyncToUsbClk),
440
  .fifoWEn(RxFifoEP2WEn),
441
  .fifoFull(RxFifoEP2Full),
442
  .busAddress(address_i[2:0]),
443
  .busWriteEn(we_i),
444
  .busStrobe_i(strobe_i),
445
  .busFifoSelect(slaveEP2RxFifoSel),
446
  .busDataIn(data_i),
447
  .busDataOut(dataFromEP2RxFifo),
448
  .fifoDataIn(slaveRxFifoData)  );
449
 
450
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
451
  .usbClk(usbClk),
452
  .busClk(clk_i),
453
  .rstSyncToBusClk(rstSyncToBusClk),
454
  .rstSyncToUsbClk(rstSyncToUsbClk),
455
  .fifoWEn(RxFifoEP3WEn),
456
  .fifoFull(RxFifoEP3Full),
457
  .busAddress(address_i[2:0]),
458
  .busWriteEn(we_i),
459
  .busStrobe_i(strobe_i),
460
  .busFifoSelect(slaveEP3RxFifoSel),
461
  .busDataIn(data_i),
462
  .busDataOut(dataFromEP3RxFifo),
463
  .fifoDataIn(slaveRxFifoData)  );
464
 
465
 
466
 
467
endmodule
468
 
469
 
470
 
471
 
472
 
473
 
474
 

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