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1 6 julius
######################################################################
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####                                                              ####
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####  ORPSoCv2 Testbenches Makefile                               ####
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####                                                              ####
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####  Description                                                 ####
6
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
7
####  configuring and running different tests on the current      ####
8
####  ORPSoC(v2) design.                                          ####
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####                                                              ####
10
####  To do:                                                      ####
11
####    * Arrange verilator make rules so that the whole thing    ####
12
####      isn't recompiled when a single SystemC module is        ####
13
####      updated.                                                ####
14
####    * Test if each software test file gets made properly      ####
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####      before it's run in whatever model we're using           ####
16
####    * Expand software test-suite (uClibc, ecos tests, LTP?)   ####
17
####                                                              ####
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####  Author(s):                                                  ####
19
####      - jb, jb@orsoc.se                                       ####
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####                                                              ####
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####                                                              ####
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######################################################################
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####                                                              ####
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#### Copyright (C) 2009 Authors and OPENCORES.ORG                 ####
25
####                                                              ####
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#### This source file may be used and distributed without         ####
27
#### restriction provided that this copyright statement is not    ####
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#### removed from the file and that any derivative work contains  ####
29
#### the original copyright notice and the associated disclaimer. ####
30
####                                                              ####
31
#### This source file is free software; you can redistribute it   ####
32
#### and/or modify it under the terms of the GNU Lesser General   ####
33
#### Public License as published by the Free Software Foundation; ####
34
#### either version 2.1 of the License, or (at your option) any   ####
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#### later version.                                               ####
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####                                                              ####
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#### This source is distributed in the hope that it will be       ####
38
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
39
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
40
#### PURPOSE.  See the GNU Lesser General Public License for more ####
41
#### details.                                                     ####
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####                                                              ####
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#### You should have received a copy of the GNU Lesser General    ####
44
#### Public License along with this source; if not, download it   ####
45
#### from http://www.opencores.org/lgpl.shtml                     ####
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####                                                              ####
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######################################################################
48
 
49
# Usage:
50
#
51
#       make rtl-tests
52
#
53
#       Run the software tests in the RTL model of the ORPSoC being
54
#       simulated with an event-driven simulator like Icarus. Also
55
#       possible to use Cadence's Verilog simulators with the
56
#       "rtl-nc-tests" target.
57
#
58
#       make vlt-tests
59
#
60
#       Run all the software tests in the RTL model which has been
61
#       converted into a cycle-accurate SystemC model with Verilator.
62
#
63
#       make sim-tests
64
#
65
#       Run all the software tests in the architectural simulator
66
#
67 40 julius
#
68
# Debugging modes:
69
#
70
#       make rtl-debug
71
#
72
#       Enable a GDB stub integrated into the simulation via VPI. This will
73
#       start a simulation, then the GDB server, and allow the user to connect
74
#       using the OpenRISC GDB port. It should provide the same functionality
75
#       as GDB to a physical target, although a little slower.
76
#       It is provided here as an example of how to compile and run an OpenRISC
77
#       model at RTL level with support for debugging from GDB.
78
#       UART output from printf() is enabled by default. The model loads with
79
#       the dhrystone test running as default, but can be changed by defining
80
#       VPI_TEST_SW at the command line. Logging of the processor's execution
81
#       is also disabled by default to speed up simulation.
82
#
83 6 julius
 
84
# Simulation results:
85
#
86
# The results and output of the event-driven simulations are in the
87
# results path, in parallel to the simulation run and bin paths.
88
 
89
# Specific tests:
90
#
91
# To run an individual test, specify it in the variable TESTS when
92
# calling make, eg:
93
#
94
#        make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
95
 
96
# UART printf:
97
#
98
# It is possible to enable printf to the console via the UART when
99
# running the event-driven simulators. To do this define UART_PRINTF=1
100
# when calling make. The SystemC cycle-acccurate model uses this by
101
# default.
102
# Also note when switching between runs with and without UART printf
103
# enabled, run a clean-sw so the library files are recompiled when
104
# the tests are run - this is not done automatically.
105
 
106
# VCDs:
107
#
108
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
109
# to inspect the internals of the system graphically) files can be
110
# generated by defining a variable VCD, eg.
111
#
112
#       make rtl-tests VCD=1
113
#
114
# and a dump file will be created in the simulation results directory,
115
# and named according to the test run which generated it. This is
116
# possible for both event-driven and cycle-accurate simulations.
117
# However the cycle-accurate
118
 
119
# NO_SIM_LOGGING:
120
#
121
# It is possible to speed up the event-driven simulation slightly by
122
# disabling log output of the processor's state to files by defining
123
# NO_SIM_LOGGING, eg:
124
#
125
#       make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
126
#
127
 
128
# Cleaning:
129
# A simple "make clean" cleans everything - software and all temporary
130
# simulation files and directories. To clean just the software run:
131
#
132
#       make clean-sw
133
#
134
# and to clean just the temporary simulation files (including VCDs,
135
# results logs - everything under, and including, sim/results/, run
136
#
137
#       make clean-sim
138
#
139
 
140
# Note:
141
#
142
# The way each of the test loops is written is probably a bit overly complex
143
# but this is to save maintaining, and calling, multiple files.
144
#
145
 
146
# Model configuration:
147
#
148
# Currently, the ORPSoCv2, by default, contains an internal SRAM (configurable
149
# size - check the defparam in rtl/verilog/orpsoc_top.v), standard OR1200 (check
150
# the config in rtl/verilog/or1200_defines.v) and UART.
151
# Switches can be passed to enable certain parts of the design if testing with
152
# these is desired.
153
#
154
# SDRAM and controller
155
#
156
# To enable the use of SDRAM, define USE_SDRAM when calling the sim -this
157
# only has an effect in the event-driven simulators as the external SDRAM model
158
# is not availble in SystemC format. eg:
159
#
160
#       make rtl-tests USE_SDRAM=1
161
#
162
# This not only enables SDRAM but also enables the booting from external SPI
163
# interfaced flash memory. This causes significant increase in the time taken
164
# for simulation as the program to test is first loaded out of SPI flash memory
165
# and into SDRAM before it is executed. Although this more closely mimics the
166
# behaviour of the hardware, for simulation purposes it is purely time-consuming
167
# however it may be useful to track down any problems with this boot-loading
168 43 julius
# process. Therefore, becuase it enables SDRAM memory, it also enables the flash
169 6 julius
# memory model and SPI controller inside ORPSoC.
170
#
171
# Ethernet
172
#
173
# Ethernet is disabled by default. This is due to the fact that it is not
174
# supported in the verilator/systemC model. Also, there is currently no software
175
# which tests it in any meaningful way.
176
#
177
 
178
#
179
# Event-driven simulation compilation
180
#
181
# The way the event-driven simulations are compiled is simply using the
182
# configuration script file in this directory, currently called icarus.scr -
183
# however it is first processesed to replace the variables, beginning with $'s,
184
# with the appropriate paths. Instead of naming each file to be compiled, the
185
# paths to be searched for each module are instead defined ( -y paths), and
186
# only the toplevel testbench and library source files are explicitly named.
187
# This simplifies the script, and also requires that the name of each verilog
188
# source file is the same as the module it contains (a good convention
189
# regardless.) In addition to the script/command file, defines are passed to
190
# the compiler via the command line in the EVENT_SIM_FLAGS variable.
191
# Additionally, a source file, test_define.v, is created with  some defines
192
# that cannot be passed to the compiled reliably (there are differences between
193
# the way, for instance, icarus and ncverilog parse strings +define+'d on the
194
# command line). This file is then included at the appropriate places.
195
# It is probably not ideal that the entire design be re-compiled for each test,
196
# but currently the design is small enough so that this doesn't cause a
197
# significant overhead, unlike the cycle-accurate model compile time.
198
#
199
 
200
#
201
# SystemC cycle-accurate model compilation
202
#
203
# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
204 44 julius
# behind this is verilator, which processes the RTL source and generates a c++
205
# description of the system. This c++ description is then compiled, with a
206 6 julius
# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
207 44 julius
# model, and other useful modules - in this case a reset generation, UART
208 6 julius
# decoder, and monitor module are included at the top level. These additional
209 44 julius
# modules and models are written in SystemC. Finally, everything is linked with
210
# the cycle-accurate ORPSoC model to create the simulation executable. This
211
# executable is the cycle-representation of the system.
212
#
213
# VCDs can be generated if the model is made with VCD=1 specified on the
214
# command line. Specify a dump file with the "-vcd" option at runtime, eg:
215
# "./Vorpsoc_top -vcd dump.vcd"
216
# Note that this slows down the simulation.
217
#
218
# Logging of the processor's execution can be done by specifying a log file
219
# on the command line at runtime, eg: "./Vorpsoc_top -log or1200_exec.log"
220
# Note that this slows down the simulation.
221
#
222
# There are performance metrics printed at the conclusion of simulations. To
223
# disable these launch the executable with either the -q or --no-perf-summary
224
# options. eg: "./Vorpsoc_top -q"
225
#
226
# The compilation is all done with the GNU c++ compiler, g++.
227
#
228
# The compilation process is a little more complicated than the event-driven
229 6 julius
# simulator. It proceeds basically by generating the makefiles for compiling
230
# the design with verilator, running these makes which produces a library
231
# containing the cycle-accurate ORPSoC design, compiling the additional
232
# top-level, and testbench, systemC models into a library, and then linking it
233
# all together into the simulation executable.
234 44 julius
#
235 6 julius
# The major advantage of the cycle-accurate model is that it is quicker, in
236
# terms of simulated cycles/second, when compared with event-driven simulators.
237
# It is, of course, less accurate in that it cannot model propegation delays.
238
# However this is usually not an issue for simulating a design which is known
239
# to synthesize and run OK. It is very useful for running complex software,
240
# such as the linux kernel and real-time OS applications, which generally
241 44 julius
# result in long simulation times.
242
#
243 6 julius
# Currently the cycle-accurate model being used doesn't contain much more than
244
# the processor and a UART, however it's exepected in future this will be
245
# expanded on and more complex software test suites will be implemented to put
246
# the system through its paces.
247
#
248 44 julius
#
249 6 julius
 
250 44 julius
# Name of the directory we're currently in
251 6 julius
CUR_DIR=$(shell pwd)
252
 
253
# The root path of the whole project
254
PROJECT_ROOT=$(CUR_DIR)/../..
255
 
256
# Tests is only defined if it wasn't already defined when make was called
257
# This is the default list of every test that is currently possible
258
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
259
 
260
# Paths to other important parts of this test suite
261
SIM_DIR=$(PROJECT_ROOT)/sim
262
SIM_RUN_DIR=$(SIM_DIR)/run
263
SIM_BIN_DIR=$(SIM_DIR)/bin
264
SIM_RESULTS_DIR=$(SIM_DIR)/results
265
SIM_VLT_DIR=$(SIM_DIR)/vlt
266
BENCH_DIR=$(PROJECT_ROOT)/bench
267
BACKEND_DIR=$(PROJECT_ROOT)/backend
268
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
269
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
270
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
271
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
272
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
273
SW_DIR=$(PROJECT_ROOT)/sw
274
 
275
ICARUS=iverilog
276
ICARUS_VVP=vvp
277
ICARUS_COMMAND_FILE=icarus.scr
278
VLT_COMMAND_FILE=verilator.scr
279
SIM_SUCCESS_MESSAGE=deaddead
280
 
281
ARCH_SIM_EXE=or32-elf-sim
282
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
283
 
284
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
285
# command line becuase it's used by many different modules and it's easier
286
# to do it this way than make them all include a file.
287
ifdef USE_SDRAM
288
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
289
endif
290
 
291
# Enable ethernet if defined on the command line
292
ifdef USE_ETHERNET
293 44 julius
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)"
294
# Extra tests we do if ethernet is enabled
295
TESTS += eth-basic
296 6 julius
endif
297
 
298
SIM_FLASH_MEM_FILE="flash.in"
299
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
300
SIM_SRAM_MEM_FILE="sram.vmem"
301
 
302
TESTS_PASSED=0
303
TESTS_PERFORMED=0;
304
 
305
################################################################################
306
# Event-driven simulator build rules (Icarus, NCSim)
307
################################################################################
308
 
309
.PHONY: prepare_rtl
310
prepare_rtl:
311
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
312
        @cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
313
 
314
 
315
ifdef UART_PRINTF
316 44 julius
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
317 6 julius
endif
318
 
319
.PHONY: prepare_sw
320
prepare_sw:
321
        @$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
322
        @$(MAKE) -C $(SW_DIR)/utils all
323
 
324
# A rule with UART_PRINTF hard defined ... used by verilator make sw
325
prepare_sw_uart_printf:
326
        @$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
327
        @$(MAKE) -C $(SW_DIR)/utils all
328
 
329 40 julius
prepare_dirs:
330
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
331 6 julius
 
332
# Rough guide to how these tests work:
333
# First, the couple of custom, required, software tools under sw/utils are
334
# compiled, and then the software library files.
335
# Next the few verilog files that need preperation are taken care of.
336
# The test begins by starting a loop in bash using on the strings defined in
337
# TESTS. Each one corresponds to a certain module of software for the OpenRISC
338
# that is included in this test suite. Under the sw/ path is a set of paths,
339
# and all except the support/ and utils/ paths contain code which is run to
340
# test the OR1k used in this test suite. For each of these software modules,
341
# it is possible that different tests are done using the same module. These
342
# tests can vary by either using different levels of optimisation during
343
# compilation, and/or by having the OR1k's caches enabled or disabled.
344
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
345
# usually just ../results, log files, and optionally VCD files, are created for
346
# inspection later and are named according to the test. Inspect the file
347
# bench/verilog/or1200_monitor.v to find out in detail what each log consists
348
# of.
349
# For each test, a few things occur. First the software that will run inside
350
# the simulated OR1k system is compiled, converted to a format which can be
351
# read
352
# into the flash memory model via $readmemh() and linked to the sim/run
353
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
354
# compilation script for icarus is generated, containing a list of all the
355
# RTL files and include directories. Next, an include file for the verilog
356
# testbench is generated, containing a string of the name of the current
357
# test, path to the results directory (for VCD generation) and any other
358
# things which might vary from test to test. This is not done by +define
359
# lines in the icarus script because of string handling incosistencies
360
# between different simulators and shells.
361
# Once all the files are generated, icarus is called to compile the rtl
362
# design, and then run it. Each of the tested software modules have code which
363
# will trigger the simulation to be stopped by use of the l.nop instruction
364
# with an immediate value of 1. When the simulation finishes, the simulation
365
# executable exits and the log of the simulation is inspected for the expected
366
# output. Currently, the string "deaddead" indicates that the software
367
# completed successfully. This is counted as the ORPSoC "passing" the test. In
368
# fact, whether the system did the right thing or not requires more
369
# inspection, but roughly this is a good indicator that nothing major went
370
# wrong.
371
# Once the current test is finished, the next begins with the compilation of its
372
# software and linking of the resulting hex file to the run path, etc.
373
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
374
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
375
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
376
# Verilator defaults to internal memories
377 44 julius
rtl-tests: prepare_sw prepare_rtl prepare_dirs
378 6 julius
        @echo
379
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
380
        @echo
381
        @for TEST in $(TESTS); do \
382
                echo "################################################################################"; \
383
                echo; \
384
                echo "\t#### Current test: $$TEST ####"; echo; \
385
                echo "\t#### Compiling software ####"; echo; \
386
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
387
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
388
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
389
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
390
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
391
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
392
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
393
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
394
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
395
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
396
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
397
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
398
                if [ ! -z $$VCD ]; \
399
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
400
                fi; \
401
                if [ ! -z $$UART_PRINTF ]; \
402
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
403
                fi; \
404
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
405
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
406 44 julius
                if echo $$TEST | grep -q -i ^eth; then \
407
                        echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
408
                        echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
409
                fi; \
410 43 julius
                if [ -z $$NO_SIM_LOGGING ]; then \
411 6 julius
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
412
                fi; \
413
                echo ; \
414
                echo "\t#### Compiling RTL ####"; \
415
                rm -f $(SIM_RUN_DIR)/a.out; \
416
                $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS); \
417
                echo; \
418
                echo "\t#### Beginning simulation ####"; \
419
                time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
420
                if [ $$? -gt 0 ]; then exit $$?; fi; \
421
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
422
                echo; echo "\t####"; \
423
                if [ $$TEST_RESULT -gt 0 ]; then \
424
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
425
                else    echo "\t#### Test $$TEST FAILED ####";\
426
                fi; \
427
                echo "\t####"; echo; \
428
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
429
        done; \
430
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
431
 
432
 
433
 
434
# Use NCSIM instead of icarus
435 40 julius
rtl-nc-tests: prepare_sw prepare_rtl prepare_dirs
436 6 julius
        @echo
437
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
438
        @echo
439
        @for TEST in $(TESTS); do \
440
                echo "################################################################################"; \
441
                echo; \
442
                echo "\t#### Current test: $$TEST ####"; echo; \
443
                echo "\t#### Compiling software ####"; echo; \
444
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
445
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
446
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
447
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
448
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
449
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
450
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
451
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
452
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
453
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
454
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
455
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
456
                if [ ! -z $$VCD ]; \
457
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
458
                        echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
459
                fi; \
460
                if [ ! -z $$UART_PRINTF ]; \
461
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
462
                fi; \
463
                if [ ! -z $$USE_SDRAM ]; then \
464
                        echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
465
                fi; \
466 44 julius
                if echo $$TEST | grep -q -i ^eth; then \
467
                        echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
468
                        echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
469
                fi; \
470 6 julius
                echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
471
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
472
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
473
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
474
                if [ -z $$NO_SIM_LOGGING ]; then \
475
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
476
                fi; \
477
                echo ; \
478
                echo "\t#### Beginning simulation ####"; \
479
                time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(EVENT_SIM_FLAGS); \
480
                if [ $$? -gt 0 ]; then exit $$?; fi; \
481
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
482
                echo; echo "\t####"; \
483
                if [ $$TEST_RESULT -gt 0 ]; then \
484
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
485
                else    echo "\t#### Test $$TEST FAILED ####";\
486
                fi; \
487
                echo "\t####"; echo; \
488
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
489
        done; \
490
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
491
 
492
################################################################################
493 40 julius
# RTL simulation in Icarus with GDB stub via VPI for debugging
494
################################################################################
495
# This compiles a version of the system which starts up the dhrystone nocache
496
# test, and launches the simulator with a VPI module that provides a GDB stub
497
# allowing the OpenRISC compatible GDB to connect and debug the system.
498
# The launched test can be changed by defining VPI_TEST_SW on the make line
499
VPI_DIR=$(BENCH_VERILOG_DIR)/vpi
500
VPI_C_DIR=$(VPI_DIR)/c
501
VPI_VERILOG_DIR=$(VPI_DIR)/verilog
502
VPI_LIB_NAME=jp_vpi
503
ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)
504
VPI_TEST_SW ?= dhry-nocache-O2
505
 
506
prepare_vpi:
507
## Build the VPI library
508
        $(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)
509
 
510
clean_vpi:
511
        $(MAKE) -C $(VPI_C_DIR) clean
512
 
513
rtl-debug: prepare_sw_uart_printf prepare_rtl prepare_vpi prepare_dirs
514
## Prepare the software for the test
515
        @echo "\t#### Compiling software ####"; echo; \
516
        CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \
517
        $(MAKE) -C $$CURRENT_TEST_SW_DIR $(VPI_TEST_SW) $(TEST_SW_MAKE_OPTS); \
518
        rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
519
        rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
520
        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
521
        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)
522
## Generate the icarus script we'll compile with
523
        @sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
524
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
525
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
526
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
527
                -e \\!^//.*\$$!d -e \\!^\$$!d
528
## Add a couple of extra defines to the icarus compile script
529
        @echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
530
## The define that enables the VPI debug module
531
        @echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
532
        @if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi
533
## Unless NO_UART_PRINTF=1 we use printf via the UART
534
        @if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi
535
        @echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
536
        @echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
537
        @if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
538
        @echo
539
        @echo "\t#### Compiling RTL ####"
540
        @rm -f $(SIM_RUN_DIR)/a.out
541
        @$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
542
        @echo
543
        @echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
544
        @$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
545
 
546
################################################################################
547 6 julius
# Verilator model build rules
548
################################################################################
549
 
550
 
551
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
552
 
553
 
554
# List of System C models - use this list to link the sources into the Verilator
555
# build directory
556
SYSC_MODELS=OrpsocAccess TraceSC
557
 
558
ifdef VCD
559
VLT_FLAGS +=-trace
560
endif
561
 
562
# Only need the trace target if we are tracing
563
ifneq (,$(findstring -trace, $(VLT_FLAGS)))
564
VLT_TRACEOBJ = SpTraceVcdC
565
endif
566
 
567
# This is the list of extra models we'll issue make commands for
568
# Included is the SystemPerl trace model
569
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
570
 
571
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
572
 
573
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
574
# Final linking of the simulation executable. Order of libraries here is important!
575
        @echo; echo "\tGenerating simulation executable"; echo
576
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
577
 
578
$(SIM_VLT_DIR)/OrpsocMain.o:
579
# Now compile the top level systemC "testbench" module
580
        @echo; echo "\tCompiling top level SystemC testbench"; echo
581
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
582
 
583
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
584
# Now archive all of the libraries from verilator witht he other modules we might have
585
        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
586
        @cd $(SIM_VLT_DIR) && \
587
        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
588
        ar rcs libVorpsoc_top.a verilated.o; \
589
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
590
                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
591
        done
592
 
593
$(SIM_VLT_DIR)/verilated.o:
594
        @echo; echo "\tCompiling verilated.o"; echo
595
        @cd $(SIM_VLT_DIR) && \
596
        $(MAKE) -f Vorpsoc_top.mk verilated.o
597
 
598
.PHONY: vlt_modules_compile
599
vlt_modules_compile:
600
# Compile the module files
601
        @echo; echo "\tCompiling SystemC models"
602
        @cd $(SIM_VLT_DIR) && \
603
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
604
                echo;echo "\t$$SYSCMODEL"; echo; \
605
                $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
606
        done
607
 
608
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
609
        @echo; echo "\tCompiling main design"; echo
610
        @cd $(SIM_VLT_DIR) && \
611
        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
612
 
613
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
614
# Now call verilator to generate the .mk files
615
        @echo; echo "\tGenerating makefiles with Verilator"; echo
616
        cd $(SIM_VLT_DIR) && \
617
        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
618
 
619
# SystemC modules library
620
$(SIM_VLT_DIR)/libmodules.a:
621
        @echo; echo "\tCompiling SystemC modules"; echo
622
        @$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
623
 
624
 
625
# Verilator command script
626
# Generate the compile script to give Verilator
627
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
628
        @echo; echo "\tGenerating verilator compile script"; echo
629
        @sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
630
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
631
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
632
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
633
                -e \\!^//.*\$$!d -e \\!^\$$!d;
634
 
635
.PHONY: vlt_model_links
636
vlt_model_links:
637
# Link all the required system C model files into the verilator work dir
638
        @echo; echo "\tLinking SystemC model source to verilator build path"; echo
639
        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
640
        @cd $(SIM_VLT_DIR) && \
641
        for SYSCMODEL in $(SYSC_MODELS); do \
642
                if [ ! -e $$SYSCMODEL.cpp ]; then \
643
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
644
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
645
                fi; \
646
        done
647
 
648
 
649
################################################################################
650
# Verilator test loop
651
################################################################################
652
 
653
# Verilator defaults to internal memories
654 40 julius
vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_dirs prepare_vlt
655 6 julius
        @echo
656
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
657
        @echo
658
        @for TEST in $(TESTS); do \
659
                echo "################################################################################"; \
660
                echo; \
661
                echo "\t#### Current test: $$TEST ####"; echo; \
662
                echo "\t#### Compiling software ####"; echo; \
663
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
664
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
665
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
666
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
667
                echo "\t#### Beginning simulation ####"; \
668
                time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
669
                if [ $$? -gt 0 ]; then exit $$?; fi; \
670
                TEST_RESULT=1; \
671
                echo; echo "\t####"; \
672
                if [ $$TEST_RESULT -gt 0 ]; then \
673
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
674
                else    echo "\t#### Test $$TEST FAILED ####";\
675
                fi; \
676
                echo "\t####"; echo; \
677
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
678
        done; \
679
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
680
 
681
 
682
 
683
################################################################################
684
# Architectural simulator test loop
685
################################################################################
686
 
687
# Verilator defaults to internal memories
688
sim-tests: prepare_sw_uart_printf
689
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
690
        @echo
691
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
692
        @echo
693
        @for TEST in $(TESTS); do \
694
                echo "################################################################################"; \
695
                echo; \
696
                echo "\t#### Current test: $$TEST ####"; echo; \
697
                echo "\t#### Compiling software ####"; echo; \
698
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
699
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
700
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
701
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
702
                echo;echo "\t#### Launching architectural simulator ####"; \
703
                time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
704
                if [ $$? -gt 0 ]; then exit $$?; fi; \
705
                if [ `tail -n 10 $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log | grep -c $(SIM_SUCCESS_MESSAGE)` -gt 0 ]; then \
706
                        TEST_RESULT=1; \
707
                fi; \
708
                echo; echo "\t####"; \
709
                if [ $$TEST_RESULT -gt 0 ]; then \
710
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
711
                else    echo "\t#### Test $$TEST FAILED ####";\
712
                fi; \
713
                echo "\t####"; echo; \
714
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
715
                unlink $(SIM_RUN_DIR)/$$TEST.or32; \
716
        done; \
717
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
718
 
719
 
720
 
721
################################################################################
722
# Cleaning rules
723
################################################################################
724
 
725 40 julius
clean: clean-sw clean-sim clean-sysc clean-rtl clean_vpi
726 6 julius
 
727
clean-sw:
728 44 julius
        @for SWDIR in `ls $(SW_DIR)`; do \
729
                echo $$SWDIR; \
730
                $(MAKE) -C $(SW_DIR)/$$SWDIR clean; \
731 6 julius
        done
732
 
733
clean-sim:
734
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
735 36 julius
 
736
clean-sysc:
737
# Clean away dependency files generated by verilator
738 42 julius
        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
739 36 julius
 
740
clean-rtl:
741
# Clean away temporary verilog source files
742
        rm -f $(RTL_VERILOG_DIR)/intercon.v
743 44 julius
        rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
744
 

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