URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [i2c_master_slave/] [i2c_master_slave.c] - Blame information for rev 403

Go to most recent revision | Details | Compare with Previous | View Log


/*************************************************************
* I2C functions for the Herveille i2c controller            *
*                                                           *
* Provides functions to read from and write to the I2C bus. *
* Master and slave mode are both supported                  *
*                                                           *
* Julius Baxter, julius@opencores.org                       *
*                                                           *
************************************************************/
 
#include "board.h"
#include "cpu-utils.h"
#include "i2c_master_slave.h"
 
inline unsigned char i2c_master_slave_read_reg(int core, unsigned char addr)
{
        return REG8((i2c_base_adr[core] + addr));
}
 
inline void i2c_master_slave_write_reg(int core, unsigned char addr,
                                       unsigned char data)
{
        REG8((i2c_base_adr[core] + addr)) = data;
}
 
int i2c_master_slave_wait_for_busy(int core)
{
        while (1) {
                // Check for busy flag in i2c status reg
                if (!
                    (i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR) &
                     I2C_MASTER_SLAVE_SR_BUSY))
                        return 0;
        }
}
 
int i2c_master_slave_wait_for_transfer(int core)
{
        volatile unsigned char status;
        // Wait for ongoing transmission to finish
        while (1) {
                status = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR);
                // If arbitration lost
                if ((status & I2C_MASTER_SLAVE_SR_ARB_LOST) ==
                    I2C_MASTER_SLAVE_SR_ARB_LOST)
                        return 2;
                // If TIP bit = o , stop waiting
                else if (!(status & I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG))
                        return 0;
        }
}
 
/***********************************************************
* i2c_master_slave_init_core                               *
*                                                          *
* Setup i2c core:                                          *
* Write prescaler register with parmeter passed, enable    *
* core in control register, optionally enable interrupts   *
************************************************************/
int i2c_master_slave_init_core(int core, unsigned short prescaler,
                               int interrupt_enable)
{
 
        // Setup I2C prescaler,
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERlo,
                                   prescaler & 0xff);
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERhi,
                                   (prescaler >> 8) & 0xff);
 
        // Enable I2C controller and optionally interrupts
        if (interrupt_enable)
                i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
                                           I2C_MASTER_SLAVE_CTR_CORE_ENABLE |
                                           I2C_MASTER_SLAVE_CTR_INTR_ENABLE);
        else
                i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
                                           I2C_MASTER_SLAVE_CTR_CORE_ENABLE);
 
        return 0;
 
}
 
/***********************************************************
* i2c_master_slave_deact_core                              *
*                                                          *
* Deactivate i2c core:                                     *
* Clear core enable and interrupt enable bits              *
************************************************************/
int i2c_master_slave_deact_core(int core)
{
 
 
  i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
                             i2c_master_slave_read_reg(core,
                                                       I2C_MASTER_SLAVE_CTR) &
                             ~(I2C_MASTER_SLAVE_CTR_CORE_ENABLE |
                               I2C_MASTER_SLAVE_CTR_INTR_ENABLE));
 
 
        return 0;
 
}
 
/***********************************************************
* i2c_master_slave_init_as_slave                           *
*                                                          *
* Setup i2c core to service slave accesses                 *
* OR in slave enable bit to control register               *
* Set slave address                                        *
************************************************************/
int i2c_master_slave_init_as_slave(int core, char addr)
{
 
        // Set slave enable bit
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
                                   i2c_master_slave_read_reg(core,
                                                             I2C_MASTER_SLAVE_CTR)
                                   | I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE);
        // Set slave address
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_SLADR, addr);
 
        return 0;
 
}
 
/***********************************************************
* i2c_master_slave_deact_as_slave                          *
*                                                          *
* Disable slave mode for this I2C core                     *
* Deassert slave eanble bit in control register            *
************************************************************/
int i2c_master_slave_deact_as_slave(int core)
{
        // Clear slave enable bit
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
                                   i2c_master_slave_read_reg(core,
                                                             I2C_MASTER_SLAVE_CTR)
                                   & ~I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE);
 
        return 0;
}
 
/***********************************************************
* i2c_master_slave_master_start                            *
*                                                          *
* Get the i2c bus.                                         *
************************************************************/
int i2c_master_slave_master_start(int core, unsigned char addr, int read)
{
 
        i2c_master_slave_wait_for_busy(core);
 
        // Set address in transfer register
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR,
                                   (addr << 1) | read);
 
        // Start and write the address
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                   I2C_MASTER_SLAVE_CR_START |
                                   I2C_MASTER_SLAVE_CR_WRITE);
 
        i2c_master_slave_wait_for_transfer(core);
 
        return 0;
}
 
/***********************************************************
* i2c_master_slave_master_write                            *
*                                                          *
* Send 1 byte of data                                      *
************************************************************/
int i2c_master_slave_master_write(int core, unsigned char data,
                                  int check_prev_ack, int stop)
{
        if (i2c_master_slave_wait_for_transfer(core))
                return 1;
 
        // present data
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR, data);
 
        if (!stop)
                // set command (write)
                i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                           I2C_MASTER_SLAVE_CR_WRITE);
        else
                // set command (write) and stop
                i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                           I2C_MASTER_SLAVE_CR_WRITE |
                                           I2C_MASTER_SLAVE_CR_STOP);
 
        return 0;
}
 
/***********************************************************
* i2c_master_slave_master_stop                             *
*                                                          *
* Send stop condition                                      *
************************************************************/
int i2c_master_slave_master_stop(int core)
{
        unsigned char status;
        unsigned char ready = 0;
 
        // Make I2C controller wait at end of finished byte
        if (i2c_master_slave_wait_for_transfer(core))
                return 1;
 
        // Send stop condition
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                   I2C_MASTER_SLAVE_CR_STOP);
 
        return 0;
}
 
/***********************************************************
* i2c_master_slave_master_read                             *
*                                                          *
* Read 1 byte of data                                      *
************************************************************/
int i2c_master_slave_master_read(int core, int check_prev_ack,
                                 int stop, char *data)
{
 
        // Make I2C controller wait at end of finished byte
        if (i2c_master_slave_wait_for_transfer(core))
                return 1;
 
        if (stop)
                i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                           I2C_MASTER_SLAVE_CR_READ |
                                           I2C_MASTER_SLAVE_CR_STOP);
        else
                i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                           I2C_MASTER_SLAVE_CR_READ);
 
        if (i2c_master_slave_wait_for_transfer(core))
                return 1;
 
        *data = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_RXR);
 
        return 0;
}
 
/***********************************************************
* i2c_master_slave_ack_interrupt                           *
*                                                          *
* Acknowledge interrupt has been serviced                  *
************************************************************/
int i2c_master_slave_ack_interrupt(int core)
{
 
        i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
                                   I2C_MASTER_SLAVE_CR_IACK);
 
        return 0;
}

Line No.	Rev	Author	Line
1	393	julius	`/*************************************************************`
2			`* I2C functions for the Herveille i2c controller *`
3			`* *`
4			`* Provides functions to read from and write to the I2C bus. *`
5			`* Master and slave mode are both supported *`
6			`* *`
7	403	julius	`* Julius Baxter, julius@opencores.org *`
8	393	julius	`* *`
9			`************************************************************/`
10
11			`#include "board.h"`
12			`#include "cpu-utils.h"`
13			`#include "i2c_master_slave.h"`
14
15	403	julius	`inline unsigned char i2c_master_slave_read_reg(int core, unsigned char addr)`
16	393	julius	`{`
17	403	julius	`return REG8((i2c_base_adr[core] + addr));`
18	393	julius	`}`
19	403	julius
20			`inline void i2c_master_slave_write_reg(int core, unsigned char addr,`
21			`unsigned char data)`
22	393	julius	`{`
23	403	julius	`REG8((i2c_base_adr[core] + addr)) = data;`
24	393	julius	`}`
25
26			`int i2c_master_slave_wait_for_busy(int core)`
27			`{`
28	403	julius	`while (1) {`
29			`// Check for busy flag in i2c status reg`
30			`if (!`
31			`(i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR) &`
32			`I2C_MASTER_SLAVE_SR_BUSY))`
33			`return 0;`
34			`}`
35	393	julius	`}`
36
37			`int i2c_master_slave_wait_for_transfer(int core)`
38			`{`
39	403	julius	`volatile unsigned char status;`
40			`// Wait for ongoing transmission to finish`
41			`while (1) {`
42			`status = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR);`
43			`// If arbitration lost`
44			`if ((status & I2C_MASTER_SLAVE_SR_ARB_LOST) ==`
45			`I2C_MASTER_SLAVE_SR_ARB_LOST)`
46			`return 2;`
47			`// If TIP bit = o , stop waiting`
48			`else if (!(status & I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG))`
49			`return 0;`
50			`}`
51	393	julius	`}`
52
53			`/***********************************************************`
54	403	julius	`* i2c_master_slave_init_core *`
55	393	julius	`* *`
56			`* Setup i2c core: *`
57			`* Write prescaler register with parmeter passed, enable *`
58			`* core in control register, optionally enable interrupts *`
59			`************************************************************/`
60	403	julius	`int i2c_master_slave_init_core(int core, unsigned short prescaler,`
61			`int interrupt_enable)`
62	393	julius	`{`
63
64	403	julius	`// Setup I2C prescaler,`
65			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERlo,`
66			`prescaler & 0xff);`
67			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERhi,`
68			`(prescaler >> 8) & 0xff);`
69	393	julius
70	403	julius	`// Enable I2C controller and optionally interrupts`
71			`if (interrupt_enable)`
72			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,`
73			`I2C_MASTER_SLAVE_CTR_CORE_ENABLE \|`
74			`I2C_MASTER_SLAVE_CTR_INTR_ENABLE);`
75			`else`
76			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,`
77			`I2C_MASTER_SLAVE_CTR_CORE_ENABLE);`
78	393	julius
79	403	julius	`return 0;`
80	393	julius
81			`}`
82
83			`/***********************************************************`
84	403	julius	`* i2c_master_slave_deact_core *`
85	393	julius	`* *`
86	403	julius	`* Deactivate i2c core: *`
87			`* Clear core enable and interrupt enable bits *`
88			`************************************************************/`
89			`int i2c_master_slave_deact_core(int core)`
90			`{`
91
92
93			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,`
94			`i2c_master_slave_read_reg(core,`
95			`I2C_MASTER_SLAVE_CTR) &`
96			`~(I2C_MASTER_SLAVE_CTR_CORE_ENABLE \|`
97			`I2C_MASTER_SLAVE_CTR_INTR_ENABLE));`
98
99
100			`return 0;`
101
102			`}`
103
104			`/***********************************************************`
105			`* i2c_master_slave_init_as_slave *`
106			`* *`
107			`* Setup i2c core to service slave accesses *`
108	393	julius	`* OR in slave enable bit to control register *`
109			`* Set slave address *`
110			`************************************************************/`
111	403	julius	`int i2c_master_slave_init_as_slave(int core, char addr)`
112	393	julius	`{`
113
114	403	julius	`// Set slave enable bit`
115			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,`
116			`i2c_master_slave_read_reg(core,`
117			`I2C_MASTER_SLAVE_CTR)`
118			`\| I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE);`
119			`// Set slave address`
120			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_SLADR, addr);`
121
122			`return 0;`
123
124	393	julius	`}`
125
126			`/***********************************************************`
127	403	julius	`* i2c_master_slave_deact_as_slave *`
128	393	julius	`* *`
129			`* Disable slave mode for this I2C core *`
130			`* Deassert slave eanble bit in control register *`
131			`************************************************************/`
132	403	julius	`int i2c_master_slave_deact_as_slave(int core)`
133	393	julius	`{`
134	403	julius	`// Clear slave enable bit`
135			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,`
136			`i2c_master_slave_read_reg(core,`
137			`I2C_MASTER_SLAVE_CTR)`
138			`& ~I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE);`
139
140			`return 0;`
141	393	julius	`}`
142
143			`/***********************************************************`
144	403	julius	`* i2c_master_slave_master_start *`
145	393	julius	`* *`
146			`* Get the i2c bus. *`
147			`************************************************************/`
148	403	julius	`int i2c_master_slave_master_start(int core, unsigned char addr, int read)`
149			`{`
150	393	julius
151	403	julius	`i2c_master_slave_wait_for_busy(core);`
152	393	julius
153	403	julius	`// Set address in transfer register`
154			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR,`
155			`(addr << 1) \| read);`
156
157			`// Start and write the address`
158			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
159			`I2C_MASTER_SLAVE_CR_START \|`
160			`I2C_MASTER_SLAVE_CR_WRITE);`
161
162			`i2c_master_slave_wait_for_transfer(core);`
163
164			`return 0;`
165	393	julius	`}`
166
167			`/***********************************************************`
168	403	julius	`* i2c_master_slave_master_write *`
169	393	julius	`* *`
170			`* Send 1 byte of data *`
171			`************************************************************/`
172	403	julius	`int i2c_master_slave_master_write(int core, unsigned char data,`
173			`int check_prev_ack, int stop)`
174	393	julius	`{`
175	403	julius	`if (i2c_master_slave_wait_for_transfer(core))`
176			`return 1;`
177
178			`// present data`
179			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR, data);`
180	393	julius
181	403	julius	`if (!stop)`
182			`// set command (write)`
183			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
184			`I2C_MASTER_SLAVE_CR_WRITE);`
185			`else`
186			`// set command (write) and stop`
187			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
188			`I2C_MASTER_SLAVE_CR_WRITE \|`
189			`I2C_MASTER_SLAVE_CR_STOP);`
190
191			`return 0;`
192	393	julius	`}`
193
194			`/***********************************************************`
195	403	julius	`* i2c_master_slave_master_stop *`
196	393	julius	`* *`
197			`* Send stop condition *`
198			`************************************************************/`
199	403	julius	`int i2c_master_slave_master_stop(int core)`
200			`{`
201			`unsigned char status;`
202			`unsigned char ready = 0;`
203	393	julius
204	403	julius	`// Make I2C controller wait at end of finished byte`
205			`if (i2c_master_slave_wait_for_transfer(core))`
206			`return 1;`
207	393	julius
208	403	julius	`// Send stop condition`
209			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
210			`I2C_MASTER_SLAVE_CR_STOP);`
211
212			`return 0;`
213	393	julius	`}`
214
215			`/***********************************************************`
216	403	julius	`* i2c_master_slave_master_read *`
217	393	julius	`* *`
218			`* Read 1 byte of data *`
219			`************************************************************/`
220	403	julius	`int i2c_master_slave_master_read(int core, int check_prev_ack,`
221			`int stop, char *data)`
222			`{`
223	393	julius
224	403	julius	`// Make I2C controller wait at end of finished byte`
225			`if (i2c_master_slave_wait_for_transfer(core))`
226			`return 1;`
227	393	julius
228	403	julius	`if (stop)`
229			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
230			`I2C_MASTER_SLAVE_CR_READ \|`
231			`I2C_MASTER_SLAVE_CR_STOP);`
232			`else`
233			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
234			`I2C_MASTER_SLAVE_CR_READ);`
235	393	julius
236	403	julius	`if (i2c_master_slave_wait_for_transfer(core))`
237			`return 1;`
238
239			`*data = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_RXR);`
240
241			`return 0;`
242	393	julius	`}`
243
244			`/***********************************************************`
245	403	julius	`* i2c_master_slave_ack_interrupt *`
246	393	julius	`* *`
247			`* Acknowledge interrupt has been serviced *`
248			`************************************************************/`
249	403	julius	`int i2c_master_slave_ack_interrupt(int core)`
250	393	julius	`{`
251	403	julius
252			`i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,`
253			`I2C_MASTER_SLAVE_CR_IACK);`
254
255			`return 0;`
256	393	julius	`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [i2c_master_slave/] [i2c_master_slave.c] - Blame information for rev 403