URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [uart/] [uart.c] - Blame information for rev 485

Details | Compare with Previous | View Log


#include "cpu-utils.h"
#include "board.h"
#include "uart.h"
 
#ifdef UART_NUM_CORES
const int UART_BASE_ADR[UART_NUM_CORES] = {UART_BASE_ADDRESSES_CSV};
const int UART_BAUDS[UART_NUM_CORES] = {UART_BAUD_RATES_CSV};
#else
const int UART_BASE_ADR[1] = {0};
const int UART_BAUDS[1] = {0};
#endif
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR(core)                    \
        do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE(core)                     \
        do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR(core)                     \
         do { \
                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(int core)
{
        int divisor;
        float float_divisor;
        /* Reset receiver and transmiter */
        REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
        /* Disable all interrupts */
        REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
 
        /* Set 8 bit char, 1 stop bit, no parity */
        REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
        /* Set baud rate */
        float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);
        float_divisor += 0.50f; // Ensure round up
        divisor = (int) float_divisor;
 
        REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
        REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
        REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
        REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
 
        return;
}
 
void uart_putc(int core, char c)
{
        unsigned char lsr;
 
        WAIT_FOR_THRE(core);
        REG8(UART_BASE_ADR[core] + UART_TX) = c;
        if(c == '\n') {
          WAIT_FOR_THRE(core);
          REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
        }
        WAIT_FOR_XMITR(core);
}
 
// Only used when we know THRE is empty, typically in interrupt
void uart_putc_noblock(int core, char c)
{
  REG8(UART_BASE_ADR[core] + UART_TX) = c;
}
 
 
char uart_getc(int core)
{
        unsigned char lsr;
        char c;
 
        WAIT_FOR_CHAR(core);
        c = REG8(UART_BASE_ADR[core] + UART_RX);
        return c;
}
 
int uart_check_for_char(int core)
{
  return CHECK_FOR_CHAR(core);
}
 
void uart_rxint_enable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_RDI;
}
 
void uart_rxint_disable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);
}
 
void uart_txint_enable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_THRI;
}
 
void uart_txint_disable(int core)
{
  REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);
}
 
char uart_get_iir(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_IIR);
}
 
 
char uart_get_lsr(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_LSR);
}
 
 
char uart_get_msr(int core)
{
  return REG8(UART_BASE_ADR[core] + UART_MSR);
}

Line No.	Rev	Author	Line
1	393	julius	`#include "cpu-utils.h"`
2	349	julius	`#include "board.h"`
3			`#include "uart.h"`
4
5	485	julius	`#ifdef UART_NUM_CORES`
6			`const int UART_BASE_ADR[UART_NUM_CORES] = {UART_BASE_ADDRESSES_CSV};`
7			`const int UART_BAUDS[UART_NUM_CORES] = {UART_BAUD_RATES_CSV};`
8			`#else`
9			`const int UART_BASE_ADR[1] = {0};`
10			`const int UART_BAUDS[1] = {0};`
11			`#endif`
12	349	julius
13			`#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)`
14
15			`#define WAIT_FOR_XMITR(core) \`
16			`do { \`
17			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
18			`} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)`
19
20			`#define WAIT_FOR_THRE(core) \`
21			`do { \`
22			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
23			`} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)`
24
25			`#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)`
26
27			`#define WAIT_FOR_CHAR(core) \`
28			`do { \`
29			`lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \`
30			`} while ((lsr & UART_LSR_DR) != UART_LSR_DR)`
31
32			`#define UART_TX_BUFF_LEN 32`
33			`#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)`
34
35			`char tx_buff[UART_TX_BUFF_LEN];`
36			`volatile int tx_level, rx_level;`
37
38			`void uart_init(int core)`
39			`{`
40			`int divisor;`
41			`float float_divisor;`
42			`/* Reset receiver and transmiter */`
43			`REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT \| UART_FCR_TRIGGER_14;`
44
45			`/* Disable all interrupts */`
46			`REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;`
47
48			`/* Set 8 bit char, 1 stop bit, no parity */`
49			`REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP \| UART_LCR_PARITY);`
50
51			`/* Set baud rate */`
52			`float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);`
53			`float_divisor += 0.50f; // Ensure round up`
54			`divisor = (int) float_divisor;`
55
56			`REG8(UART_BASE_ADR[core] + UART_LCR) \|= UART_LCR_DLAB;`
57			`REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;`
58			`REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;`
59			`REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);`
60
61			`return;`
62			`}`
63
64			`void uart_putc(int core, char c)`
65			`{`
66			`unsigned char lsr;`
67
68			`WAIT_FOR_THRE(core);`
69			`REG8(UART_BASE_ADR[core] + UART_TX) = c;`
70			`if(c == '\n') {`
71			`WAIT_FOR_THRE(core);`
72			`REG8(UART_BASE_ADR[core] + UART_TX) = '\r';`
73			`}`
74			`WAIT_FOR_XMITR(core);`
75			`}`
76
77			`// Only used when we know THRE is empty, typically in interrupt`
78			`void uart_putc_noblock(int core, char c)`
79			`{`
80			`REG8(UART_BASE_ADR[core] + UART_TX) = c;`
81			`}`
82
83
84			`char uart_getc(int core)`
85			`{`
86			`unsigned char lsr;`
87			`char c;`
88
89			`WAIT_FOR_CHAR(core);`
90			`c = REG8(UART_BASE_ADR[core] + UART_RX);`
91			`return c;`
92			`}`
93
94			`int uart_check_for_char(int core)`
95			`{`
96			`return CHECK_FOR_CHAR(core);`
97			`}`
98
99			`void uart_rxint_enable(int core)`
100			`{`
101			`REG8(UART_BASE_ADR[core] + UART_IER) \|= UART_IER_RDI;`
102			`}`
103
104			`void uart_rxint_disable(int core)`
105			`{`
106			`REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);`
107			`}`
108
109			`void uart_txint_enable(int core)`
110			`{`
111			`REG8(UART_BASE_ADR[core] + UART_IER) \|= UART_IER_THRI;`
112			`}`
113
114			`void uart_txint_disable(int core)`
115			`{`
116			`REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);`
117			`}`
118
119			`char uart_get_iir(int core)`
120			`{`
121			`return REG8(UART_BASE_ADR[core] + UART_IIR);`
122			`}`
123
124
125			`char uart_get_lsr(int core)`
126			`{`
127			`return REG8(UART_BASE_ADR[core] + UART_LSR);`
128			`}`
129
130
131			`char uart_get_msr(int core)`
132			`{`
133			`return REG8(UART_BASE_ADR[core] + UART_MSR);`
134			`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [uart/] [uart.c] - Blame information for rev 485