OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-basic.S] - Blame information for rev 425

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 349 julius 
/*
2 
 
3 
        Basic instruction set test
4 
 
5 
        Requires hardware multiply (uses l.muli and l.mul)
6 
 
7 
        We specify our own reset and initialisation routines as we don't link
8 
        in the usual initialisation code.
9 
 
10 
        Based on original or1200 instruction set test
11 
 
12 
        modified by
13 
 
14 
        Julius Baxter, julius@opencores.org
15 
        Tadej Markovic, tadej@opencores.org
16 
 
17 
*/
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
 
45 
 
46 
#include "spr-defs.h"
47 
#include "board.h"
48 
#include "or1200-defines.h"
49 
 
50 
// Check multiply unit is enabled before trying to run this test
51 
#ifndef OR1200_MULT_IMPLEMENTED
52 
# error
53 
# error No multiply unit detected. This test requires hardware multiply support
54 
# error
55 
#endif
56 
 
57 
 
58 
/* =================================================== [ exceptions ] === */
59 
        .section .vectors, "ax"
60 
 
61 
 
62 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
63 
        .org 0x100
64 
        l.movhi r0, 0
65 
        /* Clear status register */
66 
        l.ori r1, r0, SPR_SR_SM
67 
        l.mtspr r0, r1, SPR_SR
68 
        /* Clear timer  */
69 
        l.mtspr r0, r0, SPR_TTMR
70 
 
71 
        /* Jump to program initialisation code */
72 
        .global _start
73 
        l.movhi r4, hi(_start)
74 
        l.ori r4, r4, lo(_start)
75 
        l.jr    r4
76 
        l.nop
77 
 
78 
 
79 
/* =================================================== [ text ] === */
80 
        .section .text
81 
 
82 
/* =================================================== [ start ] === */
83 
 
84 
        .global _start
85 
_start:
86 
 
87 
        /* Instruction cache enable */
88 
        /* Check if IC present and skip enabling otherwise */
89 
        l.mfspr r24,r0,SPR_UPR
90 
        l.andi  r26,r24,SPR_UPR_ICP
91 
        l.sfeq  r26,r0
92 
        l.bf    .L8
93 
        l.nop
94 
 
95 
        /* Disable IC */
96 
        l.mfspr r6,r0,SPR_SR
97 
        l.addi  r5,r0,-1
98 
        l.xori  r5,r5,SPR_SR_ICE
99 
        l.and   r5,r6,r5
100 
        l.mtspr r0,r5,SPR_SR
101 
 
102 
        /* Establish cache block size
103 
        If BS=0, 16;
104 
        If BS=1, 32;
105 
        r14 contain block size
106 
        */
107 
        l.mfspr r24,r0,SPR_ICCFGR
108 
        l.andi  r26,r24,SPR_ICCFGR_CBS
109 
        l.srli  r28,r26,7
110 
        l.ori   r30,r0,16
111 
        l.sll   r14,r30,r28
112 
 
113 
        /* Establish number of cache sets
114 
        r16 contains number of cache sets
115 
        r28 contains log(# of cache sets)
116 
        */
117 
        l.andi  r26,r24,SPR_ICCFGR_NCS
118 
        l.srli  r28,r26,3
119 
        l.ori   r30,r0,1
120 
        l.sll   r16,r30,r28
121 
 
122 
        /* Invalidate IC */
123 
        l.addi  r6,r0,0
124 
        l.sll   r5,r14,r28
125 
 
126 
.L7:
127 
        l.mtspr r0,r6,SPR_ICBIR
128 
        l.sfne  r6,r5
129 
        l.bf    .L7
130 
        l.add   r6,r6,r14
131 
 
132 
        /* Enable IC */
133 
        l.mfspr r6,r0,SPR_SR
134 
        l.ori   r6,r6,SPR_SR_ICE
135 
        l.mtspr r0,r6,SPR_SR
136 
        l.nop
137 
        l.nop
138 
        l.nop
139 
        l.nop
140 
        l.nop
141 
        l.nop
142 
        l.nop
143 
        l.nop
144 
 
145 
.L8:
146 
        /* Data cache enable */
147 
        /* Check if DC present and skip enabling otherwise */
148 
        l.mfspr r24,r0,SPR_UPR
149 
        l.andi  r26,r24,SPR_UPR_DCP
150 
        l.sfeq  r26,r0
151 
        l.bf    .L10
152 
        l.nop
153 
        /* Disable DC */
154 
        l.mfspr r6,r0,SPR_SR
155 
        l.addi  r5,r0,-1
156 
        l.xori  r5,r5,SPR_SR_DCE
157 
        l.and   r5,r6,r5
158 
        l.mtspr r0,r5,SPR_SR
159 
        /* Establish cache block size
160 
           If BS=0, 16;
161 
           If BS=1, 32;
162 
           r14 contain block size
163 
        */
164 
        l.mfspr r24,r0,SPR_DCCFGR
165 
        l.andi  r26,r24,SPR_DCCFGR_CBS
166 
        l.srli  r28,r26,7
167 
        l.ori   r30,r0,16
168 
        l.sll   r14,r30,r28
169 
        /* Establish number of cache sets
170 
           r16 contains number of cache sets
171 
           r28 contains log(# of cache sets)
172 
        */
173 
        l.andi  r26,r24,SPR_DCCFGR_NCS
174 
        l.srli  r28,r26,3
175 
        l.ori   r30,r0,1
176 
        l.sll   r16,r30,r28
177 
        /* Invalidate DC */
178 
        l.addi  r6,r0,0
179 
        l.sll   r5,r14,r28
180 
.L9:
181 
        l.mtspr r0,r6,SPR_DCBIR
182 
        l.sfne  r6,r5
183 
        l.bf    .L9
184 
        l.add   r6,r6,r14
185 
        /* Enable DC */
186 
        l.mfspr r6,r0,SPR_SR
187 
        l.ori   r6,r6,SPR_SR_DCE
188 
        l.mtspr r0,r6,SPR_SR
189 
.L10:
190 
        // Kick off test
191 
        l.jal   _main
192 
        l.nop
193 
 
194 
 
195 
 
196 
/* =================================================== [ main ] === */
197 
 
198 
        .global _main
199 
_main:
200 
        l.nop
201 
        l.j     _regs
202 
        l.nop
203 
 
204 
 
205 
_regs:
206 
        l.addi  r1,r0,0x1
207 
        l.addi  r2,r1,0x2
208 
        l.addi  r3,r2,0x4
209 
        l.addi  r4,r3,0x8
210 
        l.addi  r5,r4,0x10
211 
        l.addi  r6,r5,0x20
212 
        l.addi  r7,r6,0x40
213 
        l.addi  r8,r7,0x80
214 
        l.addi  r9,r8,0x100
215 
        l.addi  r10,r9,0x200
216 
        l.addi  r11,r10,0x400
217 
        l.addi  r12,r11,0x800
218 
        l.addi  r13,r12,0x1000
219 
        l.addi  r14,r13,0x2000
220 
        l.addi  r15,r14,0x4000
221 
        l.addi  r16,r15,0x8000
222 
 
223 
        l.sub   r31,r0,r1
224 
        l.sub   r30,r31,r2
225 
        l.sub   r29,r30,r3
226 
        l.sub   r28,r29,r4
227 
        l.sub   r27,r28,r5
228 
        l.sub   r26,r27,r6
229 
        l.sub   r25,r26,r7
230 
        l.sub   r24,r25,r8
231 
        l.sub   r23,r24,r9
232 
        l.sub   r22,r23,r10
233 
        l.sub   r21,r22,r11
234 
        l.sub   r20,r21,r12
235 
        l.sub   r19,r20,r13
236 
        l.sub   r18,r19,r14
237 
        l.sub   r17,r18,r15
238 
        l.sub   r16,r17,r16
239 
        l.movhi r31,0x0000
240 
        l.ori   r31,r31,0x0040
241 
 
242 
        l.mtspr r0,r16,0x1234   /* Should be 0xffff0012 */
243 
 
244 
        l.sw    0(r31),r16
245 
 
246 
 
247 
_mem:   l.movhi r3,0x1234
248 
        l.ori   r3,r3,0x5678
249 
 
250 
        l.sw    4(r31),r3
251 
 
252 
        l.lbz   r4,4(r31)
253 
        l.add   r8,r8,r4
254 
        l.sb    11(r31),r4
255 
        l.lbz   r4,5(r31)
256 
        l.add   r8,r8,r4
257 
        l.sb    10(r31),r4
258 
        l.lbz   r4,6(r31)
259 
        l.add   r8,r8,r4
260 
        l.sb    9(r31),r4
261 
        l.lbz   r4,7(r31)
262 
        l.add   r8,r8,r4
263 
        l.sb    8(r31),r4
264 
 
265 
        l.lbs   r4,8(r31)
266 
        l.add   r8,r8,r4
267 
        l.sb    7(r31),r4
268 
        l.lbs   r4,9(r31)
269 
        l.add   r8,r8,r4
270 
        l.sb    6(r31),r4
271 
        l.lbs   r4,10(r31)
272 
        l.add   r8,r8,r4
273 
        l.sb    5(r31),r4
274 
        l.lbs   r4,11(r31)
275 
        l.add   r8,r8,r4
276 
        l.sb    4(r31),r4
277 
 
278 
        l.lhz   r4,4(r31)
279 
        l.add   r8,r8,r4
280 
        l.sh    10(r31),r4
281 
        l.lhz   r4,6(r31)
282 
        l.add   r8,r8,r4
283 
        l.sh    8(r31),r4
284 
 
285 
        l.lhs   r4,8(r31)
286 
        l.add   r8,r8,r4
287 
        l.sh    6(r31),r4
288 
        l.lhs   r4,10(r31)
289 
        l.add   r8,r8,r4
290 
        l.sh    4(r31),r4
291 
 
292 
        l.lwz   r4,4(r31)
293 
        l.add   r8,r8,r4
294 
 
295 
        l.mtspr r0,r8,0x1234   /* Should be 0x12352af7 */
296 
 
297 
        l.lwz   r9,0(r31)
298 
        l.add   r8,r9,r8
299 
        l.sw    0(r31),r8
300 
 
301 
 
302 
_arith:
303 
        l.addi  r3,r0,1
304 
        l.addi  r4,r0,2
305 
        l.addi  r5,r0,-1
306 
        l.addi  r6,r0,-1
307 
        l.addi  r8,r0,0
308 
 
309 
        l.sub   r7,r5,r3
310 
        l.sub   r8,r3,r5
311 
        l.add   r8,r8,r7
312 
 
313 
#       l.div   r7,r7,r4
314 
        l.add   r9,r3,r4
315 
        l.mul   r7,r9,r7
316 
#       l.divu  r7,r7,r4
317 
        l.add   r8,r8,r7
318 
 
319 
        l.mtspr r0,r8,0x1234   /* Should be 0x7ffffffe */
320 
 
321 
        l.lwz   r9,0(r31)
322 
        l.add   r8,r9,r8
323 
        l.sw    0(r31),r8
324 
 
325 
 
326 
_log:
327 
        l.addi  r3,r0,1
328 
        l.addi  r4,r0,2
329 
        l.addi  r5,r0,-1
330 
        l.addi  r6,r0,-1
331 
        l.addi  r8,r0,0
332 
 
333 
        l.andi  r8,r8,1
334 
        l.and   r8,r8,r3
335 
 
336 
        l.xori  r8,r5,0xa5a5
337 
        l.xor   r8,r8,r5
338 
 
339 
        l.ori   r8,r8,2
340 
        l.or    r8,r8,r4
341 
 
342 
        l.mtspr r0,r8,0x1234   /* Should be 0xffffa5a7 */
343 
 
344 
        l.lwz   r9,0(r31)
345 
        l.add   r8,r9,r8
346 
        l.sw    0(r31),r8
347 
 
348 
 
349 
_shift:
350 
        l.addi  r3,r0,1
351 
        l.addi  r4,r0,2
352 
        l.addi  r5,r0,-1
353 
        l.addi  r6,r0,-1
354 
        l.addi  r8,r0,0
355 
 
356 
        l.slli  r8,r5,6
357 
        l.sll   r8,r8,r4
358 
 
359 
        l.srli  r8,r8,6
360 
        l.srl   r8,r8,r4
361 
 
362 
        l.srai  r8,r8,2
363 
        l.sra   r8,r8,r4
364 
 
365 
        l.mtspr r0,r8,0x1234   /* Should be 0x000fffff */
366 
 
367 
        l.lwz   r9,0(r31)
368 
        l.add   r8,r9,r8
369 
        l.sw    0(r31),r8
370 
 
371 
 
372 
_flag:
373 
        l.addi  r3,r0,1
374 
        l.addi  r4,r0,-2
375 
        l.addi  r8,r0,0
376 
 
377 
        l.sfeq  r3,r3
378 
        l.mfspr r5,r0,17
379 
        l.andi  r4,r5,0x200
380 
        l.add   r8,r8,r4
381 
 
382 
        l.sfeq  r3,r4
383 
        l.mfspr r5,r0,17
384 
        l.andi  r4,r5,0x200
385 
        l.add   r8,r8,r4
386 
 
387 
        l.sfeqi r3,1
388 
        l.mfspr r5,r0,17
389 
        l.andi  r4,r5,0x200
390 
        l.add   r8,r8,r4
391 
 
392 
        l.sfeqi r3,-2
393 
        l.mfspr r5,r0,17
394 
        l.andi  r4,r5,0x200
395 
        l.add   r8,r8,r4
396 
 
397 
        l.sfne  r3,r3
398 
        l.mfspr r5,r0,17
399 
        l.andi  r4,r5,0x200
400 
        l.add   r8,r8,r4
401 
 
402 
        l.sfne  r3,r4
403 
        l.mfspr r5,r0,17
404 
        l.andi  r4,r5,0x200
405 
        l.add   r8,r8,r4
406 
 
407 
        l.sfnei r3,1
408 
        l.mfspr r5,r0,17
409 
        l.andi  r4,r5,0x200
410 
        l.add   r8,r8,r4
411 
 
412 
        l.sfnei r3,-2
413 
        l.mfspr r5,r0,17
414 
        l.andi  r4,r5,0x200
415 
        l.add   r8,r8,r4
416 
 
417 
        l.sfgtu r3,r3
418 
        l.mfspr r5,r0,17
419 
        l.andi  r4,r5,0x200
420 
        l.add   r8,r8,r4
421 
 
422 
        l.sfgtu r3,r4
423 
        l.mfspr r5,r0,17
424 
        l.andi  r4,r5,0x200
425 
        l.add   r8,r8,r4
426 
 
427 
        l.sfgtui        r3,1
428 
        l.mfspr r5,r0,17
429 
        l.andi  r4,r5,0x200
430 
        l.add   r8,r8,r4
431 
 
432 
        l.sfgtui        r3,-2
433 
        l.mfspr r5,r0,17
434 
        l.andi  r4,r5,0x200
435 
        l.add   r8,r8,r4
436 
 
437 
        l.sfgeu r3,r3
438 
        l.mfspr r5,r0,17
439 
        l.andi  r4,r5,0x200
440 
        l.add   r8,r8,r4
441 
 
442 
        l.sfgeu r3,r4
443 
        l.mfspr r5,r0,17
444 
        l.andi  r4,r5,0x200
445 
        l.add   r8,r8,r4
446 
 
447 
        l.sfgeui        r3,1
448 
        l.mfspr r5,r0,17
449 
        l.andi  r4,r5,0x200
450 
        l.add   r8,r8,r4
451 
 
452 
        l.sfgeui        r3,-2
453 
        l.mfspr r5,r0,17
454 
        l.andi  r4,r5,0x200
455 
        l.add   r8,r8,r4
456 
 
457 
        l.sfltu r3,r3
458 
        l.mfspr r5,r0,17
459 
        l.andi  r4,r5,0x200
460 
        l.add   r8,r8,r4
461 
 
462 
        l.sfltu r3,r4
463 
        l.mfspr r5,r0,17
464 
        l.andi  r4,r5,0x200
465 
        l.add   r8,r8,r4
466 
 
467 
        l.sfltui        r3,1
468 
        l.mfspr r5,r0,17
469 
        l.andi  r4,r5,0x200
470 
        l.add   r8,r8,r4
471 
 
472 
        l.sfltui        r3,-2
473 
        l.mfspr r5,r0,17
474 
        l.andi  r4,r5,0x200
475 
        l.add   r8,r8,r4
476 
 
477 
        l.sfleu r3,r3
478 
        l.mfspr r5,r0,17
479 
        l.andi  r4,r5,0x200
480 
        l.add   r8,r8,r4
481 
 
482 
        l.sfleu r3,r4
483 
        l.mfspr r5,r0,17
484 
        l.andi  r4,r5,0x200
485 
        l.add   r8,r8,r4
486 
 
487 
        l.sfleui        r3,1
488 
        l.mfspr r5,r0,17
489 
        l.andi  r4,r5,0x200
490 
        l.add   r8,r8,r4
491 
 
492 
        l.sfleui        r3,-2
493 
        l.mfspr r5,r0,17
494 
        l.andi  r4,r5,0x200
495 
        l.add   r8,r8,r4
496 
 
497 
        l.sfgts r3,r3
498 
        l.mfspr r5,r0,17
499 
        l.andi  r4,r5,0x200
500 
        l.add   r8,r8,r4
501 
 
502 
        l.sfgts r3,r4
503 
        l.mfspr r5,r0,17
504 
        l.andi  r4,r5,0x200
505 
        l.add   r8,r8,r4
506 
 
507 
        l.sfgtsi        r3,1
508 
        l.mfspr r5,r0,17
509 
        l.andi  r4,r5,0x200
510 
        l.add   r8,r8,r4
511 
 
512 
        l.sfgtsi        r3,-2
513 
        l.mfspr r5,r0,17
514 
        l.andi  r4,r5,0x200
515 
        l.add   r8,r8,r4
516 
 
517 
        l.sfges r3,r3
518 
        l.mfspr r5,r0,17
519 
        l.andi  r4,r5,0x200
520 
        l.add   r8,r8,r4
521 
 
522 
        l.sfges r3,r4
523 
        l.mfspr r5,r0,17
524 
        l.andi  r4,r5,0x200
525 
        l.add   r8,r8,r4
526 
 
527 
        l.sfgesi        r3,1
528 
        l.mfspr r5,r0,17
529 
        l.andi  r4,r5,0x200
530 
        l.add   r8,r8,r4
531 
 
532 
        l.sfgesi        r3,-2
533 
        l.mfspr r5,r0,17
534 
        l.andi  r4,r5,0x200
535 
        l.add   r8,r8,r4
536 
 
537 
        l.sflts r3,r3
538 
        l.mfspr r5,r0,17
539 
        l.andi  r4,r5,0x200
540 
        l.add   r8,r8,r4
541 
 
542 
        l.sflts r3,r4
543 
        l.mfspr r5,r0,17
544 
        l.andi  r4,r5,0x200
545 
        l.add   r8,r8,r4
546 
 
547 
        l.sfltsi        r3,1
548 
        l.mfspr r5,r0,17
549 
        l.andi  r4,r5,0x200
550 
        l.add   r8,r8,r4
551 
 
552 
        l.sfltsi        r3,-2
553 
        l.mfspr r5,r0,17
554 
        l.andi  r4,r5,0x200
555 
        l.add   r8,r8,r4
556 
 
557 
        l.sfles r3,r3
558 
        l.mfspr r5,r0,17
559 
        l.andi  r4,r5,0x200
560 
        l.add   r8,r8,r4
561 
 
562 
        l.sfles r3,r4
563 
        l.mfspr r5,r0,17
564 
        l.andi  r4,r5,0x200
565 
        l.add   r8,r8,r4
566 
 
567 
        l.sflesi        r3,1
568 
        l.mfspr r5,r0,17
569 
        l.andi  r4,r5,0x200
570 
        l.add   r8,r8,r4
571 
 
572 
        l.sflesi        r3,-2
573 
        l.mfspr r5,r0,17
574 
        l.andi  r4,r5,0x200
575 
        l.add   r8,r8,r4
576 
 
577 
        l.mtspr r0,r8,0x1234   /* Should be 0x00002800 */
578 
 
579 
        l.lwz   r9,0(r31)
580 
        l.add   r8,r9,r8
581 
        l.sw    0(r31),r8
582 
 
583 
 
584 
_dslot:
585 
        l.addi  r14,r0,0x4      /* inc. loop cnt. - must be non-zero */
586 
                                /* and operand at 1st operation */
587 
        l.addi  r15,r0,0x14     /* inc. cnt. limit value (4+4+4+4+4) */
588 
        l.addi  r21,r0,0x40     /* mul. by 2 cnt. limit value (4*2*2*2*2) */
589 
        l.addi  r16,r0,0x10     /* dec. loop cnt. - limits at 0 */
590 
                                /* loop counters are changed by 4 due */
591 
                                /* to value is used by l.lwz/l.sw */
592 
        l.addi  r17,r0,7        /* operand at 2nd operation */
593 
                                /* and test result */
594 
        l.addi  r18,r0,8        /* operand at 2nd operation */
595 
        l.addi  r19,r0,9        /* operand at 3rd operation */
596 
        l.addi  r20,r0,-1       /* xor every intermediate result by */
597 
                                /* value 0xffffffff */
598 
 
599 
        l.sw    (0x0)(r14),r0   /* init RAM to zero */
600 
        l.sw    (0x4)(r14),r0
601 
        l.sw    (0x8)(r14),r0
602 
        l.sw    (0xc)(r14),r0
603 
        l.sw    (0x10)(r14),r0
604 
        l.sw    (0x14)(r14),r0
605 
        l.sw    (0x18)(r14),r0
606 
        l.sw    (0x1c)(r14),r0
607 
        l.sw    (0x20)(r14),r0
608 
        l.sw    (0x24)(r14),r0
609 
        l.sw    (0x28)(r14),r0
610 
        l.sw    (0x2c)(r14),r0
611 
 
612 
 
613 
        /* ins. in dslot - loop 1: */
614 
        /* 1st operation operand before branch is NOT used to set flag */
615 
        /* 1st and 2nd operation operands before and after branch are NOT related */
616 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
617 
        /* 1st operation before branch is SINGLE cycle */
618 
        /* 2nd operation after branch/before jump is SINGLE cycle */
619 
        /* 3rd operation after jump is SINGLE cycle */
620 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
621 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
622 
_D1:
623 
        l.add   r17,r17,r14     /* merge test case operands */
624 
        l.add   r17,r17,r19     /* merge test case operands */
625 
        l.xor   r17,r17,r20     /* invert test result value */
626 
        l.addi  r16,r16,-4      /* dec. cnt. */
627 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
628 
        l.sfeqi r16,0
629 
        l.bf    _D2s
630 
        l.add   r17,r17,r18     /* r17,r18..2nd opertion operands */
631 
        l.j     _D1
632 
        l.addi  r19,r19,1       /* r19..3rd operation operand */
633 
 
634 
 
635 
        /* ins. in dslot - loop 2: */
636 
        /* 1st operation operand before branch is used to set flag */
637 
        /* 1st and 2nd operation operands before and after branch are NOT related */
638 
        /* 2nd and 3rd operation operands before and after jump are related */
639 
        /* 1st operation before branch is SINGLE cycle */
640 
        /* 2nd operation after branch/before jump is SINGLE cycle */
641 
        /* 3rd operation after jump is SINGLE cycle */
642 
_D2s:
643 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
644 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
645 
_D2:
646 
        l.add   r17,r17,r14     /* merge test case operands */
647 
        l.add   r17,r17,r19     /* merge test case operands */
648 
        l.xor   r17,r17,r20     /* invert test result value */
649 
        l.addi  r16,r16,-4      /* dec. cnt. */
650 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
651 
        l.sfgeu r14,r15
652 
        l.bf    _D3s
653 
        l.add   r17,r17,r18     /* r17,r18..2nd opertion operands */
654 
        l.j     _D2
655 
        l.addi  r19,r17,1       /* r19,r17..3rd operation operand */
656 
 
657 
 
658 
        /* ins. in dslot - loop 3: */
659 
        /* 1st operation operand before branch is NOT used to set flag */
660 
        /* 1st and 2nd operation operands before and after branch are related */
661 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
662 
        /* 1st operation before branch is SINGLE cycle */
663 
        /* 2nd operation after branch/before jump is SINGLE cycle */
664 
        /* 3rd operation after jump is MULTI cycle */
665 
_D3s:
666 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
667 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
668 
_D3:
669 
        l.add   r17,r17,r14     /* merge test case operands */
670 
        l.add   r17,r17,r19     /* merge test case operands */
671 
        l.xor   r17,r17,r20     /* invert test result value */
672 
        l.addi  r16,r16,-4      /* dec. cnt. */
673 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
674 
        l.sfeqi r16,0
675 
        l.bf    _D4s
676 
        l.add   r17,r17,r14     /* r17,r14..2nd opertion operands */
677 
        l.j     _D3
678 
        l.muli  r19,r19,2       /* r19..3rd operation operand */
679 
 
680 
 
681 
        /* ins. in dslot - loop 4: */
682 
        /* 1st operation operand before branch is used to set flag */
683 
        /* 1st and 2nd operation operands before and after branch are related */
684 
        /* 2nd and 3rd operation operands before and after jump are related */
685 
        /* 1st operation before branch is SINGLE cycle */
686 
        /* 2nd operation after branch/before jump is SINGLE cycle */
687 
        /* 3rd operation after jump is MULTI cycle */
688 
_D4s:
689 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
690 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
691 
_D4:
692 
        l.add   r17,r17,r14     /* merge test case operands */
693 
        l.add   r17,r17,r19     /* merge test case operands */
694 
        l.xor   r17,r17,r20     /* invert test result value */
695 
        l.addi  r16,r16,-4      /* dec. cnt. */
696 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
697 
        l.sfgeu r14,r15
698 
        l.bf    _D5s
699 
        l.add   r17,r17,r14     /* r17,r14..2nd opertion operands */
700 
        l.j     _D4
701 
        l.muli  r19,r17,1       /* r19,r17..3rd operation operand */
702 
 
703 
 
704 
        /* ins. in dslot - loop 5: */
705 
        /* 1st operation operand before branch is NOT used to set flag */
706 
        /* 1st and 2nd operation operands before and after branch are NOT related */
707 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
708 
        /* 1st operation before branch is SINGLE cycle */
709 
        /* 2nd operation after branch/before jump is MULTI cycle */
710 
        /* 3rd operation after jump is SINGLE cycle */
711 
_D5s:
712 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
713 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
714 
_D5:
715 
        l.add   r17,r17,r14     /* merge test case operands */
716 
        l.add   r17,r17,r19     /* merge test case operands */
717 
        l.xor   r17,r17,r20     /* invert test result value */
718 
        l.addi  r16,r16,-4      /* dec. cnt. */
719 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
720 
        l.sfeqi r16,0
721 
        l.bf    _D6s
722 
        l.mul   r17,r17,r18     /* r17,r18..2nd opertion operands */
723 
        l.j     _D5
724 
        l.addi  r19,r19,1       /* r19..3rd operation operand */
725 
 
726 
 
727 
        /* ins. in dslot - loop 6: */
728 
        /* 1st operation operand before branch is used to set flag */
729 
        /* 1st and 2nd operation operands before and after branch are NOT related */
730 
        /* 2nd and 3rd operation operands before and after jump are related */
731 
        /* 1st operation before branch is SINGLE cycle */
732 
        /* 2nd operation after branch/before jump is MULTI cycle */
733 
        /* 3rd operation after jump is SINGLE cycle */
734 
_D6s:
735 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
736 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
737 
_D6:
738 
        l.add   r17,r17,r14     /* merge test case operands */
739 
        l.add   r17,r17,r19     /* merge test case operands */
740 
        l.xor   r17,r17,r20     /* invert test result value */
741 
        l.addi  r16,r16,-4      /* dec. cnt. */
742 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
743 
        l.sfgeu r14,r15
744 
        l.bf    _D7s
745 
        l.mul   r17,r17,r18     /* r17,r18..2nd opertion operands */
746 
        l.j     _D6
747 
        l.addi  r19,r17,1       /* r19,r17..3rd operation operand */
748 
 
749 
 
750 
        /* ins. in dslot - loop 7: */
751 
        /* 1st operation operand before branch is NOT used to set flag */
752 
        /* 1st and 2nd operation operands before and after branch are related */
753 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
754 
        /* 1st operation before branch is SINGLE cycle */
755 
        /* 2nd operation after branch/before jump is MULTI cycle */
756 
        /* 3rd operation after jump is MULTI cycle */
757 
_D7s:
758 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
759 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
760 
_D7:
761 
        l.add   r17,r17,r14     /* merge test case operands */
762 
        l.add   r17,r17,r19     /* merge test case operands */
763 
        l.xor   r17,r17,r20     /* invert test result value */
764 
        l.addi  r16,r16,-4      /* dec. cnt. */
765 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
766 
        l.sfeqi r16,0
767 
        l.bf    _D8s
768 
        l.mul   r17,r17,r14     /* r17,r14..2nd opertion operands */
769 
        l.j     _D7
770 
        l.muli  r19,r19,2       /* r19..3rd operation operand */
771 
 
772 
 
773 
        /* ins. in dslot - loop 8: */
774 
        /* 1st operation operand before branch is used to set flag */
775 
        /* 1st and 2nd operation operands before and after branch are related */
776 
        /* 2nd and 3rd operation operands before and after jump are related */
777 
        /* 1st operation before branch is SINGLE cycle */
778 
        /* 2nd operation after branch/before jump is MULTI cycle */
779 
        /* 3rd operation after jump is MULTI cycle */
780 
_D8s:
781 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
782 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
783 
_D8:
784 
        l.add   r17,r17,r14     /* merge test case operands */
785 
        l.add   r17,r17,r19     /* merge test case operands */
786 
        l.xor   r17,r17,r20     /* invert test result value */
787 
        l.addi  r16,r16,-4      /* dec. cnt. */
788 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
789 
        l.sfgeu r14,r15
790 
        l.bf    _D9s
791 
        l.mul   r17,r17,r14     /* r17,r14..2nd opertion operands */
792 
        l.j     _D8
793 
        l.muli  r19,r17,1       /* r19,r17..3rd operation operand */
794 
 
795 
 
796 
        /* ins. in dslot - loop 9: */
797 
        /* 1st operation operand before branch is NOT used to set flag */
798 
        /* 1st and 2nd operation operands before and after branch are NOT related */
799 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
800 
        /* 1st operation before branch is MULTI cycle */
801 
        /* 2nd operation after branch/before jump is SINGLE cycle */
802 
        /* 3rd operation after jump is SINGLE cycle */
803 
_D9s:
804 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
805 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
806 
_D9:
807 
        l.add   r17,r17,r14     /* merge test case operands */
808 
        l.add   r17,r17,r19     /* merge test case operands */
809 
        l.xor   r17,r17,r20     /* invert test result value */
810 
        l.addi  r16,r16,-4      /* dec. cnt. */
811 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
812 
        l.sfeqi r16,0
813 
        l.bf    _D10s
814 
        l.add   r17,r17,r18     /* r17,r18..2nd opertion operands */
815 
        l.j     _D9
816 
        l.addi  r19,r19,1       /* r19..3rd operation operand */
817 
 
818 
 
819 
        /* ins. in dslot - loop 10: */
820 
        /* 1st operation operand before branch is used to set flag */
821 
        /* 1st and 2nd operation operands before and after branch are NOT related */
822 
        /* 2nd and 3rd operation operands before and after jump are related */
823 
        /* 1st operation before branch is MULTI cycle */
824 
        /* 2nd operation after branch/before jump is SINGLE cycle */
825 
        /* 3rd operation after jump is SINGLE cycle */
826 
_D10s:
827 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
828 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
829 
_D10:
830 
        l.add   r17,r17,r14     /* merge test case operands */
831 
        l.add   r17,r17,r19     /* merge test case operands */
832 
        l.xor   r17,r17,r20     /* invert test result value */
833 
        l.addi  r16,r16,-4      /* dec. cnt. */
834 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
835 
        l.sfgeu r14,r21
836 
        l.bf    _D11s
837 
        l.add   r17,r17,r18     /* r17,r18..2nd opertion operands */
838 
        l.j     _D10
839 
        l.addi  r19,r17,1       /* r19,r17..3rd operation operand */
840 
 
841 
 
842 
        /* ins. in dslot - loop 11: */
843 
        /* 1st operation operand before branch is NOT used to set flag */
844 
        /* 1st and 2nd operation operands before and after branch are related */
845 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
846 
        /* 1st operation before branch is MULTI cycle */
847 
        /* 2nd operation after branch/before jump is SINGLE cycle */
848 
        /* 3rd operation after jump is MULTI cycle */
849 
_D11s:
850 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
851 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
852 
_D11:
853 
        l.add   r17,r17,r14     /* merge test case operands */
854 
        l.add   r17,r17,r19     /* merge test case operands */
855 
        l.xor   r17,r17,r20     /* invert test result value */
856 
        l.addi  r16,r16,-4      /* dec. cnt. */
857 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
858 
        l.sfeqi r16,0
859 
        l.bf    _D12s
860 
        l.add   r17,r17,r14     /* r17,r14..2nd opertion operands */
861 
        l.j     _D11
862 
        l.muli  r19,r19,2       /* r19..3rd operation operand */
863 
 
864 
 
865 
        /* ins. in dslot - loop 12: */
866 
        /* 1st operation operand before branch is used to set flag */
867 
        /* 1st and 2nd operation operands before and after branch are related */
868 
        /* 2nd and 3rd operation operands before and after jump are related */
869 
        /* 1st operation before branch is MULTI cycle */
870 
        /* 2nd operation after branch/before jump is SINGLE cycle */
871 
        /* 3rd operation after jump is MULTI cycle */
872 
_D12s:
873 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
874 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
875 
_D12:
876 
        l.add   r17,r17,r14     /* merge test case operands */
877 
        l.add   r17,r17,r19     /* merge test case operands */
878 
        l.xor   r17,r17,r20     /* invert test result value */
879 
        l.addi  r16,r16,-4      /* dec. cnt. */
880 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
881 
        l.sfgeu r14,r21
882 
        l.bf    _D13s
883 
        l.add   r17,r17,r14     /* r17,r14..2nd opertion operands */
884 
        l.j     _D12
885 
        l.muli  r19,r17,1       /* r19,r17..3rd operation operand */
886 
 
887 
 
888 
        /* ins. in dslot - loop 13: */
889 
        /* 1st operation operand before branch is NOT used to set flag */
890 
        /* 1st and 2nd operation operands before and after branch are NOT related */
891 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
892 
        /* 1st operation before branch is MULTI cycle */
893 
        /* 2nd operation after branch/before jump is MULTI cycle */
894 
        /* 3rd operation after jump is SINGLE cycle */
895 
_D13s:
896 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
897 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
898 
_D13:
899 
        l.add   r17,r17,r14     /* merge test case operands */
900 
        l.add   r17,r17,r19     /* merge test case operands */
901 
        l.xor   r17,r17,r20     /* invert test result value */
902 
        l.addi  r16,r16,-4      /* dec. cnt. */
903 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
904 
        l.sfeqi r16,0
905 
        l.bf    _D14s
906 
        l.mul   r17,r17,r18     /* r17,r18..2nd opertion operands */
907 
        l.j     _D13
908 
        l.addi  r19,r19,1       /* r19..3rd operation operand */
909 
 
910 
 
911 
        /* ins. in dslot - loop 14: */
912 
        /* 1st operation operand before branch is used to set flag */
913 
        /* 1st and 2nd operation operands before and after branch are NOT related */
914 
        /* 2nd and 3rd operation operands before and after jump are related */
915 
        /* 1st operation before branch is MULTI cycle */
916 
        /* 2nd operation after branch/before jump is MULTI cycle */
917 
        /* 3rd operation after jump is SINGLE cycle */
918 
_D14s:
919 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
920 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
921 
_D14:
922 
        l.add   r17,r17,r14     /* merge test case operands */
923 
        l.add   r17,r17,r19     /* merge test case operands */
924 
        l.xor   r17,r17,r20     /* invert test result value */
925 
        l.addi  r16,r16,-4      /* dec. cnt. */
926 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
927 
        l.sfgeu r14,r21
928 
        l.bf    _D15s
929 
        l.mul   r17,r17,r18     /* r17,r18..2nd opertion operands */
930 
        l.j     _D14
931 
        l.addi  r19,r17,1       /* r19,r17..3rd operation operand */
932 
 
933 
 
934 
        /* ins. in dslot - loop 15: */
935 
        /* 1st operation operand before branch is NOT used to set flag */
936 
        /* 1st and 2nd operation operands before and after branch are related */
937 
        /* 2nd and 3rd operation operands before and after jump are NOT related */
938 
        /* 1st operation before branch is MULTI cycle */
939 
        /* 2nd operation after branch/before jump is MULTI cycle */
940 
        /* 3rd operation after jump is MULTI cycle */
941 
_D15s:
942 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
943 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
944 
_D15:
945 
        l.add   r17,r17,r14     /* merge test case operands */
946 
        l.add   r17,r17,r19     /* merge test case operands */
947 
        l.xor   r17,r17,r20     /* invert test result value */
948 
        l.addi  r16,r16,-4      /* dec. cnt. */
949 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
950 
        l.sfeqi r16,0
951 
        l.bf    _D16s
952 
        l.mul   r17,r17,r14     /* r17,r14..2nd opertion operands */
953 
        l.j     _D15
954 
        l.muli  r19,r19,2       /* r19..3rd operation operand */
955 
 
956 
 
957 
        /* ins. in dslot - loop 16: */
958 
        /* 1st operation operand before branch is used to set flag */
959 
        /* 1st and 2nd operation operands before and after branch are related */
960 
        /* 2nd and 3rd operation operands before and after jump are related */
961 
        /* 1st operation before branch is MULTI cycle */
962 
        /* 2nd operation after branch/before jump is MULTI cycle */
963 
        /* 3rd operation after jump is MULTI cycle */
964 
_D16s:
965 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
966 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
967 
_D16:
968 
        l.add   r17,r17,r14     /* merge test case operands */
969 
        l.add   r17,r17,r19     /* merge test case operands */
970 
        l.xor   r17,r17,r20     /* invert test result value */
971 
        l.addi  r16,r16,-4      /* dec. cnt. */
972 
        l.muli  r14,r14,2       /* mul. cnt. - r14..1st operation operand */
973 
        l.sfgeu r14,r21
974 
        l.bf    _D17s
975 
        l.mul   r17,r17,r14     /* r17,r14..2nd opertion operands */
976 
        l.j     _D16
977 
        l.muli  r19,r17,1       /* r19,r17..3rd operation operand */
978 
 
979 
 
980 
        /* ins. in dslot - loop 17: */
981 
        /* 1st operation operand before branch is used to set flag */
982 
        /* 1st and 2nd operation operands before and after branch are NOT related */
983 
        /* 1st operation before branch is SINGLE cycle */
984 
        /* 2nd operation after branch/before jump is SW */
985 
_D17s:
986 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
987 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
988 
_D17:
989 
        l.add   r17,r17,r14     /* merge test case operands */
990 
        l.xor   r17,r17,r20     /* invert test result value */
991 
        l.addi  r16,r16,-4      /* dec. cnt. */
992 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
993 
        l.sfgeu r14,r15
994 
        l.bnf   _D17
995 
        l.sw    0(r16),r17      /* r16,r17..2nd opertion operands */
996 
 
997 
 
998 
        /* ins. in dslot - loop 18: */
999 
        /* 1st operation operand before branch is used to set flag */
1000 
        /* 1st and 2nd operation operands before and after branch are NOT related */
1001 
        /* 1st operation before branch is SINGLE cycle */
1002 
        /* 2nd operation after branch/before jump is LWZ */
1003 
        l.addi  r14,r0,0x4      /* init inc. loop cnt. */
1004 
        l.addi  r16,r0,0x10     /* init dec. loop cnt. */
1005 
_D18:
1006 
        l.add   r17,r17,r22     /* merge test case operands */
1007 
        l.add   r17,r17,r14     /* merge test case operands */
1008 
        l.xor   r17,r17,r20     /* invert test result value */
1009 
        l.addi  r16,r16,-4      /* dec. cnt. */
1010 
        l.addi  r14,r14,4       /* inc. cnt. - r14..1st operation operand */
1011 
        l.sfgeu r14,r15
1012 
        l.bnf   _D18
1013 
        l.lwz   r22,0(r16)      /* r16,r22..2nd opertion operands */
1014 
 
1015 
 
1016 
        /* following are ins. in dslot in three different JUMPs: l.jal, l.jr, l.j */
1017 
        l.add   r17,r17,r22     /* merge test case operands */
1018 
        l.xor   r17,r17,r20     /* invert test result value */
1019 
        l.jal   _D19
1020 
        l.muli  r17,r17,2
1021 
        l.add   r17,r17,r18
1022 
        l.xor   r17,r17,r20     /* invert test result value */
1023 
        l.j     _D20
1024 
        l.sub   r18,r18,r17
1025 
 
1026 
_D19:
1027 
        l.addi  r17,r17,1
1028 
        l.xor   r17,r17,r20     /* invert test result value */
1029 
        l.jr    r9
1030 
        l.addi  r18,r18,8
1031 
 
1032 
_D20:
1033 
        l.mul   r17,r17,r18             /* r17 shold be 0xb093a787 */
1034 
        l.movhi r18,hi(0xb093a787)
1035 
        l.ori   r18,r18,lo(0xb093a787)
1036 
        l.sub   r17,r17,r18             /* r17 used further in code */
1037 
        l.nop
1038 
        l.nop
1039 
 
1040 
 
1041 
_jump:
1042 
        l.add   r8,r0,r17
1043 
 
1044 
        l.j     _T1
1045 
        l.addi  r8,r8,1
1046 
 
1047 
_T2:    l.or    r10,r0,r9
1048 
        l.jalr  r10
1049 
        l.addi  r8,r8,1
1050 
 
1051 
_T1:    l.jal   _T2
1052 
        l.addi  r8,r8,1
1053 
 
1054 
        l.sfeqi r0,0
1055 
        l.bf    _T3
1056 
        l.addi  r8,r8,1
1057 
 
1058 
_T3:    l.sfeqi r0,1
1059 
        l.bf    _T4
1060 
        l.addi  r8,r8,1
1061 
 
1062 
        l.addi  r8,r8,1
1063 
 
1064 
_T4:    l.sfeqi r0,0
1065 
        l.bnf    _T5
1066 
        l.addi  r8,r8,1
1067 
 
1068 
        l.addi  r8,r8,1
1069 
 
1070 
_T5:    l.sfeqi r0,1
1071 
        l.bnf    _T6
1072 
        l.addi  r8,r8,1
1073 
 
1074 
        l.addi  r8,r8,1
1075 
 
1076 
_T6:    l.movhi r3,hi(_T7)
1077 
        l.ori  r3,r3,lo(_T7)
1078 
        l.mtspr r0,r3,32
1079 
        l.mfspr r5,r0,17
1080 
        l.mtspr r0,r5,64
1081 
        l.rfe
1082 
        l.addi  r8,r8,1
1083 
 
1084 
        l.addi  r8,r8,1
1085 
 
1086 
_T7:    l.mtspr r0,r8,0x1234   /* Should be 0x00000000a */
1087 
 
1088 
        l.lwz   r9,0(r31)
1089 
        l.add   r8,r9,r8
1090 
        l.sw    0(r31),r8
1091 
 
1092 
        l.lwz   r9,0(r31)
1093 
        l.movhi r3,0xcc69
1094 
        l.ori   r3,r3,0xe5fb
1095 
        l.add   r3,r8,r3        /* Should be 0xdeaddead */
1096 
 
1097 
        l.movhi r4, 0x5ead
1098 425 julius 
        l.ori   r4, r4, 0xdea0
1099 
        l.sub   r3, r3, r4 /* Should now be 0x8000000d */
1100 
        l.nop   0x2
1101 
        l.ori   r3, r0, 0 /* Clear R3 */
1102 
        l.nop   0x1 /* Exit simulation */
1103 349 julius 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.