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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-dsxinsn.S] - Blame information for rev 858

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/*
        Test correct delay-slot exception bit (DSX) behavior on
        instruction-fetch related exceptions.
 
        The only case where DSX is set on instruction-fetch related
        exception is when instructions in delay slots occur in a new
        page which needs to be mapped.
 
        In this test we will trigger an instruction MMU miss for an
        instruction in a delay slot. To do this, we need to have a
        branch instruction as the very last instruction of a page,
        with the delay slot instruction being on a new unmapped page.
 
        Set r10 to hold whether we are expecting SR[DSX] to be set or
        not. Exceptions will advance the PC by 0x8 to step over both
        the jump/branch and instruction causing an exception.
 
        Julius Baxter 
 
*/
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2012 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#include "spr-defs.h"
#include "board.h"
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register */
        l.ori   r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Init the stack */
        .global stack
        l.movhi r1, hi(stack)
        l.ori   r1, r1, lo(stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori   r4, r4, lo(_start)
        l.jr    r4
        l.nop
 
/* ---[ 0x200: BUS error ]------------------------------------------------ */
        .org 0x200
        l.j     test_fail
        l.nop
 
/* ---[ 0x600: ALIGN error ]------------------------------------------------ */
        .org 0x600
        l.j     test_fail
        l.nop
 
/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */
        .org 0x700
        l.j     test_fail
        l.nop
 
/* ---[ 0x900: DTLB exception ]--------------------------------------------- */
        .org 0x900
        l.j     test_fail
        l.nop
 
/* ---[ 0xa00: itlb miss ]---------------------------------------------- */
        .org 0xa00
 
        /* First check if we're expecting a miss in a delay slot - check r10 */
        l.mfspr r3,r0,SPR_EEAR_BASE     /* Get EPC */
        l.nop   2                       /* Report PC for diagnostic purpose */
        /* Check SR[DSX] was as expected */
        l.mfspr r8,r0,SPR_SR            /* Get SR */
        l.andi  r8,r8,SPR_SR_DSX        /* Clear all bits except DSX */
        l.xor   r8,r8,r10               /* r8 will be >0 if error */
        l.sfne  r8,r0
        l.bf    test_fail
        l.nop
 
        /* Simple itlb miss handler - install 1-1 mappings on misses */
        l.mfspr r12,r0,SPR_EEAR_BASE /* Get the PC of the exception */
        l.srli  r13,r12,13 /* Get the page number, divide by 8K, store in r13 */
        /* Set up the match registers */
        l.movhi r14,hi(SPR_ITLBMR_VPN)
        l.ori   r14,r14,lo(SPR_ITLBMR_VPN)
        l.and   r14,r12,r14 /* Mask in the VPN */
        l.ori   r15,r14,SPR_ITLBMR_V /* Set this match as valid */
        /* Write it into the appropriate match register, way 0 only */
        l.mtspr r13,r15,SPR_ITLBMR_BASE(0)
        /* Set up the translate register - no restrictions */
        l.ori   r15,r14,ITLB_PR_NOLIMIT
        /* Write it into the appropriate translate register  */
        l.mtspr r13,r15,SPR_ITLBTR_BASE(0)
        /* MMU setup should now be complete, let's go back */
        l.rfe
 
/* ---[ 0xe00: TRAP error ]------------------------------------------------ */
        .org 0xe00
        l.j     test_fail
        l.nop
 
/* =================================================== [ text section ] === */
        .section  .text
 
/* =================================================== [ start ] === */
 
        .global _start
_start:
        /* First initialise the instruction MMU */
 
        l.mfspr r3,r0,SPR_IMMUCFGR
        l.andi  r4,r3,SPR_IMMUCFGR_NTS
        l.srli  r4,r4,SPR_IMMUCFGR_NTS_OFF
        l.ori   r6,r0,1
        l.sll   r3,r6,r4
 
        /* Setup the IMMU's TLBs - invalidate them */
        l.movhi r4, hi(SPR_ITLBMR_BASE(0))
        l.ori r4, r4, lo(SPR_ITLBMR_BASE(0))
 
        /* ITLB invalidate loop */
1:
        l.mtspr r4, r0, 0x0
        l.addi r4, r4, 0x1
        l.sfeq r3, r0
        l.bnf 1b
        l.addi r3, r3, -1
 
        /* Enable MMU - we should get a miss for this page */
        l.movhi r10,0 /* Clear r10 - not expecting to be in a delay slot
                        when this TLB miss occurs */
 
        .extern lo_immu_en
        /* Now enable the IMMU */
        l.movhi r4, hi(lo_immu_en)
        l.ori r4, r4, lo(lo_immu_en)
        l.jalr r4
        l.nop
 
        /* Copy the 2 instructions from the ljr9_function function to
        places which should cause TLB misses in the delay slot */
        l.movhi r6,hi(ljr9_function)
        l.ori   r6,r6,lo(ljr9_function)
 
        /* r13 should have the page number we're in from the TLB miss we caused
        when enabling the immu. Take that and add 16 to determine the page
        boundary we'll play with */
        l.addi  r4,r13,16
 
        /* Calculate the physical address for this page */
        l.slli  r8,r4,13
 
        /* Copy our function to the last 2 instructions of the page before */
        l.lwz   r1,0(r6)
        l.sw    -8(r8),r1
        l.lwz   r1,4(r6)
        l.sw    -4(r8),r1
 
        /* Call it - we should _not_ have DSX set on the itbl miss */
        l.movhi r10,0
        l.addi  r1,r8,-8
 
        /* Report value */
        l.or    r3,r1,r1
        l.nop   2
 
        l.jalr  r1
        l.nop
 
        /* Tests finish */
 
        /* Now do what we've done for the miss but put delay slot instruction
        in the new page */
 
        /* Calculate the physical address for this page */
        l.slli  r8,r4,13
 
        /* Copy our function to the last 2 instructions of the page before */
        l.lwz   r1,0(r6)
        l.sw    -4(r8),r1
        l.lwz   r1,4(r6)
        l.sw    0(r8),r1
 
        /* Clear insn cache for this area (need to if it's enabled so we
        don't get the cached instructions from the previous test) */
        l.mtspr r0,r8,SPR_ICBIR
        l.addi  r1,r8,-4
        l.mtspr r0,r1,SPR_ICBIR
 
        /* Jump to (r8-0x4) - we _should_ have DSX set on the itbl miss as
        the jump instruction will be on the last instruction of the previous
        page (already mapped in ITLB) and the delay slot will be the first
        instruction on the next page, which is unmapped at this stage and
        should cause an ITLB miss*/
        l.ori   r10,r0,SPR_SR_DSX
        l.addi  r1,r8,-4
 
        /* Report value */
        l.or    r3,r1,r1
        l.nop   2
 
        l.jalr  r1
        l.nop
 
 
        /* TODO - track and check the number of TLB misses we should
        have incurred */
 
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r3,r0,SPR_UPR
        l.andi  r4,r3,SPR_UPR_ICP
        l.sfeq  r4,r0
        l.bf    test_ok
        l.nop
 
        /* Now repeat the tests with caches enabled if they weren't */
        l.mfspr r1,r0,SPR_SR
        l.andi  r1,r1,SPR_SR_ICE
        l.sfeq  r0,r1  /* Set flag if caches not enabled */
        l.bf    restart_with_caches_enabled
        l.nop
 
test_ok:
        l.movhi r3,0x8000
        l.ori   r3,r3,0x000d
        l.nop   2
        l.or    r3,r0,r0
        l.nop   1
 
test_fail:
        l.movhi r3,0xbaaa
        l.ori   r3,r3,0xaaad
        l.nop   2
        l.ori   r3,r0,1
        l.nop   1
 
restart_with_caches_enabled:
 
        /* Disable IMMU before restart*/
        l.mfspr r3,r0,SPR_SR
        l.xori  r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.movhi r9,hi(.L1)
        l.ori   r9,r9,lo(.L1)
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
.L1:
        l.jal   _cache_init
        l.nop
 
        /* Actually we won't want dcache enabled as we'll be reading
        and writing instructions around the shop so will not want them
        being cached */
        l.mfspr r3,r0,SPR_SR
        l.xori  r3,r3,SPR_SR_DCE
        l.mtspr r0,r3,SPR_SR
 
        l.j     _start
        l.nop
 
        /* A simple function, which we will copy the instructions of
        to different parts of memory */
ljr9_function:
        l.jr    r9
        l.nop
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-dsxinsn.S] - Blame information for rev 858

Line No.	Rev	Author	Line
1	807	julius	`/*`
2			`Test correct delay-slot exception bit (DSX) behavior on`
3			`instruction-fetch related exceptions.`
4
5			`The only case where DSX is set on instruction-fetch related`
6			`exception is when instructions in delay slots occur in a new`
7			`page which needs to be mapped.`
8
9			`In this test we will trigger an instruction MMU miss for an`
10			`instruction in a delay slot. To do this, we need to have a`
11			`branch instruction as the very last instruction of a page,`
12			`with the delay slot instruction being on a new unmapped page.`
13
14			`Set r10 to hold whether we are expecting SR[DSX] to be set or`
15			`not. Exceptions will advance the PC by 0x8 to step over both`
16			`the jump/branch and instruction causing an exception.`
17
18			`Julius Baxter`
19
20			`*/`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2012 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47
48			`#include "spr-defs.h"`
49			`#include "board.h"`
50
51			`/* =================================================== [ exceptions ] === */`
52			`.section .vectors, "ax"`
53
54
55			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
56			`.org 0x100`
57			`l.movhi r0, 0`
58			`/* Clear status register */`
59			`l.ori r1, r0, SPR_SR_SM`
60			`l.mtspr r0, r1, SPR_SR`
61			`/* Clear timer */`
62			`l.mtspr r0, r0, SPR_TTMR`
63			`/* Init the stack */`
64			`.global stack`
65			`l.movhi r1, hi(stack)`
66			`l.ori r1, r1, lo(stack)`
67			`l.addi r2, r0, -3`
68			`l.and r1, r1, r2`
69			`/* Jump to program initialisation code */`
70			`.global _start`
71			`l.movhi r4, hi(_start)`
72			`l.ori r4, r4, lo(_start)`
73			`l.jr r4`
74			`l.nop`
75
76			`/* ---[ 0x200: BUS error ]------------------------------------------------ */`
77			`.org 0x200`
78			`l.j test_fail`
79			`l.nop`
80
81			`/* ---[ 0x600: ALIGN error ]------------------------------------------------ */`
82			`.org 0x600`
83			`l.j test_fail`
84			`l.nop`
85
86			`/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */`
87			`.org 0x700`
88			`l.j test_fail`
89			`l.nop`
90
91			`/* ---[ 0x900: DTLB exception ]--------------------------------------------- */`
92			`.org 0x900`
93			`l.j test_fail`
94			`l.nop`
95
96			`/* ---[ 0xa00: itlb miss ]---------------------------------------------- */`
97			`.org 0xa00`
98
99			`/* First check if we're expecting a miss in a delay slot - check r10 */`
100			`l.mfspr r3,r0,SPR_EEAR_BASE /* Get EPC */`
101			`l.nop 2 /* Report PC for diagnostic purpose */`
102			`/* Check SR[DSX] was as expected */`
103			`l.mfspr r8,r0,SPR_SR /* Get SR */`
104			`l.andi r8,r8,SPR_SR_DSX /* Clear all bits except DSX */`
105			`l.xor r8,r8,r10 /* r8 will be >0 if error */`
106			`l.sfne r8,r0`
107			`l.bf test_fail`
108			`l.nop`
109
110			`/* Simple itlb miss handler - install 1-1 mappings on misses */`
111			`l.mfspr r12,r0,SPR_EEAR_BASE /* Get the PC of the exception */`
112			`l.srli r13,r12,13 /* Get the page number, divide by 8K, store in r13 */`
113			`/* Set up the match registers */`
114			`l.movhi r14,hi(SPR_ITLBMR_VPN)`
115			`l.ori r14,r14,lo(SPR_ITLBMR_VPN)`
116			`l.and r14,r12,r14 /* Mask in the VPN */`
117			`l.ori r15,r14,SPR_ITLBMR_V /* Set this match as valid */`
118			`/* Write it into the appropriate match register, way 0 only */`
119			`l.mtspr r13,r15,SPR_ITLBMR_BASE(0)`
120			`/* Set up the translate register - no restrictions */`
121			`l.ori r15,r14,ITLB_PR_NOLIMIT`
122			`/* Write it into the appropriate translate register */`
123			`l.mtspr r13,r15,SPR_ITLBTR_BASE(0)`
124			`/* MMU setup should now be complete, let's go back */`
125			`l.rfe`
126
127			`/* ---[ 0xe00: TRAP error ]------------------------------------------------ */`
128			`.org 0xe00`
129			`l.j test_fail`
130			`l.nop`
131
132			`/* =================================================== [ text section ] === */`
133			`.section .text`
134
135			`/* =================================================== [ start ] === */`
136
137			`.global _start`
138			`_start:`
139			`/* First initialise the instruction MMU */`
140
141			`l.mfspr r3,r0,SPR_IMMUCFGR`
142			`l.andi r4,r3,SPR_IMMUCFGR_NTS`
143			`l.srli r4,r4,SPR_IMMUCFGR_NTS_OFF`
144			`l.ori r6,r0,1`
145			`l.sll r3,r6,r4`
146
147			`/* Setup the IMMU's TLBs - invalidate them */`
148			`l.movhi r4, hi(SPR_ITLBMR_BASE(0))`
149			`l.ori r4, r4, lo(SPR_ITLBMR_BASE(0))`
150
151			`/* ITLB invalidate loop */`
152			`1:`
153			`l.mtspr r4, r0, 0x0`
154			`l.addi r4, r4, 0x1`
155			`l.sfeq r3, r0`
156			`l.bnf 1b`
157			`l.addi r3, r3, -1`
158
159			`/* Enable MMU - we should get a miss for this page */`
160			`l.movhi r10,0 /* Clear r10 - not expecting to be in a delay slot`
161			`when this TLB miss occurs */`
162
163			`.extern lo_immu_en`
164			`/* Now enable the IMMU */`
165			`l.movhi r4, hi(lo_immu_en)`
166			`l.ori r4, r4, lo(lo_immu_en)`
167			`l.jalr r4`
168			`l.nop`
169
170			`/* Copy the 2 instructions from the ljr9_function function to`
171			`places which should cause TLB misses in the delay slot */`
172			`l.movhi r6,hi(ljr9_function)`
173			`l.ori r6,r6,lo(ljr9_function)`
174
175			`/* r13 should have the page number we're in from the TLB miss we caused`
176			`when enabling the immu. Take that and add 16 to determine the page`
177			`boundary we'll play with */`
178			`l.addi r4,r13,16`
179
180			`/* Calculate the physical address for this page */`
181			`l.slli r8,r4,13`
182
183			`/* Copy our function to the last 2 instructions of the page before */`
184			`l.lwz r1,0(r6)`
185			`l.sw -8(r8),r1`
186			`l.lwz r1,4(r6)`
187			`l.sw -4(r8),r1`
188
189			`/* Call it - we should _not_ have DSX set on the itbl miss */`
190			`l.movhi r10,0`
191			`l.addi r1,r8,-8`
192
193			`/* Report value */`
194			`l.or r3,r1,r1`
195			`l.nop 2`
196
197			`l.jalr r1`
198			`l.nop`
199
200			`/* Tests finish */`
201
202			`/* Now do what we've done for the miss but put delay slot instruction`
203			`in the new page */`
204
205			`/* Calculate the physical address for this page */`
206			`l.slli r8,r4,13`
207
208			`/* Copy our function to the last 2 instructions of the page before */`
209			`l.lwz r1,0(r6)`
210			`l.sw -4(r8),r1`
211			`l.lwz r1,4(r6)`
212			`l.sw 0(r8),r1`
213
214			`/* Clear insn cache for this area (need to if it's enabled so we`
215			`don't get the cached instructions from the previous test) */`
216			`l.mtspr r0,r8,SPR_ICBIR`
217			`l.addi r1,r8,-4`
218			`l.mtspr r0,r1,SPR_ICBIR`
219
220			`/* Jump to (r8-0x4) - we _should_ have DSX set on the itbl miss as`
221			`the jump instruction will be on the last instruction of the previous`
222			`page (already mapped in ITLB) and the delay slot will be the first`
223			`instruction on the next page, which is unmapped at this stage and`
224			`should cause an ITLB miss*/`
225			`l.ori r10,r0,SPR_SR_DSX`
226			`l.addi r1,r8,-4`
227
228			`/* Report value */`
229			`l.or r3,r1,r1`
230			`l.nop 2`
231
232			`l.jalr r1`
233			`l.nop`
234
235
236			`/* TODO - track and check the number of TLB misses we should`
237			`have incurred */`
238
239	858	stekern	`/* Check if IC present and skip enabling otherwise */`
240			`l.mfspr r3,r0,SPR_UPR`
241			`l.andi r4,r3,SPR_UPR_ICP`
242			`l.sfeq r4,r0`
243			`l.bf test_ok`
244			`l.nop`
245
246	807	julius	`/* Now repeat the tests with caches enabled if they weren't */`
247			`l.mfspr r1,r0,SPR_SR`
248			`l.andi r1,r1,SPR_SR_ICE`
249			`l.sfeq r0,r1 /* Set flag if caches not enabled */`
250			`l.bf restart_with_caches_enabled`
251			`l.nop`
252
253			`test_ok:`
254			`l.movhi r3,0x8000`
255			`l.ori r3,r3,0x000d`
256			`l.nop 2`
257			`l.or r3,r0,r0`
258			`l.nop 1`
259
260			`test_fail:`
261			`l.movhi r3,0xbaaa`
262			`l.ori r3,r3,0xaaad`
263			`l.nop 2`
264			`l.ori r3,r0,1`
265			`l.nop 1`
266
267			`restart_with_caches_enabled:`
268
269			`/* Disable IMMU before restart*/`
270			`l.mfspr r3,r0,SPR_SR`
271			`l.xori r3,r3,SPR_SR_IME`
272			`l.mtspr r0,r3,SPR_ESR_BASE`
273			`l.movhi r9,hi(.L1)`
274			`l.ori r9,r9,lo(.L1)`
275			`l.mtspr r0,r9,SPR_EPCR_BASE`
276			`l.rfe`
277			`.L1:`
278			`l.jal _cache_init`
279			`l.nop`
280
281			`/* Actually we won't want dcache enabled as we'll be reading`
282			`and writing instructions around the shop so will not want them`
283			`being cached */`
284			`l.mfspr r3,r0,SPR_SR`
285			`l.xori r3,r3,SPR_SR_DCE`
286			`l.mtspr r0,r3,SPR_SR`
287
288			`l.j _start`
289			`l.nop`
290
291			`/* A simple function, which we will copy the instructions of`
292			`to different parts of memory */`
293			`ljr9_function:`
294			`l.jr r9`
295			`l.nop`
296