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julius |
/*
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OR1200 Range exception test
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Very basic, testing, checking that the EPC value is correct
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for generated range exceptions.
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Julius Baxter
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*/
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2012 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "board.h"
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#include "or1200-defines.h"
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Init the stack */
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.global stack
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l.movhi r1, hi(stack)
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l.ori r1, r1, lo(stack)
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l.addi r2, r0, -3
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l.and r1, r1, r2
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// Clear r10 -used to remember if we've run the
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// test with cache eanbeld yet.
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l.movhi r10, 0
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/* Jump to program initialisation code */
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.global _start
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.nop
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/* ---[ 0x700: ILLEGAL INSN exception ]------------------------------------- */
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.org 0x700
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l.nop 0x1
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/* ---[ 0xB00: RANGE exception ]-------------------------------------------- */
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.org 0xb00
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l.mfspr r3,r0,SPR_EPCR_BASE
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l.nop 2
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// Check the PC
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l.ori r6,r0,0x7fff // Use this as a mask for the PC
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l.and r7,r6,r3 // just take the bottom 15 bits, should be enough
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// Test 1 should be at
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l.sfeqi r5,1
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l.bf test1
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l.nop
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l.sfeqi r5,2
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l.bf test2
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l.nop
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test1:
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l.sfnei r7,0xf08 // test 1 trigger insn PC
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l.bf fail
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l.nop
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// set the PC to step over the range exception
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l.addi r3,r3,4
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l.mtspr r0,r3,SPR_EPCR_BASE
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l.nop 2
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l.j return
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l.nop
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test2:
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l.sfnei r7,0xf10 // test 2 - in delay slot, so PC should be of
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// preceeding l.j insn
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l.bf fail
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l.nop
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// set the PC to step over the branch and range exception
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l.addi r3,r3,8
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l.mtspr r0,r3,SPR_EPCR_BASE
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l.j return
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l.nop
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return:
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// Clear the OV flag
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l.mfspr r3,r0,SPR_ESR_BASE
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l.xori r3,r3,SPR_SR_OV
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l.mtspr r0,r3,SPR_ESR_BASE
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l.rfe
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.org 0xf00
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ov_tests:
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// Cause some range exceptions at known PC
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// Trigger a range execption
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l.movhi r2,0x4000
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// Test 1
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l.ori r5,r0,1
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// Should have 0x40000000 + 0x40000000, at PC 0xf08
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l.add r4,r2,r2
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// Test 2 - delay slot
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l.ori r5,r0,2
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l.j a_place
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// Should have 0x40000000 + 0x40000000, at PC 0xf10 (insn before as
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// we're in delay slot)
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l.add r4,r2,r2
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a_place:
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l.nop
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// Check if we've run with cache yet - if so then
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// r10 will contain nonzero
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l.sfeq r10,r0
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l.bnf pass
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l.nop
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// Init caches and restart
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l.jal _cache_init
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l.nop
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l.j _start
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l.ori r10,r0,1
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pass:
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l.movhi r3,0
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l.nop 1
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/* =================================================== [ text section ] === */
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.section .text
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/* =================================================== [ start ] === */
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.global _start
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_start:
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// Set up SR to have range exception enabled
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l.mfspr r3, r0, SPR_SR
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l.nop 0x2
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l.ori r3,r3,SPR_SR_OVE
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l.nop 0x2
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l.mtspr r0,r3,SPR_SR
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// Now jump to the tests
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l.movhi r1,hi(ov_tests)
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l.ori r1,r1,lo(ov_tests)
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l.jr r1
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l.nop
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fail:
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l.nop 2
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l.ori r3,r0,1
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l.nop 1
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