URL https://opencores.org/ocsvn/opentech/opentech/trunk

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[/] [opentech/] [web_uploads/] [changes_1_6_0.txt] - Blame information for rev 6

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Changes from version 1.5.1
 
OpenCores.org
======
Site and CVS are Updated
 
DESIGNS
======
- Free Model Foundation models (updated)
- Gadgetboard (added)
- Logic Analyzer (updated)
- OpenEEG (added)
- OpenHardware.ru projects (addded)
- Gadgetboard (updated)
 
 
TOOLS:
=====
In Design Entry
- gEDA (updated)
- TinyCad (updated)
- xcircuit (updated)
- veditor_Eclipse (updated)
- jhdl-ide (added)
- vhdl-emacs-mode (updated)
- KICAD (updated)
 
In pcb
- FreePCB (updated)
- pcb (added)
 
 
In PLDs
- fpgaC (added)
 
 
In uC
- ketchlab (updated)
- piklab (added)
 
 
In  Analysis
- wcalc (added)
- gsmc+xsmc (added)
 
 
In Spice
- ASCO (added)
- gSpiceUI (updated)
- gwave (updated)
 
In simulation
- Qucs (updated)
- FlowDesign (added)
- gtkwave (updated)
 
 
In Synthesis
- balsa (added)
 
In IC layout/vlsi
- electric (updated)
- magic (updated)
- LayoutEditor (added)
- IRSIM (updated)
- netgen (updated)
 
In Verification
- confluence (updated)
- hdcaml (added)
- jove (added)
 
In instruments
 
In Others
 
 
In Verilog
- Covered (updated)
- Ircus (updated)
- verilator (updated)
- veriwell (added)
 
 
In VHDL
- signs (updated)
 
 
in ROMs
 
In Modeling
- GreeSOCs (added)
- sc2ast (added)
 
 
In Extras
- Xemacs (updated)
- nedit (updated)
- wincvs (updated)

Line No.	Rev	Author	Line
1	6	root	`Changes from version 1.5.1`
2
3			`OpenCores.org`
4			`======`
5			`Site and CVS are Updated`
6
7			`DESIGNS`
8			`======`
9			`- Free Model Foundation models (updated)`
10			`- Gadgetboard (added)`
11			`- Logic Analyzer (updated)`
12			`- OpenEEG (added)`
13			`- OpenHardware.ru projects (addded)`
14			`- Gadgetboard (updated)`
15
16
17			`TOOLS:`
18			`=====`
19			`In Design Entry`
20			`- gEDA (updated)`
21			`- TinyCad (updated)`
22			`- xcircuit (updated)`
23			`- veditor_Eclipse (updated)`
24			`- jhdl-ide (added)`
25			`- vhdl-emacs-mode (updated)`
26			`- KICAD (updated)`
27
28			`In pcb`
29			`- FreePCB (updated)`
30			`- pcb (added)`
31
32
33			`In PLDs`
34			`- fpgaC (added)`
35
36
37			`In uC`
38			`- ketchlab (updated)`
39			`- piklab (added)`
40
41
42			`In Analysis`
43			`- wcalc (added)`
44			`- gsmc+xsmc (added)`
45
46
47			`In Spice`
48			`- ASCO (added)`
49			`- gSpiceUI (updated)`
50			`- gwave (updated)`
51
52			`In simulation`
53			`- Qucs (updated)`
54			`- FlowDesign (added)`
55			`- gtkwave (updated)`
56
57
58			`In Synthesis`
59			`- balsa (added)`
60
61			`In IC layout/vlsi`
62			`- electric (updated)`
63			`- magic (updated)`
64			`- LayoutEditor (added)`
65			`- IRSIM (updated)`
66			`- netgen (updated)`
67
68			`In Verification`
69			`- confluence (updated)`
70			`- hdcaml (added)`
71			`- jove (added)`
72
73			`In instruments`
74
75			`In Others`
76
77
78			`In Verilog`
79			`- Covered (updated)`
80			`- Ircus (updated)`
81			`- verilator (updated)`
82			`- veriwell (added)`
83
84
85			`In VHDL`
86			`- signs (updated)`
87
88
89			`in ROMs`
90
91			`In Modeling`
92			`- GreeSOCs (added)`
93			`- sc2ast (added)`
94
95
96			`In Extras`
97			`- Xemacs (updated)`
98			`- nedit (updated)`
99			`- wincvs (updated)`

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Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_6_0.txt] - Blame information for rev 6