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[/] [or1200_soc/] [trunk/] [boards/] [de1_board/] [sim/] [models/] [S29al032d_00/] [model/] [s29al032d_00.v] - Blame information for rev 22

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1 22 qaztronic
//////////////////////////////////////////////////////////////////////////////
2
//  File name : s29al032d_00.v
3
//////////////////////////////////////////////////////////////////////////////
4
//  Copyright (C) 2005 Spansion, LLC.
5
//
6
// MODIFICATION HISTORY :
7
//
8
//
9
//  version:   | author:        | mod date: | changes made:
10
//    V1.0       D.Lukovic       05 May 17    Initial release
11
//   
12
//////////////////////////////////////////////////////////////////////////////
13
//
14
//  PART DESCRIPTION:
15
//
16
//  Library:        FLASH
17
//  Technology:     Flash memory
18
//  Part:           s29al032d_00
19
//
20
//  Description:    32Mbit (4M x 8-Bit)  Flash Memory
21
//
22
//
23
//
24
///////////////////////////////////////////////////////////////////////////////
25
//  Known Bugs:
26
//
27
///////////////////////////////////////////////////////////////////////////////
28
`timescale 1 ns/1 ns
29
 
30
module s29al032d_00
31
(
32
    A21      ,
33
    A20      ,
34
    A19      ,
35
    A18      ,
36
    A17      ,
37
    A16      ,
38
    A15      ,
39
    A14      ,
40
    A13      ,
41
    A12      ,
42
    A11      ,
43
    A10      ,
44
    A9       ,
45
    A8       ,
46
    A7       ,
47
    A6       ,
48
    A5       ,
49
    A4       ,
50
    A3       ,
51
    A2       ,
52
    A1       ,
53
    A0       ,
54
 
55
    DQ7      ,
56
    DQ6      ,
57
    DQ5      ,
58
    DQ4      ,
59
    DQ3      ,
60
    DQ2      ,
61
    DQ1      ,
62
    DQ0      ,
63
 
64
    CENeg    ,
65
    OENeg    ,
66
    WENeg    ,
67
    RESETNeg ,
68
    ACC      ,
69
    RY
70
 
71
);
72
 
73
////////////////////////////////////////////////////////////////////////
74
// Port / Part Pin Declarations
75
////////////////////////////////////////////////////////////////////////
76
 
77
    input  A21  ;
78
    input  A20  ;
79
    input  A19  ;
80
    input  A18  ;
81
    input  A17  ;
82
    input  A16  ;
83
    input  A15  ;
84
    input  A14  ;
85
    input  A13  ;
86
    input  A12  ;
87
    input  A11  ;
88
    input  A10  ;
89
    input  A9   ;
90
    input  A8   ;
91
    input  A7   ;
92
    input  A6   ;
93
    input  A5   ;
94
    input  A4   ;
95
    input  A3   ;
96
    input  A2   ;
97
    input  A1   ;
98
    input  A0   ;
99
 
100
    inout  DQ7   ;
101
    inout  DQ6   ;
102
    inout  DQ5   ;
103
    inout  DQ4   ;
104
    inout  DQ3   ;
105
    inout  DQ2   ;
106
    inout  DQ1   ;
107
    inout  DQ0   ;
108
 
109
    input  CENeg    ;
110
    input  OENeg    ;
111
    input  WENeg    ;
112
    input  RESETNeg ;
113
    input  ACC      ;
114
    output RY       ;
115
 
116
// interconnect path delay signals
117
 
118
    wire  A21_ipd  ;
119
    wire  A20_ipd  ;
120
    wire  A19_ipd  ;
121
    wire  A18_ipd  ;
122
    wire  A17_ipd  ;
123
    wire  A16_ipd  ;
124
    wire  A15_ipd  ;
125
    wire  A14_ipd  ;
126
    wire  A13_ipd  ;
127
    wire  A12_ipd  ;
128
    wire  A11_ipd  ;
129
    wire  A10_ipd  ;
130
    wire  A9_ipd   ;
131
    wire  A8_ipd   ;
132
    wire  A7_ipd   ;
133
    wire  A6_ipd   ;
134
    wire  A5_ipd   ;
135
    wire  A4_ipd   ;
136
    wire  A3_ipd   ;
137
    wire  A2_ipd   ;
138
    wire  A1_ipd   ;
139
    wire  A0_ipd   ;
140
 
141
    wire [21 : 0] A;
142
    assign A = {
143
                A21_ipd,
144
                A20_ipd,
145
                A19_ipd,
146
                A18_ipd,
147
                A17_ipd,
148
                A16_ipd,
149
                A15_ipd,
150
                A14_ipd,
151
                A13_ipd,
152
                A12_ipd,
153
                A11_ipd,
154
                A10_ipd,
155
                A9_ipd,
156
                A8_ipd,
157
                A7_ipd,
158
                A6_ipd,
159
                A5_ipd,
160
                A4_ipd,
161
                A3_ipd,
162
                A2_ipd,
163
                A1_ipd,
164
                A0_ipd };
165
 
166
    wire  DQ7_ipd   ;
167
    wire  DQ6_ipd   ;
168
    wire  DQ5_ipd   ;
169
    wire  DQ4_ipd   ;
170
    wire  DQ3_ipd   ;
171
    wire  DQ2_ipd   ;
172
    wire  DQ1_ipd   ;
173
    wire  DQ0_ipd   ;
174
 
175
    wire [7 : 0 ] DIn;
176
    assign DIn = {DQ7_ipd,
177
                  DQ6_ipd,
178
                  DQ5_ipd,
179
                  DQ4_ipd,
180
                  DQ3_ipd,
181
                  DQ2_ipd,
182
                  DQ1_ipd,
183
                  DQ0_ipd };
184
 
185
    wire [7 : 0 ] DOut;
186
    assign DOut = {DQ7,
187
                  DQ6,
188
                  DQ5,
189
                  DQ4,
190
                  DQ3,
191
                  DQ2,
192
                  DQ1,
193
                  DQ0 };
194
 
195
    wire  CENeg_ipd    ;
196
    wire  OENeg_ipd    ;
197
    wire  WENeg_ipd    ;
198
    wire  RESETNeg_ipd ;
199
    wire  ACC_ipd      ;
200
    wire  VIO_ipd      ;
201
 
202
//  internal delays
203
 
204
    reg HANG_out    ; // Program/Erase Timing Limit
205
    reg HANG_in     ;
206
    reg START_T1    ; // Start TimeOut
207
    reg START_T1_in ;
208
    reg CTMOUT      ; // Sector Erase TimeOut
209
    reg CTMOUT_in   ;
210
    reg READY_in    ;
211
    reg READY       ; // Device ready after reset
212
 
213
    reg [7 : 0] DOut_zd;
214
    wire  DQ7_Pass   ;
215
    wire  DQ6_Pass   ;
216
    wire  DQ5_Pass   ;
217
    wire  DQ4_Pass   ;
218
    wire  DQ3_Pass   ;
219
    wire  DQ2_Pass   ;
220
    wire  DQ1_Pass   ;
221
    wire  DQ0_Pass   ;
222
 
223
    reg [7 : 0] DOut_Pass;
224
    assign {DQ7_Pass,
225
            DQ6_Pass,
226
            DQ5_Pass,
227
            DQ4_Pass,
228
            DQ3_Pass,
229
            DQ2_Pass,
230
            DQ1_Pass,
231
            DQ0_Pass  } = DOut_Pass;
232
 
233
    reg RY_zd;
234
 
235
    parameter UserPreload     = 1'b0;
236
    parameter mem_file_name   = "none";
237
    parameter prot_file_name  = "none";
238
    parameter secsi_file_name = "none";
239
 
240
    parameter TimingModel = "DefaultTimingModel";
241
 
242
    parameter DelayValues = "FROM_PLI";
243
    parameter PartID    = "s29al032d";
244
    parameter MaxData   = 255;
245
    parameter SecSize   = 65535;
246
    parameter SecNum    = 63;
247
    parameter HiAddrBit = 21;
248
    parameter SecSiSize = 255;
249
 
250
    // powerup
251
    reg PoweredUp;
252
 
253
    //FSM control signals
254
    reg ULBYPASS ; ////Unlock Bypass Active
255
    reg ESP_ACT  ; ////Erase Suspend
256
    reg OTP_ACT  ; ////SecSi Access
257
 
258
    reg PDONE    ; ////Prog. Done
259
    reg PSTART   ; ////Start Programming
260
    //Program location is in protected sector
261
    reg PERR     ;
262
 
263
    reg EDONE    ; ////Ers. Done
264
    reg ESTART   ; ////Start Erase
265
    reg ESUSP    ; ////Suspend Erase
266
    reg ERES     ; ////Resume Erase
267
    //All sectors selected for erasure are protected
268
    reg EERR     ;
269
 
270
    //Sectors selected for erasure
271
    reg [SecNum:0] Ers_queue; // = SecNum'b0;
272
 
273
    //Command Register
274
    reg write ;
275
    reg read  ;
276
 
277
    //Sector Address
278
    integer SecAddr = 0;
279
 
280
    integer SA      = 0;
281
 
282
    //Address within sector
283
    integer Address = 0;
284
    integer MemAddress = 0;
285
    integer SecSiAddr = 0;
286
 
287
    integer AS_ID = 0;
288
    integer AS_SecSi_FP = 0;
289
    integer AS_ID2 = 0;
290
    //A19:A11 Don't Care
291
    integer Addr ;
292
 
293
    //glitch protection
294
    wire gWE_n ;
295
    wire gCE_n ;
296
    wire gOE_n ;
297
 
298
    reg RST ;
299
    reg reseted ;
300
 
301
    integer Mem[0:(SecNum+1)*(SecSize+1)-1];
302
    //Sector Protection Status
303
    reg [SecNum:0] Sec_Prot;
304
 
305
    // timing check violation
306
    reg Viol = 1'b0;
307
    // CFI query address
308
    integer SecSi[0:SecSiSize];
309
    integer CFI_array[16:79];
310
 
311
    reg FactoryProt = 0;
312
 
313
    integer WBData;
314
    integer WBAddr;
315
 
316
    reg oe = 1'b0;
317
    event oe_event;
318
 
319
    event initOK;
320
    event MergeE;
321
 
322
    //Status reg.
323
    reg[15:0] Status = 8'b0;
324
 
325
    reg[7:0]  old_bit, new_bit;
326
    integer old_int, new_int;
327
    integer wr_cnt;
328
    reg[7:0] temp;
329
 
330
    integer S_ind = 0;
331
    integer ind   = 0;
332
 
333
    integer i,j,k;
334
 
335
    integer Debug;
336
 
337
    //TPD_XX_DATA
338
    time OEDQ_t;
339
    time CEDQ_t;
340
    time ADDRDQ_t;
341
    time OENeg_event;
342
    time CENeg_event;
343
    time OENeg_posEvent;
344
    time CENeg_posEvent;
345
    time ADDR_event;
346
    reg FROMOE;
347
    reg FROMCE;
348
    reg FROMADDR;
349
    integer   OEDQ_01;
350
    integer   CEDQ_01;
351
    integer   ADDRDQ_01;
352
 
353
    reg[7:0] TempData;
354
 
355
///////////////////////////////////////////////////////////////////////////////
356
//Interconnect Path Delay Section
357
///////////////////////////////////////////////////////////////////////////////
358
    buf   (A21_ipd, A21);
359
    buf   (A20_ipd, A20);
360
    buf   (A19_ipd, A19);
361
    buf   (A18_ipd, A18);
362
    buf   (A17_ipd, A17);
363
    buf   (A16_ipd, A16);
364
    buf   (A15_ipd, A15);
365
    buf   (A14_ipd, A14);
366
    buf   (A13_ipd, A13);
367
    buf   (A12_ipd, A12);
368
    buf   (A11_ipd, A11);
369
    buf   (A10_ipd, A10);
370
    buf   (A9_ipd , A9 );
371
    buf   (A8_ipd , A8 );
372
    buf   (A7_ipd , A7 );
373
    buf   (A6_ipd , A6 );
374
    buf   (A5_ipd , A5 );
375
    buf   (A4_ipd , A4 );
376
    buf   (A3_ipd , A3 );
377
    buf   (A2_ipd , A2 );
378
    buf   (A1_ipd , A1 );
379
    buf   (A0_ipd , A0 );
380
 
381
    buf   (DQ7_ipd , DQ7 );
382
    buf   (DQ6_ipd , DQ6 );
383
    buf   (DQ5_ipd , DQ5 );
384
    buf   (DQ4_ipd , DQ4 );
385
    buf   (DQ3_ipd , DQ3 );
386
    buf   (DQ2_ipd , DQ2 );
387
    buf   (DQ1_ipd , DQ1 );
388
    buf   (DQ0_ipd , DQ0 );
389
 
390
    buf   (CENeg_ipd    , CENeg    );
391
    buf   (OENeg_ipd    , OENeg    );
392
    buf   (WENeg_ipd    , WENeg    );
393
    buf   (RESETNeg_ipd , RESETNeg );
394
    buf   (ACC_ipd      , ACC      );
395
///////////////////////////////////////////////////////////////////////////////
396
// Propagation  delay Section
397
///////////////////////////////////////////////////////////////////////////////
398
    nmos   (DQ7 ,   DQ7_Pass  , 1);
399
    nmos   (DQ6 ,   DQ6_Pass  , 1);
400
    nmos   (DQ5 ,   DQ5_Pass  , 1);
401
    nmos   (DQ4 ,   DQ4_Pass  , 1);
402
    nmos   (DQ3 ,   DQ3_Pass  , 1);
403
    nmos   (DQ2 ,   DQ2_Pass  , 1);
404
    nmos   (DQ1 ,   DQ1_Pass  , 1);
405
    nmos   (DQ0 ,   DQ0_Pass  , 1);
406
    nmos   (RY  ,   1'b0      , ~RY_zd);
407
 
408
    wire deg;
409
 
410
    //VHDL VITAL CheckEnable equivalents
411
    // Address setup/hold near WE# falling edge
412
    wire   CheckEnable_A0_WE;
413
    assign CheckEnable_A0_WE  = ~CENeg && OENeg;
414
    // Data setup/hold near WE# rising edge
415
    wire   CheckEnable_DQ0_WE;
416
    assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
417
    // Address setup/hold near CE# falling edge
418
    wire   CheckEnable_A0_CE;
419
    assign CheckEnable_A0_CE  = ~WENeg && OENeg;
420
    // Data setup/hold near CE# rising edge
421
    wire   CheckEnable_DQ0_CE;
422
    assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
423
 
424
specify
425
 
426
    // tipd delays: interconnect path delays , mapped to input port delays.
427
    // In Verilog is not necessary to declare any tipd_ delay variables,
428
    // they can be taken from SDF file
429
    // With all the other delays real delays would be taken from SDF file
430
 
431
    // tpd delays
432
    specparam           tpd_RESETNeg_DQ0        =1;
433
    specparam           tpd_A0_DQ0              =1;//tacc ok
434
    specparam           tpd_CENeg_DQ0           =1;//ok
435
                      //(tCE,tCE,tDF,-,tDF,-)
436
    specparam           tpd_OENeg_DQ0           =1;//ok
437
                      //(tOE,tOE,tDF,-,tDF,-)
438
    specparam           tpd_WENeg_RY            =1;    //tBUSY
439
    specparam           tpd_CENeg_RY            =1;    //tBUSY
440
 
441
    // tsetup values: setup time
442
    specparam           tsetup_A0_WENeg         =1;   //tAS edge \
443
    specparam           tsetup_DQ0_WENeg        =1;   //tDS edge /
444
 
445
    // thold values: hold times
446
    specparam           thold_A0_WENeg          =1; //tAH  edge \
447
    specparam           thold_DQ0_CENeg         =1; //tDH edge /
448
    specparam           thold_OENeg_WENeg       =1; //tOEH edge /
449
    specparam           thold_CENeg_RESETNeg    =1; //tRH  edge /
450
    specparam           thold_WENeg_OENeg       =1; //tGHVL edge /
451
 
452
    // tpw values: pulse width
453
    specparam           tpw_RESETNeg_negedge    =1; //tRP
454
    specparam           tpw_WENeg_negedge       =1; //tWP
455
    specparam           tpw_WENeg_posedge       =1; //tWPH
456
    specparam           tpw_CENeg_negedge       =1; //tCP
457
    specparam           tpw_CENeg_posedge       =1; //tCEPH
458
    specparam           tpw_A0_negedge          =1; //tWC tRC ok
459
    specparam           tpw_A0_posedge          =1; //tWC tRC ok 
460
 
461
    // tdevice values: values for internal delays
462
            //Program Operation
463
    specparam   tdevice_POB                     = 9000; //9 us;
464
           //Sector Erase Operation
465
    specparam   tdevice_SEO                     = 700000000; //700 ms;
466
           //Timing Limit Exceeded
467
    specparam   tdevice_HANG                    = 400000000; //400 ms;
468
           //Erase suspend time
469
    specparam   tdevice_START_T1                = 20000; //20 us;
470
           //sector erase command sequence timeout
471
    specparam   tdevice_CTMOUT                  = 50000; //50 us;
472
           //device ready after Hardware reset(during embeded algorithm)
473
    specparam   tdevice_READY                   = 20000; //20 us; //tReady
474
 
475
    // If tpd values are fetched from specify block, these parameters
476
    // must change along with SDF values, SDF values change will NOT
477
    // imlicitly apply here !
478
    // If you want tpd values to be fetched by the model itself, please
479
    // use the PLI routine approach but be shure to set parameter
480
    // DelayValues to "FROM_PLI" as default
481
 
482
///////////////////////////////////////////////////////////////////////////////
483
// Input Port  Delays  don't require Verilog description
484
///////////////////////////////////////////////////////////////////////////////
485
// Path delays                                                               //
486
///////////////////////////////////////////////////////////////////////////////
487
//for DQ signals
488
    if (FROMCE)
489
        ( CENeg => DQ0 ) = tpd_CENeg_DQ0;
490
    if (FROMCE)
491
        ( CENeg => DQ1 ) = tpd_CENeg_DQ0;
492
    if (FROMCE)
493
        ( CENeg => DQ2 ) = tpd_CENeg_DQ0;
494
    if (FROMCE)
495
        ( CENeg => DQ3 ) = tpd_CENeg_DQ0;
496
    if (FROMCE)
497
        ( CENeg => DQ4 ) = tpd_CENeg_DQ0;
498
    if (FROMCE)
499
        ( CENeg => DQ5 ) = tpd_CENeg_DQ0;
500
    if (FROMCE)
501
        ( CENeg => DQ6 ) = tpd_CENeg_DQ0;
502
    if (FROMCE)
503
        ( CENeg => DQ7 ) = tpd_CENeg_DQ0;
504
 
505
    if (FROMOE)
506
        ( OENeg => DQ0 ) = tpd_OENeg_DQ0;
507
    if (FROMOE)
508
        ( OENeg => DQ1 ) = tpd_OENeg_DQ0;
509
    if (FROMOE)
510
        ( OENeg => DQ2 ) = tpd_OENeg_DQ0;
511
    if (FROMOE)
512
        ( OENeg => DQ3 ) = tpd_OENeg_DQ0;
513
    if (FROMOE)
514
        ( OENeg => DQ4 ) = tpd_OENeg_DQ0;
515
    if (FROMOE)
516
        ( OENeg => DQ5 ) = tpd_OENeg_DQ0;
517
    if (FROMOE)
518
        ( OENeg => DQ6 ) = tpd_OENeg_DQ0;
519
    if (FROMOE)
520
        ( OENeg => DQ7 ) = tpd_OENeg_DQ0;
521
 
522
    if (FROMADDR)
523
        ( A0 => DQ0 ) = tpd_A0_DQ0;
524
    if (FROMADDR)
525
        ( A0 => DQ1 ) = tpd_A0_DQ0;
526
    if (FROMADDR)
527
        ( A0 => DQ2 ) = tpd_A0_DQ0;
528
    if (FROMADDR)
529
        ( A0 => DQ3 ) = tpd_A0_DQ0;
530
    if (FROMADDR)
531
        ( A0 => DQ4 ) = tpd_A0_DQ0;
532
    if (FROMADDR)
533
        ( A0 => DQ5 ) = tpd_A0_DQ0;
534
    if (FROMADDR)
535
        ( A0 => DQ6 ) = tpd_A0_DQ0;
536
    if (FROMADDR)
537
        ( A0 => DQ7 ) = tpd_A0_DQ0;
538
    if (FROMADDR)
539
        ( A1 => DQ0 ) = tpd_A0_DQ0;
540
    if (FROMADDR)
541
        ( A1 => DQ1 ) = tpd_A0_DQ0;
542
    if (FROMADDR)
543
        ( A1 => DQ2 ) = tpd_A0_DQ0;
544
    if (FROMADDR)
545
        ( A1 => DQ3 ) = tpd_A0_DQ0;
546
    if (FROMADDR)
547
        ( A1 => DQ4 ) = tpd_A0_DQ0;
548
    if (FROMADDR)
549
        ( A1 => DQ5 ) = tpd_A0_DQ0;
550
    if (FROMADDR)
551
        ( A1 => DQ6 ) = tpd_A0_DQ0;
552
    if (FROMADDR)
553
        ( A1 => DQ7 ) = tpd_A0_DQ0;
554
    if (FROMADDR)
555
        ( A2 => DQ0 ) = tpd_A0_DQ0;
556
    if (FROMADDR)
557
        ( A2 => DQ1 ) = tpd_A0_DQ0;
558
    if (FROMADDR)
559
        ( A2 => DQ2 ) = tpd_A0_DQ0;
560
    if (FROMADDR)
561
        ( A2 => DQ3 ) = tpd_A0_DQ0;
562
    if (FROMADDR)
563
        ( A2 => DQ4 ) = tpd_A0_DQ0;
564
    if (FROMADDR)
565
        ( A2 => DQ5 ) = tpd_A0_DQ0;
566
    if (FROMADDR)
567
        ( A2 => DQ6 ) = tpd_A0_DQ0;
568
    if (FROMADDR)
569
        ( A2 => DQ7 ) = tpd_A0_DQ0;
570
    if (FROMADDR)
571
        ( A3 => DQ0 ) = tpd_A0_DQ0;
572
    if (FROMADDR)
573
        ( A3 => DQ1 ) = tpd_A0_DQ0;
574
    if (FROMADDR)
575
        ( A3 => DQ2 ) = tpd_A0_DQ0;
576
    if (FROMADDR)
577
        ( A3 => DQ3 ) = tpd_A0_DQ0;
578
    if (FROMADDR)
579
        ( A3 => DQ4 ) = tpd_A0_DQ0;
580
    if (FROMADDR)
581
        ( A3 => DQ5 ) = tpd_A0_DQ0;
582
    if (FROMADDR)
583
        ( A3 => DQ6 ) = tpd_A0_DQ0;
584
    if (FROMADDR)
585
        ( A3 => DQ7 ) = tpd_A0_DQ0;
586
    if (FROMADDR)
587
        ( A4 => DQ0 ) = tpd_A0_DQ0;
588
    if (FROMADDR)
589
        ( A4 => DQ1 ) = tpd_A0_DQ0;
590
    if (FROMADDR)
591
        ( A4 => DQ2 ) = tpd_A0_DQ0;
592
    if (FROMADDR)
593
        ( A4 => DQ3 ) = tpd_A0_DQ0;
594
    if (FROMADDR)
595
        ( A4 => DQ4 ) = tpd_A0_DQ0;
596
    if (FROMADDR)
597
        ( A4 => DQ5 ) = tpd_A0_DQ0;
598
    if (FROMADDR)
599
        ( A4 => DQ6 ) = tpd_A0_DQ0;
600
    if (FROMADDR)
601
        ( A4 => DQ7 ) = tpd_A0_DQ0;
602
    if (FROMADDR)
603
        ( A5 => DQ0 ) = tpd_A0_DQ0;
604
    if (FROMADDR)
605
        ( A5 => DQ1 ) = tpd_A0_DQ0;
606
    if (FROMADDR)
607
        ( A5 => DQ2 ) = tpd_A0_DQ0;
608
    if (FROMADDR)
609
        ( A5 => DQ3 ) = tpd_A0_DQ0;
610
    if (FROMADDR)
611
        ( A5 => DQ4 ) = tpd_A0_DQ0;
612
    if (FROMADDR)
613
        ( A5 => DQ5 ) = tpd_A0_DQ0;
614
    if (FROMADDR)
615
        ( A5 => DQ6 ) = tpd_A0_DQ0;
616
    if (FROMADDR)
617
        ( A5 => DQ7 ) = tpd_A0_DQ0;
618
    if (FROMADDR)
619
        ( A6 => DQ0 ) = tpd_A0_DQ0;
620
    if (FROMADDR)
621
        ( A6 => DQ1 ) = tpd_A0_DQ0;
622
    if (FROMADDR)
623
        ( A6 => DQ2 ) = tpd_A0_DQ0;
624
    if (FROMADDR)
625
        ( A6 => DQ3 ) = tpd_A0_DQ0;
626
    if (FROMADDR)
627
        ( A6 => DQ4 ) = tpd_A0_DQ0;
628
    if (FROMADDR)
629
        ( A6 => DQ5 ) = tpd_A0_DQ0;
630
    if (FROMADDR)
631
        ( A6 => DQ6 ) = tpd_A0_DQ0;
632
    if (FROMADDR)
633
        ( A6 => DQ7 ) = tpd_A0_DQ0;
634
    if (FROMADDR)
635
        ( A7 => DQ0 ) = tpd_A0_DQ0;
636
    if (FROMADDR)
637
        ( A7 => DQ1 ) = tpd_A0_DQ0;
638
    if (FROMADDR)
639
        ( A7 => DQ2 ) = tpd_A0_DQ0;
640
    if (FROMADDR)
641
        ( A7 => DQ3 ) = tpd_A0_DQ0;
642
    if (FROMADDR)
643
        ( A7 => DQ4 ) = tpd_A0_DQ0;
644
    if (FROMADDR)
645
        ( A7 => DQ5 ) = tpd_A0_DQ0;
646
    if (FROMADDR)
647
        ( A7 => DQ6 ) = tpd_A0_DQ0;
648
    if (FROMADDR)
649
        ( A7 => DQ7 ) = tpd_A0_DQ0;
650
    if (FROMADDR)
651
        ( A8 => DQ0 ) = tpd_A0_DQ0;
652
    if (FROMADDR)
653
        ( A8 => DQ1 ) = tpd_A0_DQ0;
654
    if (FROMADDR)
655
        ( A8 => DQ2 ) = tpd_A0_DQ0;
656
    if (FROMADDR)
657
        ( A8 => DQ3 ) = tpd_A0_DQ0;
658
    if (FROMADDR)
659
        ( A8 => DQ4 ) = tpd_A0_DQ0;
660
    if (FROMADDR)
661
        ( A8 => DQ5 ) = tpd_A0_DQ0;
662
    if (FROMADDR)
663
        ( A8 => DQ6 ) = tpd_A0_DQ0;
664
    if (FROMADDR)
665
        ( A8 => DQ7 ) = tpd_A0_DQ0;
666
    if (FROMADDR)
667
        ( A9 => DQ0 ) = tpd_A0_DQ0;
668
    if (FROMADDR)
669
        ( A9 => DQ1 ) = tpd_A0_DQ0;
670
    if (FROMADDR)
671
        ( A9 => DQ2 ) = tpd_A0_DQ0;
672
    if (FROMADDR)
673
        ( A9 => DQ3 ) = tpd_A0_DQ0;
674
    if (FROMADDR)
675
        ( A9 => DQ4 ) = tpd_A0_DQ0;
676
    if (FROMADDR)
677
        ( A9 => DQ5 ) = tpd_A0_DQ0;
678
    if (FROMADDR)
679
        ( A9 => DQ6 ) = tpd_A0_DQ0;
680
    if (FROMADDR)
681
        ( A9 => DQ7 ) = tpd_A0_DQ0;
682
    if (FROMADDR)
683
        ( A10 => DQ0 ) = tpd_A0_DQ0;
684
    if (FROMADDR)
685
        ( A10 => DQ1 ) = tpd_A0_DQ0;
686
    if (FROMADDR)
687
        ( A10 => DQ2 ) = tpd_A0_DQ0;
688
    if (FROMADDR)
689
        ( A10 => DQ3 ) = tpd_A0_DQ0;
690
    if (FROMADDR)
691
        ( A10 => DQ4 ) = tpd_A0_DQ0;
692
    if (FROMADDR)
693
        ( A10 => DQ5 ) = tpd_A0_DQ0;
694
    if (FROMADDR)
695
        ( A10 => DQ6 ) = tpd_A0_DQ0;
696
    if (FROMADDR)
697
        ( A10 => DQ7 ) = tpd_A0_DQ0;
698
    if (FROMADDR)
699
        ( A11 => DQ0 ) = tpd_A0_DQ0;
700
    if (FROMADDR)
701
        ( A11 => DQ1 ) = tpd_A0_DQ0;
702
    if (FROMADDR)
703
        ( A11 => DQ2 ) = tpd_A0_DQ0;
704
    if (FROMADDR)
705
        ( A11 => DQ3 ) = tpd_A0_DQ0;
706
    if (FROMADDR)
707
        ( A11 => DQ4 ) = tpd_A0_DQ0;
708
    if (FROMADDR)
709
        ( A11 => DQ5 ) = tpd_A0_DQ0;
710
    if (FROMADDR)
711
        ( A11 => DQ6 ) = tpd_A0_DQ0;
712
    if (FROMADDR)
713
        ( A11 => DQ7 ) = tpd_A0_DQ0;
714
    if (FROMADDR)
715
        ( A12 => DQ0 ) = tpd_A0_DQ0;
716
    if (FROMADDR)
717
        ( A12 => DQ1 ) = tpd_A0_DQ0;
718
    if (FROMADDR)
719
        ( A12 => DQ2 ) = tpd_A0_DQ0;
720
    if (FROMADDR)
721
        ( A12 => DQ3 ) = tpd_A0_DQ0;
722
    if (FROMADDR)
723
        ( A12 => DQ4 ) = tpd_A0_DQ0;
724
    if (FROMADDR)
725
        ( A12 => DQ5 ) = tpd_A0_DQ0;
726
    if (FROMADDR)
727
        ( A12 => DQ6 ) = tpd_A0_DQ0;
728
    if (FROMADDR)
729
        ( A12 => DQ7 ) = tpd_A0_DQ0;
730
    if (FROMADDR)
731
        ( A13 => DQ0 ) = tpd_A0_DQ0;
732
    if (FROMADDR)
733
        ( A13 => DQ1 ) = tpd_A0_DQ0;
734
    if (FROMADDR)
735
        ( A13 => DQ2 ) = tpd_A0_DQ0;
736
    if (FROMADDR)
737
        ( A13 => DQ3 ) = tpd_A0_DQ0;
738
    if (FROMADDR)
739
        ( A13 => DQ4 ) = tpd_A0_DQ0;
740
    if (FROMADDR)
741
        ( A13 => DQ5 ) = tpd_A0_DQ0;
742
    if (FROMADDR)
743
        ( A13 => DQ6 ) = tpd_A0_DQ0;
744
    if (FROMADDR)
745
        ( A13 => DQ7 ) = tpd_A0_DQ0;
746
    if (FROMADDR)
747
        ( A14 => DQ0 ) = tpd_A0_DQ0;
748
    if (FROMADDR)
749
        ( A14 => DQ1 ) = tpd_A0_DQ0;
750
    if (FROMADDR)
751
        ( A14 => DQ2 ) = tpd_A0_DQ0;
752
    if (FROMADDR)
753
        ( A14 => DQ3 ) = tpd_A0_DQ0;
754
    if (FROMADDR)
755
        ( A14 => DQ4 ) = tpd_A0_DQ0;
756
    if (FROMADDR)
757
        ( A14 => DQ5 ) = tpd_A0_DQ0;
758
    if (FROMADDR)
759
        ( A14 => DQ6 ) = tpd_A0_DQ0;
760
    if (FROMADDR)
761
        ( A14 => DQ7 ) = tpd_A0_DQ0;
762
    if (FROMADDR)
763
        ( A15 => DQ0 ) = tpd_A0_DQ0;
764
    if (FROMADDR)
765
        ( A15 => DQ1 ) = tpd_A0_DQ0;
766
    if (FROMADDR)
767
        ( A15 => DQ2 ) = tpd_A0_DQ0;
768
    if (FROMADDR)
769
        ( A15 => DQ3 ) = tpd_A0_DQ0;
770
    if (FROMADDR)
771
        ( A15 => DQ4 ) = tpd_A0_DQ0;
772
    if (FROMADDR)
773
        ( A15 => DQ5 ) = tpd_A0_DQ0;
774
    if (FROMADDR)
775
        ( A15 => DQ6 ) = tpd_A0_DQ0;
776
    if (FROMADDR)
777
        ( A15 => DQ7 ) = tpd_A0_DQ0;
778
    if (FROMADDR)
779
        ( A16 => DQ0 ) = tpd_A0_DQ0;
780
    if (FROMADDR)
781
        ( A16 => DQ1 ) = tpd_A0_DQ0;
782
    if (FROMADDR)
783
        ( A16 => DQ2 ) = tpd_A0_DQ0;
784
    if (FROMADDR)
785
        ( A16 => DQ3 ) = tpd_A0_DQ0;
786
    if (FROMADDR)
787
        ( A16 => DQ4 ) = tpd_A0_DQ0;
788
    if (FROMADDR)
789
        ( A16 => DQ5 ) = tpd_A0_DQ0;
790
    if (FROMADDR)
791
        ( A16 => DQ6 ) = tpd_A0_DQ0;
792
    if (FROMADDR)
793
        ( A16 => DQ7 ) = tpd_A0_DQ0;
794
    if (FROMADDR)
795
        ( A17 => DQ0 ) = tpd_A0_DQ0;
796
    if (FROMADDR)
797
        ( A17 => DQ1 ) = tpd_A0_DQ0;
798
    if (FROMADDR)
799
        ( A17 => DQ2 ) = tpd_A0_DQ0;
800
    if (FROMADDR)
801
        ( A17 => DQ3 ) = tpd_A0_DQ0;
802
    if (FROMADDR)
803
        ( A17 => DQ4 ) = tpd_A0_DQ0;
804
    if (FROMADDR)
805
        ( A17 => DQ5 ) = tpd_A0_DQ0;
806
    if (FROMADDR)
807
        ( A17 => DQ6 ) = tpd_A0_DQ0;
808
    if (FROMADDR)
809
        ( A17 => DQ7 ) = tpd_A0_DQ0;
810
    if (FROMADDR)
811
        ( A18 => DQ0 ) = tpd_A0_DQ0;
812
    if (FROMADDR)
813
        ( A18 => DQ1 ) = tpd_A0_DQ0;
814
    if (FROMADDR)
815
        ( A18 => DQ2 ) = tpd_A0_DQ0;
816
    if (FROMADDR)
817
        ( A18 => DQ3 ) = tpd_A0_DQ0;
818
    if (FROMADDR)
819
        ( A18 => DQ4 ) = tpd_A0_DQ0;
820
    if (FROMADDR)
821
        ( A18 => DQ5 ) = tpd_A0_DQ0;
822
    if (FROMADDR)
823
        ( A18 => DQ6 ) = tpd_A0_DQ0;
824
    if (FROMADDR)
825
        ( A18 => DQ7 ) = tpd_A0_DQ0;
826
 
827
    if (FROMADDR)
828
        ( A19 => DQ0 ) = tpd_A0_DQ0;
829
    if (FROMADDR)
830
        ( A19 => DQ1 ) = tpd_A0_DQ0;
831
    if (FROMADDR)
832
        ( A19 => DQ2 ) = tpd_A0_DQ0;
833
    if (FROMADDR)
834
        ( A19 => DQ3 ) = tpd_A0_DQ0;
835
    if (FROMADDR)
836
        ( A19 => DQ4 ) = tpd_A0_DQ0;
837
    if (FROMADDR)
838
        ( A19 => DQ5 ) = tpd_A0_DQ0;
839
    if (FROMADDR)
840
        ( A19 => DQ6 ) = tpd_A0_DQ0;
841
    if (FROMADDR)
842
        ( A19 => DQ7 ) = tpd_A0_DQ0;
843
 
844
    if (FROMADDR)
845
        ( A20 => DQ0 ) = tpd_A0_DQ0;
846
    if (FROMADDR)
847
        ( A20 => DQ1 ) = tpd_A0_DQ0;
848
    if (FROMADDR)
849
        ( A20 => DQ2 ) = tpd_A0_DQ0;
850
    if (FROMADDR)
851
        ( A20 => DQ3 ) = tpd_A0_DQ0;
852
    if (FROMADDR)
853
        ( A20 => DQ4 ) = tpd_A0_DQ0;
854
    if (FROMADDR)
855
        ( A20 => DQ5 ) = tpd_A0_DQ0;
856
    if (FROMADDR)
857
        ( A20 => DQ6 ) = tpd_A0_DQ0;
858
    if (FROMADDR)
859
        ( A20 => DQ7 ) = tpd_A0_DQ0;
860
 
861
    if (FROMADDR)
862
        ( A21 => DQ0 ) = tpd_A0_DQ0;
863
    if (FROMADDR)
864
        ( A21 => DQ1 ) = tpd_A0_DQ0;
865
    if (FROMADDR)
866
        ( A21 => DQ2 ) = tpd_A0_DQ0;
867
    if (FROMADDR)
868
        ( A21 => DQ3 ) = tpd_A0_DQ0;
869
    if (FROMADDR)
870
        ( A21 => DQ4 ) = tpd_A0_DQ0;
871
    if (FROMADDR)
872
        ( A21 => DQ5 ) = tpd_A0_DQ0;
873
    if (FROMADDR)
874
        ( A21 => DQ6 ) = tpd_A0_DQ0;
875
    if (FROMADDR)
876
        ( A21 => DQ7 ) = tpd_A0_DQ0;
877
 
878
    if (~RESETNeg)
879
        ( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
880
    if (~RESETNeg)
881
        ( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
882
    if (~RESETNeg)
883
        ( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
884
    if (~RESETNeg)
885
        ( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
886
    if (~RESETNeg)
887
        ( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
888
    if (~RESETNeg)
889
        ( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
890
    if (~RESETNeg)
891
        ( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
892
    if (~RESETNeg)
893
        ( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
894
 
895
//for RY signal
896
  (WENeg => RY)     = tpd_WENeg_RY;
897
  (CENeg => RY)     = tpd_CENeg_RY;
898
 
899
////////////////////////////////////////////////////////////////////////////////
900
// Timing Violation                                                           //
901
////////////////////////////////////////////////////////////////////////////////
902
 
903
    $setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
904
    $setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
905
    $setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
906
    $setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
907
    $setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
908
    $setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
909
    $setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
910
    $setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
911
    $setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
912
    $setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
913
    $setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
914
    $setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
915
    $setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
916
    $setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
917
    $setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
918
    $setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
919
    $setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
920
    $setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
921
    $setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
922
    $setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
923
    $setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
924
    $setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
925
 
926
    $setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
927
    $setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
928
    $setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
929
    $setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
930
    $setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
931
    $setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
932
    $setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
933
    $setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
934
    $setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
935
    $setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
936
    $setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
937
    $setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
938
    $setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
939
    $setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
940
    $setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
941
    $setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
942
    $setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
943
    $setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
944
    $setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
945
    $setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
946
    $setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
947
    $setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
948
 
949
    $setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
950
    $setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
951
    $setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
952
    $setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
953
    $setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
954
    $setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
955
    $setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
956
    $setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
957
 
958
    $setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
959
    $setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
960
    $setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
961
    $setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
962
    $setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
963
    $setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
964
    $setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
965
    $setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
966
 
967
    $hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol);
968
    $hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol);
969
    $hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol);
970
    $hold ( posedge OENeg, WENeg, thold_WENeg_OENeg, Viol);
971
    $hold ( posedge WENeg, OENeg, thold_OENeg_WENeg, Viol);
972
 
973
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 ,  thold_A0_WENeg, Viol);
974
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 ,  thold_A0_WENeg, Viol);
975
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 ,  thold_A0_WENeg, Viol);
976
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 ,  thold_A0_WENeg, Viol);
977
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 ,  thold_A0_WENeg, Viol);
978
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 ,  thold_A0_WENeg, Viol);
979
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 ,  thold_A0_WENeg, Viol);
980
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 ,  thold_A0_WENeg, Viol);
981
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 ,  thold_A0_WENeg, Viol);
982
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol);
983
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol);
984
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol);
985
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol);
986
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol);
987
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol);
988
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol);
989
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol);
990
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol);
991
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol);
992
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol);
993
    $hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol);
994
 
995
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 ,  thold_A0_WENeg, Viol);
996
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 ,  thold_A0_WENeg, Viol);
997
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 ,  thold_A0_WENeg, Viol);
998
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 ,  thold_A0_WENeg, Viol);
999
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 ,  thold_A0_WENeg, Viol);
1000
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 ,  thold_A0_WENeg, Viol);
1001
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 ,  thold_A0_WENeg, Viol);
1002
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 ,  thold_A0_WENeg, Viol);
1003
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 ,  thold_A0_WENeg, Viol);
1004
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 ,  thold_A0_WENeg, Viol);
1005
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol);
1006
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol);
1007
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol);
1008
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol);
1009
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol);
1010
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol);
1011
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol);
1012
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol);
1013
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol);
1014
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol);
1015
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol);
1016
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol);
1017
 
1018
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol);
1019
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol);
1020
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol);
1021
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol);
1022
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol);
1023
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol);
1024
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol);
1025
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol);
1026
 
1027
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_CENeg, Viol);
1028
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_CENeg, Viol);
1029
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_CENeg, Viol);
1030
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_CENeg, Viol);
1031
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_CENeg, Viol);
1032
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_CENeg, Viol);
1033
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_CENeg, Viol);
1034
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_CENeg, Viol);
1035
 
1036
    $width (negedge RESETNeg, tpw_RESETNeg_negedge);
1037
    $width (posedge WENeg,    tpw_WENeg_posedge);
1038
    $width (negedge WENeg,    tpw_WENeg_negedge);
1039
    $width (posedge CENeg,    tpw_CENeg_posedge);
1040
    $width (negedge CENeg,    tpw_CENeg_negedge);
1041
    $width (negedge A0,       tpw_A0_negedge);//ok
1042
    $width (negedge A1,       tpw_A0_negedge);//ok
1043
    $width (negedge A2,       tpw_A0_negedge);//ok
1044
    $width (negedge A3,       tpw_A0_negedge);//ok
1045
    $width (negedge A4,       tpw_A0_negedge);//ok
1046
    $width (negedge A5,       tpw_A0_negedge);//ok
1047
    $width (negedge A6,       tpw_A0_negedge);//ok
1048
    $width (negedge A7,       tpw_A0_negedge);//ok
1049
    $width (negedge A8,       tpw_A0_negedge);//ok
1050
    $width (negedge A9,       tpw_A0_negedge);//ok
1051
    $width (negedge A10,       tpw_A0_negedge);//ok
1052
    $width (negedge A11,       tpw_A0_negedge);//ok
1053
    $width (negedge A12,       tpw_A0_negedge);//ok
1054
    $width (negedge A13,       tpw_A0_negedge);//ok
1055
    $width (negedge A14,       tpw_A0_negedge);//ok
1056
    $width (negedge A15,       tpw_A0_negedge);//ok
1057
    $width (negedge A16,       tpw_A0_negedge);//ok
1058
    $width (negedge A17,       tpw_A0_negedge);//ok
1059
    $width (negedge A18,       tpw_A0_negedge);//ok
1060
    $width (negedge A19,       tpw_A0_negedge);//ok
1061
    $width (negedge A20,       tpw_A0_negedge);//ok
1062
    $width (negedge A21,       tpw_A0_negedge);//ok
1063
    $width (posedge A0,       tpw_A0_posedge);//ok
1064
    $width (posedge A1,       tpw_A0_posedge);//ok
1065
    $width (posedge A2,       tpw_A0_posedge);//ok
1066
    $width (posedge A3,       tpw_A0_posedge);//ok
1067
    $width (posedge A4,       tpw_A0_posedge);//ok
1068
    $width (posedge A5,       tpw_A0_posedge);//ok
1069
    $width (posedge A6,       tpw_A0_posedge);//ok
1070
    $width (posedge A7,       tpw_A0_posedge);//ok
1071
    $width (posedge A8,       tpw_A0_posedge);//ok
1072
    $width (posedge A9,       tpw_A0_posedge);//ok
1073
    $width (posedge A10,       tpw_A0_posedge);//ok
1074
    $width (posedge A11,       tpw_A0_posedge);//ok
1075
    $width (posedge A12,       tpw_A0_posedge);//ok
1076
    $width (posedge A13,       tpw_A0_posedge);//ok
1077
    $width (posedge A14,       tpw_A0_posedge);//ok
1078
    $width (posedge A15,       tpw_A0_posedge);//ok
1079
    $width (posedge A16,       tpw_A0_posedge);//ok
1080
    $width (posedge A17,       tpw_A0_posedge);//ok
1081
    $width (posedge A18,       tpw_A0_posedge);//ok
1082
    $width (posedge A19,       tpw_A0_posedge);//ok
1083
    $width (posedge A20,       tpw_A0_posedge);//ok
1084
    $width (posedge A21,       tpw_A0_posedge);//ok
1085
 
1086
    endspecify
1087
 
1088
////////////////////////////////////////////////////////////////////////////////
1089
// Main Behavior Block                                                        //
1090
////////////////////////////////////////////////////////////////////////////////
1091
 
1092
// FSM states
1093
    parameter RESET               =6'd0;
1094
    parameter Z001                =6'd1;
1095
    parameter PREL_SETBWB         =6'd2;
1096
    parameter PREL_ULBYPASS       =6'd3;
1097
    parameter PREL_ULBYPASS_RESET =6'd4;
1098
    parameter AS                  =6'd5;
1099
    parameter A0SEEN              =6'd6;
1100
    parameter OTP                 =6'd7;
1101
    parameter OTP_Z001            =6'd8;
1102
    parameter OTP_PREL            =6'd9;
1103
    parameter OTP_AS              =6'd10;
1104
    parameter OTP_AS_CFI          =6'd11;
1105
    parameter OTP_A0SEEN          =6'd12;
1106
    parameter C8                  =6'd13;
1107
    parameter C8_Z001             =6'd14;
1108
    parameter C8_PREL             =6'd15;
1109
    parameter ERS                 =6'd16;
1110
    parameter SERS                =6'd17;
1111
    parameter ESPS                =6'd18;
1112
    parameter SERS_EXEC           =6'd19;
1113
    parameter ESP                 =6'd20;
1114
    parameter ESP_Z001            =6'd21;
1115
    parameter ESP_PREL            =6'd22;
1116
    parameter ESP_A0SEEN          =6'd23;
1117
    parameter ESP_AS              =6'd24;
1118
    parameter PGMS                =6'd25;
1119
    parameter CFI                 =6'd26;
1120
    parameter AS_CFI              =6'd27;
1121
    parameter ESP_CFI             =6'd28;
1122
    parameter ESP_AS_CFI          =6'd29;
1123
 
1124
    reg [5:0] current_state;
1125
    reg [5:0] next_state;
1126
 
1127
 reg deq;
1128
 
1129
    always @(DIn, DOut)
1130
    begin
1131
        if (DIn==DOut)
1132
            deq=1'b1;
1133
        else
1134
            deq=1'b0;
1135
    end
1136
    // check when data is generated from model to avoid setuphold check in
1137
    // those occasion
1138
    assign deg =deq;
1139
 
1140
// initialize memory and load preoload files if any
1141
    initial
1142
    begin : NBlck
1143
    integer i,j;
1144
    integer tmp1,tmp2,tmp3;
1145
    integer secure_silicon[0:SecSiSize];
1146
    reg     sector_prot[0:SecNum];
1147
 
1148
        for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
1149
        begin
1150
            Mem[i]=MaxData;
1151
        end
1152
        for (i=0;i<=SecSiSize;i=i+1)
1153
        begin
1154
           secure_silicon[i]=MaxData;
1155
        end
1156
        for (i=0;i<=SecNum;i=i+1)
1157
        begin
1158
           sector_prot[i]=0;
1159
        end
1160
        if (UserPreload && !(prot_file_name == "none"))
1161
        begin
1162
            //s29al032d_00_prot  sector protect file
1163
            //   //      - comment
1164
            //   @aa    - <aa> stands for sector address
1165
            //   (aa is incremented at every load)
1166
            //   b       - <b> is 1 for protected sector <aa>, 0 for unprotect.
1167
            $readmemb(prot_file_name,sector_prot);
1168
        end
1169
        if (UserPreload && !(mem_file_name == "none"))
1170
        begin
1171
            //s29al032d_00_memory preload file
1172
            //  @aaaaaa - <aaaaaa> stands for address within last defined sector
1173
            //  dd      - <dd> is byte to be written at Mem(nn)(aaaaaa++)
1174
            // (aaaaaa is incremented at every load)
1175
            $readmemh(mem_file_name,Mem);
1176
        end
1177
        if (UserPreload && !(secsi_file_name == "none"))
1178
        begin
1179
            //s29al032d_00_secsi memory preload file
1180
            //  @aaaa   - <aaaa> stands for address within last defined sector
1181
            //  dd      - <dd> is byte to be written at Mem(nn)(aaaa++)
1182
            // (aaaa is incremented at every load)
1183
            $readmemh(secsi_file_name,secure_silicon);
1184
        end
1185
 
1186
        for (i=0;i<=SecSiSize;i=i+1)
1187
        begin
1188
           SecSi[i] = secure_silicon[i];
1189
        end
1190
        for (i=0;i<=SecNum;i=i+1)
1191
            Ers_queue[i] = 0;
1192
        // every 4-group sectors protect bit must equel
1193
        for (i=0;i<=SecNum;i=i+1)
1194
            Sec_Prot[i] = sector_prot[i];
1195
 
1196
        if ((Sec_Prot[3:0] != 4'h0 && Sec_Prot[3:0] != 4'hF)
1197
        || (Sec_Prot[7:4] != 4'h0 && Sec_Prot[7:4] != 4'hF)
1198
        || (Sec_Prot[11:8] != 4'h0 && Sec_Prot[11:8] != 4'hF)
1199
        || (Sec_Prot[15:12] != 4'h0   && Sec_Prot[15:12] != 4'hF)
1200
        || (Sec_Prot[19:16] != 4'h0   && Sec_Prot[19:16] != 4'hF)
1201
        || (Sec_Prot[23:20] != 4'h0   && Sec_Prot[23:20] != 4'hF)
1202
        || (Sec_Prot[27:24] != 4'h0   && Sec_Prot[27:24] != 4'hF)
1203
        || (Sec_Prot[31:28] != 4'h0   && Sec_Prot[31:28] != 4'hF)
1204
        || (Sec_Prot[35:32] != 4'h0   && Sec_Prot[35:32] != 4'hF)
1205
        || (Sec_Prot[39:36] != 4'h0   && Sec_Prot[39:36] != 4'hF)
1206
        || (Sec_Prot[43:40] != 4'h0   && Sec_Prot[43:40] != 4'hF)
1207
        || (Sec_Prot[47:44] != 4'h0   && Sec_Prot[47:44] != 4'hF)
1208
        || (Sec_Prot[51:48] != 4'h0   && Sec_Prot[51:48] != 4'hF)
1209
        || (Sec_Prot[55:52] != 4'h0   && Sec_Prot[55:52] != 4'hF)
1210
        || (Sec_Prot[59:56] != 4'h0   && Sec_Prot[59:56] != 4'hF)
1211
        || (Sec_Prot[63:60] != 4'h0   && Sec_Prot[63:60] != 4'hF))
1212
 
1213
            $display("Bad sector protect group preload");
1214
 
1215
        WBData = -1;
1216
 
1217
    end
1218
 
1219
    //Power Up time 100 ns;
1220
    initial
1221
    begin
1222
        PoweredUp      = 1'b0;
1223
        #100 PoweredUp = 1'b1;
1224
    end
1225
 
1226
    always @(RESETNeg)
1227
    begin
1228
        RST <= #499 RESETNeg;
1229
    end
1230
 
1231
    initial
1232
    begin
1233
        write    = 1'b0;
1234
        read     = 1'b0;
1235
        Addr   = 0;
1236
 
1237
        ULBYPASS = 1'b0;
1238
        ESP_ACT  = 1'b0;
1239
        OTP_ACT  = 1'b0;
1240
 
1241
        PDONE    = 1'b1;
1242
        PSTART   = 1'b0;
1243
 
1244
        PERR     = 1'b0;
1245
 
1246
        EDONE    = 1'b1;
1247
        ESTART   = 1'b0;
1248
        ESUSP    = 1'b0;
1249
        ERES     = 1'b0;
1250
 
1251
        EERR     = 1'b0;
1252
        READY_in = 1'b0;
1253
        READY    = 1'b0;
1254
    end
1255
 
1256
    always @(posedge START_T1_in)
1257
    begin:TESTARTT1r
1258
        #tdevice_START_T1 START_T1 = START_T1_in;
1259
    end
1260
    always @(negedge START_T1_in)
1261
    begin:TESTARTT1f
1262
        #1 START_T1 = START_T1_in;
1263
    end
1264
 
1265
    always @(posedge CTMOUT_in)
1266
    begin:TCTMOUTr
1267
        #tdevice_CTMOUT CTMOUT = CTMOUT_in;
1268
    end
1269
    always @(negedge CTMOUT_in)
1270
    begin:TCTMOUTf
1271
        #1 CTMOUT = CTMOUT_in;
1272
    end
1273
 
1274
    always @(posedge READY_in)
1275
    begin:TREADYr
1276
        #tdevice_READY READY = READY_in;
1277
    end
1278
    always @(negedge READY_in)
1279
    begin:TREADYf
1280
        #1 READY = READY_in;
1281
    end
1282
    ////////////////////////////////////////////////////////////////////////////
1283
    ////     obtain 'LAST_EVENT information
1284
    ////////////////////////////////////////////////////////////////////////////
1285
    always @(negedge OENeg)
1286
    begin
1287
        OENeg_event = $time;
1288
    end
1289
    always @(negedge CENeg)
1290
    begin
1291
        CENeg_event = $time;
1292
    end
1293
 
1294
    always @(posedge OENeg)
1295
    begin
1296
        OENeg_posEvent = $time;
1297
    end
1298
    always @(posedge CENeg)
1299
    begin
1300
        CENeg_posEvent = $time;
1301
    end
1302
 
1303
    always @(A)
1304
    begin
1305
        ADDR_event = $time;
1306
    end
1307
 
1308
    ////////////////////////////////////////////////////////////////////////////
1309
    //// sequential process for reset control and FSM state transition
1310
    ////////////////////////////////////////////////////////////////////////////
1311
    always @(negedge RST)
1312
    begin
1313
        ESP_ACT = 1'b0;
1314
        ULBYPASS = 1'b0;
1315
        OTP_ACT = 1'b0;
1316
    end
1317
 
1318
    reg R;
1319
    reg E;
1320
    always @(RESETNeg)
1321
    begin
1322
        if (PoweredUp)
1323
        begin
1324
        //Hardware reset timing control
1325
            if (~RESETNeg)
1326
            begin
1327
                E = 1'b0;
1328
                if (~PDONE || ~EDONE)
1329
                begin
1330
                    //if program or erase in progress
1331
                    READY_in = 1'b1;
1332
                    R = 1'b1;
1333
                end
1334
                else
1335
                begin
1336
                    READY_in = 1'b0;
1337
                    R = 1'b0;         //prog or erase not in progress
1338
                end
1339
            end
1340
            else if (RESETNeg && RST)
1341
            begin
1342
                //RESET# pulse < tRP
1343
                READY_in = 1'b0;
1344
                R = 1'b0;
1345
                E = 1'b1;
1346
            end
1347
         end
1348
    end
1349
 
1350
    always @(next_state or RESETNeg or CENeg or RST or
1351
         READY or PoweredUp)
1352
    begin: StateTransition
1353
 
1354
        if (PoweredUp)
1355
        begin
1356
            if (RESETNeg && (~R || (R && READY)))
1357
            begin
1358
                current_state = next_state;
1359
                READY_in = 1'b0;
1360
                E = 1'b0;
1361
                R = 1'b0;
1362
                reseted = 1'b1;
1363
            end
1364
            else if ((~R && ~RESETNeg && ~RST) ||
1365
                  (R && ~RESETNeg && ~RST && ~READY) ||
1366
                  (R && RESETNeg && ~RST && ~READY))
1367
            begin
1368
                //no state transition while RESET# low
1369
                current_state = RESET; //reset start
1370
                reseted       = 1'b0;
1371
            end
1372
        end
1373
        else
1374
        begin
1375
            current_state = RESET;      // reset
1376
            reseted       = 1'b0;
1377
            E = 1'b0;
1378
            R = 1'b0;
1379
        end
1380
    end
1381
 
1382
//    /////////////////////////////////////////////////////////////////////////
1383
//    //Glitch Protection: Inertial Delay does not propagate pulses <5ns
1384
//    /////////////////////////////////////////////////////////////////////////
1385
    assign #5 gWE_n = WENeg_ipd;
1386
    assign #5 gCE_n = CENeg_ipd;
1387
    assign #5 gOE_n = OENeg_ipd;
1388
 
1389
    ///////////////////////////////////////////////////////////////////////////
1390
    //Process that reports warning when changes on signals WE#, CE#, OE# are
1391
    //discarded
1392
    ///////////////////////////////////////////////////////////////////////////
1393
    always @(WENeg)
1394
    begin: PulseWatch1
1395
        if (gWE_n == WENeg)
1396
           $display("Glitch on WE#");
1397
    end
1398
    always @(CENeg)
1399
    begin: PulseWatch2
1400
        if (gCE_n == CENeg)
1401
            $display("Glitch on CE#");
1402
    end
1403
    always @(OENeg)
1404
    begin: PulseWatch3
1405
        if (gOE_n == OENeg)
1406
            $display("Glitch on OE#");
1407
     end
1408
 
1409
    //latch address on rising edge and data on falling edge  of write
1410
    always @(gWE_n or  gCE_n or  gOE_n )
1411
    begin: write_dc
1412
        if (RESETNeg!=1'b0)
1413
        begin
1414
            if (~gWE_n && ~gCE_n && gOE_n)
1415
                write = 1'b1;
1416
            else
1417
                write = 1'b0;
1418
        end
1419
 
1420
        if (gWE_n && ~gCE_n && ~gOE_n)
1421
            read = 1'b1;
1422
        else
1423
            read = 1'b0;
1424
    end
1425
 
1426
    ///////////////////////////////////////////////////////////////////////////
1427
    ////Latch address on falling edge of WE# or CE# what ever comes later
1428
    ////Latch data on rising edge of WE# or CE# what ever comes first
1429
    //// also Write cycle decode
1430
    ////////////////////////////////////////////////////////////////////////////
1431
    integer A_tmp  ;
1432
    integer SA_tmp ;
1433
    integer A_tmp1 ;
1434
    integer Mem_tmp;
1435
    integer AS_addr;
1436
    reg CE;
1437
 
1438
    always @(WENeg_ipd)
1439
    begin
1440
        if (reseted)
1441
        begin
1442
            if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd )
1443
            begin
1444
                A_tmp   = A[10:0];
1445
                SA_tmp  = A[HiAddrBit:16];
1446
                A_tmp1  = A[15:0];
1447
                Mem_tmp = A;
1448
                AS_addr = A[21];
1449
            end
1450
        end
1451
    end
1452
 
1453
    always @(CENeg_ipd)
1454
    begin
1455
        if (reseted)
1456
        begin
1457
            if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) )
1458
            begin
1459
                 A_tmp   = A[10:0];
1460
                 SA_tmp  = A[HiAddrBit:16];
1461
                 A_tmp1  = A[15:0];
1462
                 Mem_tmp = A;
1463
                 AS_addr = A[21];
1464
            end
1465
            if  (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd)
1466
            begin
1467
                   SecAddr = SA_tmp;
1468
                   Address = A_tmp1;
1469
                   MemAddress = Mem_tmp;
1470
                   Addr = A_tmp;
1471
            end
1472
        end
1473
    end
1474
 
1475
    always @(negedge OENeg_ipd )
1476
    begin
1477
        if (reseted)
1478
        begin
1479
            if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd)
1480
            begin
1481
                A_tmp   = A[10:0];
1482
                SA_tmp  = A[HiAddrBit:16];
1483
                A_tmp1  = A[15:0];
1484
                Mem_tmp = A;
1485
                SecAddr = SA_tmp;
1486
                Address = A_tmp1;
1487
                MemAddress = Mem_tmp;
1488
                Addr = A_tmp;
1489
                AS_addr = A[21];
1490
            end
1491
 
1492
            SecAddr = SA_tmp;
1493
            Address = A_tmp1;
1494
            MemAddress = Mem_tmp;
1495
            CE = CENeg;
1496
            Addr = A_tmp;
1497
        end
1498
    end
1499
 
1500
    always @(A)
1501
    begin
1502
        if (reseted)
1503
            if (WENeg_ipd && ~CENeg_ipd && ~OENeg_ipd)
1504
            begin
1505
                A_tmp   = A[10:0];
1506
                SA_tmp  = A[HiAddrBit:16];
1507
                A_tmp1  = A[15:0];
1508
                Mem_tmp = A;
1509
                AS_addr = A[21];
1510
                SecAddr = SA_tmp;
1511
                Address = A_tmp1;
1512
                MemAddress = Mem_tmp;
1513
                Addr = A_tmp;
1514
                CE = CENeg;
1515
            end
1516
    end
1517
 
1518
    always @(posedge write)
1519
    begin
1520
         SecAddr = SA_tmp;
1521
         Address = A_tmp1;
1522
         MemAddress = Mem_tmp;
1523
         Addr = A_tmp;
1524
         CE = CENeg;
1525
    end
1526
 
1527
///////////////////////////////////////////////////////////////////////////
1528
// Timing control for the Program Operations
1529
///////////////////////////////////////////////////////////////////////////
1530
 
1531
    integer cnt_write = 0;
1532
    //time elapsed_write  ;
1533
    time duration_write ;
1534
    //time start_write    ;
1535
    event pdone_event;
1536
 
1537
    always @(posedge reseted)
1538
    begin
1539
        PDONE = 1'b1;
1540
    end
1541
 
1542
    always @(reseted or PSTART)
1543
    begin
1544
        if (reseted)
1545
        begin
1546
            if (PSTART && PDONE)
1547
            begin
1548
                if ((~FactoryProt   && OTP_ACT)||
1549
                   ( ~Sec_Prot[SA] &&(~Ers_queue[SA] || ~ESP_ACT )&& ~OTP_ACT))
1550
                begin
1551
                    duration_write = tdevice_POB + 5;
1552
                    PDONE = 1'b0;
1553
                    ->pdone_event;
1554
                end
1555
                else
1556
                begin
1557
                    PERR = 1'b1;
1558
                    PERR <= #1005 1'b0;
1559
                end
1560
            end
1561
        end
1562
    end
1563
 
1564
    always @(pdone_event)
1565
    begin:pdone_process
1566
        PDONE = 1'b0;
1567
        #duration_write PDONE = 1'b1;
1568
    end
1569
 
1570
/////////////////////////////////////////////////////////////////////////
1571
// Timing control for the Erase Operations
1572
/////////////////////////////////////////////////////////////////////////
1573
    integer cnt_erase = 0;
1574
    time elapsed_erase;
1575
    time duration_erase;
1576
    time start_erase;
1577
 
1578
    always @(posedge reseted)
1579
    begin
1580
        disable edone_process;
1581
        EDONE = 1'b1;
1582
    end
1583
    event edone_event;
1584
    always @(reseted or ESTART)
1585
    begin: erase
1586
    integer i;
1587
        if (reseted)
1588
        begin
1589
            if (ESTART && EDONE)
1590
            begin
1591
                cnt_erase = 0;
1592
                for (i=0;i<=SecNum;i=i+1)
1593
                begin
1594
                    if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]!=1'b1))
1595
                        cnt_erase = cnt_erase + 1;
1596
                end
1597
 
1598
                if (cnt_erase>0)
1599
                begin
1600
                    elapsed_erase = 0;
1601
                    duration_erase = cnt_erase* tdevice_SEO + 4;
1602
                    ->edone_event;
1603
                    start_erase = $time;
1604
                end
1605
                else
1606
                begin
1607
                    EERR = 1'b1;
1608
                    EERR <= #100005  1'b0;
1609
                end
1610
            end
1611
        end
1612
    end
1613
 
1614
    always @(edone_event)
1615
    begin : edone_process
1616
        EDONE = 1'b0;
1617
        #duration_erase EDONE = 1'b1;
1618
    end
1619
 
1620
    always @(reseted or ESUSP)
1621
    begin
1622
        if (reseted)
1623
            if (ESUSP && ~EDONE)
1624
            begin
1625
                disable edone_process;
1626
                elapsed_erase = $time - start_erase;
1627
                duration_erase = duration_erase - elapsed_erase;
1628
                EDONE = 1'b0;
1629
            end
1630
    end
1631
    always @(reseted or ERES)
1632
    begin
1633
        if (reseted)
1634
            if (ERES && ~EDONE)
1635
            begin
1636
                start_erase = $time;
1637
                EDONE = 1'b0;
1638
                ->edone_event;
1639
            end
1640
    end
1641
 
1642
//    /////////////////////////////////////////////////////////////////////////
1643
//    // Main Behavior Process
1644
//    // combinational process for next state generation
1645
//    /////////////////////////////////////////////////////////////////////////
1646
        reg PATTERN_1  = 1'b0;
1647
        reg PATTERN_2  = 1'b0;
1648
        reg A_PAT_1  = 1'b0;
1649
        reg A_PAT_2  = 1'b0;
1650
        reg A_PAT_3  = 1'b0;
1651
        integer DataByte   ;
1652
 
1653
    always @(negedge write)
1654
    begin
1655
        DataByte = DIn;
1656
        PATTERN_1 = DataByte==8'hAA ;
1657
        PATTERN_2 = DataByte==8'h55 ;
1658
        A_PAT_1   = 1'b1;
1659
        A_PAT_2   = Address==16'hAAA ;
1660
        A_PAT_3   = Address==16'h555 ;
1661
 
1662
    end
1663
 
1664
    always @(write or reseted)
1665
    begin: StateGen1
1666
        if (reseted!=1'b1)
1667
            next_state = current_state;
1668
        else
1669
        if (~write)
1670
            case (current_state)
1671
            RESET :
1672
            begin
1673
                if (PATTERN_1)
1674
                    next_state = Z001;
1675
                else if ((Addr==8'h55) && (DataByte==8'h98))
1676
                    next_state = CFI;
1677
                else
1678
                    next_state = RESET;
1679
            end
1680
 
1681
            CFI:
1682
            begin
1683
                if (DataByte==8'hF0)
1684
                     next_state = RESET;
1685
                else
1686
                     next_state =  CFI;
1687
            end
1688
 
1689
            Z001 :
1690
            begin
1691
                if (PATTERN_2)
1692
                        next_state = PREL_SETBWB;
1693
                else
1694
                        next_state = RESET;
1695
            end
1696
 
1697
            PREL_SETBWB :
1698
            begin
1699
                if (A_PAT_1 && (DataByte==16'h20))
1700
                    next_state = PREL_ULBYPASS;
1701
                else if  (A_PAT_1 && (DataByte==16'h90))
1702
                    next_state = AS;
1703
                else if (A_PAT_1 && (DataByte==16'hA0))
1704
                    next_state = A0SEEN;
1705
                else if (A_PAT_1 && (DataByte==16'h80))
1706
                        next_state = C8;
1707
                else if  (A_PAT_1 && (DataByte==16'h88))
1708
                    next_state = OTP;
1709
                else
1710
                    next_state = RESET;
1711
            end
1712
 
1713
            PREL_ULBYPASS :
1714
            begin
1715
                if (DataByte == 16'h90 )
1716
                    next_state <= PREL_ULBYPASS_RESET;
1717
                if (A_PAT_1 && (DataByte == 16'hA0))
1718
                    next_state = A0SEEN;
1719
                else
1720
                    next_state = PREL_ULBYPASS;
1721
            end
1722
 
1723
            PREL_ULBYPASS_RESET :
1724
            begin
1725
                if (DataByte == 16'h00 )
1726
                    if (ESP_ACT)
1727
                        next_state = ESP;
1728
                    else
1729
                        next_state = RESET;
1730
                else
1731
                     next_state <= PREL_ULBYPASS;
1732
            end
1733
 
1734
            AS :
1735
            begin
1736
                if (DataByte==16'hF0)
1737
                    next_state = RESET;
1738
                else if ((Addr==8'h55) && (DataByte==8'h98))
1739
                    next_state = AS_CFI;
1740
                else
1741
                    next_state = AS;
1742
            end
1743
 
1744
            AS_CFI:
1745
            begin
1746
                if (DataByte==8'hF0)
1747
                    next_state = AS;
1748
                else
1749
                    next_state = AS_CFI;
1750
            end
1751
 
1752
            A0SEEN :
1753
            begin
1754
                next_state = PGMS;
1755
            end
1756
 
1757
            OTP :
1758
            begin
1759
                if (PATTERN_1)
1760
                    next_state = OTP_Z001;
1761
                else
1762
                   next_state = OTP;
1763
            end
1764
 
1765
            OTP_Z001 :
1766
            begin
1767
                  if (PATTERN_2)
1768
                      next_state = OTP_PREL;
1769
                  else
1770
                      next_state = OTP;
1771
            end
1772
 
1773
              OTP_PREL :
1774
               begin
1775
                     if (A_PAT_1 && (DataByte == 16'h90))
1776
                         next_state = OTP_AS;
1777
                     else if (A_PAT_1 && (DataByte == 16'hA0))
1778
                         next_state = OTP_A0SEEN;
1779
                     else
1780
                         next_state = OTP;
1781
               end
1782
 
1783
            OTP_AS:
1784
             begin
1785
                   if (DataByte == 16'h00)
1786
                       if (ESP_ACT)
1787
                           next_state = ESP;
1788
                       else
1789
                           next_state = RESET;
1790
                   else if (DataByte == 16'hF0)
1791
                       next_state = OTP;
1792
                   else if (DataByte == 16'h98)
1793
                       next_state = OTP_AS_CFI;
1794
                   else
1795
                       next_state = OTP_AS;
1796
             end
1797
 
1798
            OTP_AS_CFI:
1799
             begin
1800
                   if (DataByte == 16'hF0)
1801
                       next_state = OTP_AS;
1802
                   else
1803
                       next_state = OTP_AS_CFI;
1804
             end
1805
 
1806
            OTP_A0SEEN :
1807
            begin
1808
                 if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
1809
                     (Address >= 16'hFF00))
1810
                     next_state = PGMS;
1811
                 else
1812
                     next_state = OTP;
1813
            end
1814
 
1815
            C8 :
1816
            begin
1817
                if (PATTERN_1)
1818
                    next_state = C8_Z001;
1819
                else
1820
                    next_state = RESET;
1821
            end
1822
 
1823
            C8_Z001 :
1824
            begin
1825
                if (PATTERN_2)
1826
                     next_state = C8_PREL;
1827
                else
1828
                     next_state = RESET;
1829
            end
1830
 
1831
            C8_PREL :
1832
            begin
1833
                if (A_PAT_1 && (DataByte==16'h10))
1834
                    next_state = ERS;
1835
                else if (DataByte==16'h30)
1836
                    next_state = SERS;
1837
                else
1838
                    next_state = RESET;
1839
            end
1840
 
1841
            ERS :
1842
            begin
1843
            end
1844
 
1845
            SERS :
1846
            begin
1847
                if (~CTMOUT && DataByte == 16'hB0)
1848
                    next_state = ESP; // ESP according to datasheet
1849
                else if (DataByte==16'h30)
1850
                     next_state = SERS;
1851
                else
1852
                     next_state = RESET;
1853
            end
1854
 
1855
            SERS_EXEC :
1856
            begin
1857
            end
1858
 
1859
            ESP :
1860
            begin
1861
               if (DataByte == 16'h30)
1862
                     next_state = SERS_EXEC;
1863
               else
1864
                 begin
1865
                    if (PATTERN_1)
1866
                         next_state = ESP_Z001;
1867
                    if (Addr == 8'h55 && DataByte == 8'h98)
1868
                         next_state = ESP_CFI;
1869
                 end
1870
            end
1871
 
1872
            ESP_CFI:
1873
            begin
1874
                if (DataByte == 8'hF0)
1875
                    next_state = ESP;
1876
                else
1877
                    next_state = ESP_CFI;
1878
            end
1879
 
1880
            ESP_Z001 :
1881
            begin
1882
                    if (PATTERN_2)
1883
                        next_state = ESP_PREL;
1884
                    else
1885
                        next_state = ESP;
1886
            end
1887
 
1888
            ESP_PREL :
1889
            begin
1890
                    if (A_PAT_1 && DataByte == 16'hA0)
1891
                        next_state = ESP_A0SEEN;
1892
                    else if (A_PAT_1 && DataByte == 16'h20)
1893
                        next_state <= PREL_ULBYPASS;
1894
                    else if (A_PAT_1 && DataByte == 16'h88)
1895
                        next_state <= OTP;
1896
                    else if (A_PAT_1 && DataByte == 16'h90)
1897
                        next_state = ESP_AS;
1898
                    else
1899
                        next_state = ESP;
1900
            end
1901
 
1902
            ESP_A0SEEN :
1903
            begin
1904
                 next_state = PGMS; //set ESP
1905
            end
1906
 
1907
            ESP_AS :
1908
            begin
1909
                if (DataByte == 16'hF0)
1910
                     next_state = ESP;
1911
                else if ((Addr==8'h55) && (DataByte==8'h98))
1912
                        next_state = ESP_AS_CFI;
1913
            end
1914
 
1915
            ESP_AS_CFI:
1916
            begin
1917
                if (DataByte == 8'hF0)
1918
                    next_state = ESP_AS;
1919
                else
1920
                    next_state = ESP_AS_CFI;
1921
            end
1922
 
1923
            endcase
1924
    end
1925
 
1926
    always @(posedge PDONE or negedge PERR)
1927
    begin: StateGen6
1928
        if (reseted!=1'b1)
1929
            next_state = current_state;
1930
        else
1931
        begin
1932
           if (current_state==PGMS && ULBYPASS)
1933
                next_state = PREL_ULBYPASS;
1934
           else if (current_state==PGMS && OTP_ACT)
1935
                next_state = OTP;
1936
           else if (current_state==PGMS && ESP_ACT)
1937
                next_state = ESP;
1938
           else if (current_state==PGMS)
1939
                next_state = RESET;
1940
        end
1941
    end
1942
 
1943
    always @(posedge EDONE or negedge EERR)
1944
    begin: StateGen2
1945
        if (reseted!=1'b1)
1946
            next_state = current_state;
1947
        else
1948
        begin
1949
            if ((current_state==ERS) || (current_state==SERS_EXEC))
1950
                next_state = RESET;
1951
        end
1952
    end
1953
 
1954
    always @(negedge write or reseted)
1955
    begin: StateGen7 //ok
1956
    integer i,j;
1957
        if (reseted!=1'b1)
1958
            next_state = current_state;
1959
        else
1960
        begin
1961
            if (current_state==SERS_EXEC && (write==1'b0) && (EERR!=1'b1))
1962
                if (DataByte==16'hB0)
1963
                begin
1964
                    next_state = ESPS;
1965
                    ESUSP = 1'b1;
1966
                    ESUSP <= #1 1'b0;
1967
                end
1968
        end
1969
    end
1970
 
1971
    always @(CTMOUT or reseted)
1972
    begin: StateGen4
1973
        if (reseted!=1'b1)
1974
            next_state = current_state;
1975
        else
1976
        begin
1977
            if (current_state==SERS && CTMOUT)  next_state = SERS_EXEC;
1978
        end
1979
    end
1980
 
1981
    always @(posedge START_T1 or reseted)
1982
    begin: StateGen5
1983
        if (reseted!=1'b1)
1984
            next_state = current_state;
1985
        else
1986
            if (current_state==ESPS && START_T1) next_state = ESP;
1987
    end
1988
 
1989
    ///////////////////////////////////////////////////////////////////////////
1990
    //FSM Output generation and general funcionality
1991
    ///////////////////////////////////////////////////////////////////////////
1992
 
1993
    always @(posedge read)
1994
    begin
1995
        ->oe_event;
1996
    end
1997
    always @(MemAddress)
1998
    begin
1999
        if (read)
2000
            ->oe_event;
2001
    end
2002
 
2003
    always @(oe_event)
2004
    begin
2005
        oe = 1'b1;
2006
        #1 oe = 1'b0;
2007
    end
2008
 
2009
    always @(DOut_zd)
2010
    begin : OutputGen
2011
        if (DOut_zd[0] !== 1'bz)
2012
        begin
2013
            CEDQ_t = CENeg_event  + CEDQ_01;
2014
            OEDQ_t = OENeg_event  + OEDQ_01;
2015
            ADDRDQ_t = ADDR_event + ADDRDQ_01;
2016
            FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
2017
            FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
2018
            FROMADDR = 1'b1;
2019
            if ((ADDRDQ_t > $time )&&
2020
             (((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
2021
              ((ADDRDQ_t>CEDQ_t)&&FROMCE)))
2022
            begin
2023
                TempData = DOut_zd;
2024
                FROMADDR = 1'b0;
2025
                DOut_Pass = 8'bx;
2026
                #(ADDRDQ_t - $time) DOut_Pass = TempData;
2027
            end
2028
            else
2029
            begin
2030
                DOut_Pass = DOut_zd;
2031
            end
2032
       end
2033
    end
2034
 
2035
    always @(DOut_zd)
2036
    begin
2037
        if (DOut_zd[0] === 1'bz)
2038
        begin
2039
           disable OutputGen;
2040
           FROMCE = 1'b1;
2041
           FROMOE = 1'b1;
2042
           if ((CENeg_posEvent <= OENeg_posEvent) &&
2043
           ( CENeg_posEvent + 5 >= $time))
2044
               FROMOE = 1'b0;
2045
           if ((OENeg_posEvent < CENeg_posEvent) &&
2046
           ( OENeg_posEvent + 5 >= $time))
2047
               FROMCE = 1'b0;
2048
           FROMADDR = 1'b0;
2049
           DOut_Pass = DOut_zd;
2050
       end
2051
    end
2052
 
2053
    always @(oe or reseted or current_state)
2054
    begin
2055
        if (reseted)
2056
        begin
2057
        case (current_state)
2058
 
2059
            RESET :
2060
            begin
2061
                if (oe)
2062
                    MemRead(DOut_zd);
2063
            end
2064
 
2065
            AS, ESP_AS, OTP_AS :
2066
            begin
2067
              if (oe)
2068
                    begin
2069
                        if (AS_addr == 1'b0)
2070
                            begin
2071
                            end
2072
                        else
2073
                            AS_ID = 1'b0;
2074
                        if ((Address[7:0] == 0) && (AS_ID == 1'b1))
2075
                            DOut_zd = 1;
2076
                        else if ((Address[7:0] == 1) && (AS_ID == 1'b1))
2077
                            DOut_zd = 8'hA3;
2078
                        else if ((Address[7:0] == 2) &&
2079
                            (((SecAddr < 32 ) && (AS_ID == 1'b1))
2080
                            || ((SecAddr > 31 ) && (AS_ID2 == 1'b1))))
2081
                        begin
2082
                            DOut_zd    = 8'b00000000;
2083
                            DOut_zd[0] = Sec_Prot[SecAddr];
2084
                        end
2085
                        else if ((Address[7:0] == 6) && (AS_SecSi_FP == 1'b1))
2086
                        begin
2087
                            DOut_zd = 8'b0;
2088
                            if (FactoryProt)
2089
                                DOut_zd = 16'h99;
2090
                            else
2091
                                DOut_zd = 16'h19;
2092
                        end
2093
                        else
2094
                            DOut_zd    = 8'bz;
2095
                    end
2096
            end
2097
 
2098
            OTP :
2099
             begin
2100
                 if (oe)
2101
                 begin
2102
                     if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
2103
                        (Address >= 16'hFF00))
2104
                     begin
2105
                         SecSiAddr = Address%(SecSiSize +1);
2106
                         if (SecSi[SecSiAddr]==-1)
2107
                             DOut_zd = 8'bx;
2108
                         else
2109
                             DOut_zd = SecSi[SecSiAddr];
2110
                     end
2111
                     else
2112
                         $display ("Invalid SecSi query address");
2113
                 end
2114
             end
2115
 
2116
            CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, OTP_AS_CFI :
2117
            begin
2118
            if (oe)
2119
            begin
2120
                 DOut_zd = 8'bZ;
2121
                 if (((MemAddress>=16'h10) && (MemAddress <= 16'h3C)) ||
2122
                     ((MemAddress>=16'h40) && (MemAddress <= 16'h4F)))
2123
                 begin
2124
                     DOut_zd = CFI_array[MemAddress];
2125
                 end
2126
                 else
2127
                 begin
2128
                     $display ("Invalid CFI query address");
2129
                 end
2130
            end
2131
            end
2132
 
2133
            ERS :
2134
            begin
2135
                if (oe)
2136
                begin
2137
                    ///////////////////////////////////////////////////////////
2138
                    // read status / embeded erase algorithm - Chip Erase
2139
                    ///////////////////////////////////////////////////////////
2140
                    Status[7] = 1'b0;
2141
                    Status[6] = ~Status[6]; //toggle
2142
                    Status[5] = 1'b0;
2143
                    Status[3] = 1'b1;
2144
                    Status[2] = ~Status[2]; //toggle
2145
 
2146
                    DOut_zd = Status;
2147
                end
2148
            end
2149
 
2150
        SERS :
2151
        begin
2152
            if (oe)
2153
            begin
2154
                ///////////////////////////////////////////////////////////
2155
                //read status - sector erase timeout
2156
                ///////////////////////////////////////////////////////////
2157
                Status[3] = 1'b0;
2158
                Status[7] = 1'b1;
2159
                DOut_zd = Status;
2160
            end
2161
        end
2162
 
2163
        ESPS :
2164
        begin
2165
            if (oe)
2166
            begin
2167
                ///////////////////////////////////////////////////////////
2168
                //read status / erase suspend timeout - stil erasing
2169
                ///////////////////////////////////////////////////////////
2170
                if (Ers_queue[SecAddr]==1'b1)
2171
                begin
2172
                    Status[7] = 1'b0;
2173
                    Status[2] = ~Status[2]; //toggle
2174
                end
2175
                else
2176
                    Status[7] = 1'b1;
2177
                Status[6] = ~Status[6]; //toggle
2178
                Status[5] = 1'b0;
2179
                Status[3] = 1'b1;
2180
                DOut_zd = Status;
2181
            end
2182
        end
2183
 
2184
        SERS_EXEC:
2185
        begin
2186
            if (oe)
2187
            begin
2188
                 ///////////////////////////////////////////////////
2189
                 //read status erase
2190
                 ///////////////////////////////////////////////////
2191
                 if (Ers_queue[SecAddr]==1'b1)
2192
                 begin
2193
                     Status[7] = 1'b0;
2194
                     Status[2] = ~Status[2]; //toggle
2195
                 end
2196
                 else
2197
                 Status[7] = 1'b1;
2198
                 Status[6] = ~Status[6]; //toggle
2199
                 Status[5] = 1'b0;
2200
                 Status[3] = 1'b1;
2201
                 DOut_zd = Status;
2202
            end
2203
        end
2204
 
2205
        ESP :
2206
        begin
2207
            if (oe)
2208
            begin
2209
                ///////////////////////////////////////////////////////////
2210
                //read
2211
                ///////////////////////////////////////////////////////////
2212
 
2213
                if    (Ers_queue[SecAddr]!=1'b1)
2214
                begin
2215
                    MemRead(DOut_zd);
2216
                end
2217
                else
2218
                begin
2219
                    ///////////////////////////////////////////////////////
2220
                    //read status
2221
                    ///////////////////////////////////////////////////////
2222
                    Status[7] = 1'b1;
2223
                    // Status[6) No toggle
2224
                    Status[5] = 1'b0;
2225
                    Status[2] = ~Status[2]; //toggle
2226
                    DOut_zd = Status;
2227
                end
2228
            end
2229
        end
2230
 
2231
        PGMS :
2232
        begin
2233
            if (oe)
2234
            begin
2235
                ///////////////////////////////////////////////////////////
2236
                //read status
2237
                ///////////////////////////////////////////////////////////
2238
                Status[6] = ~Status[6]; //toggle
2239
                Status[5] = 1'b0;
2240
                //Status[2) no toggle
2241
                Status[1] = 1'b0;
2242
                DOut_zd = Status;
2243
                if (SecAddr == SA)
2244
                    DOut_zd[7] = Status[7];
2245
                else
2246
                    DOut_zd[7] = ~Status[7];
2247
            end
2248
 
2249
        end
2250
        endcase
2251
    end
2252
    end
2253
 
2254
    always @(write or reseted)
2255
    begin : Output_generation
2256
        if (reseted)
2257
        begin
2258
        case (current_state)
2259
            RESET :
2260
            begin
2261
                ESP_ACT  = 1'b0;
2262
                ULBYPASS = 1'b0;
2263
                OTP_ACT  = 1'b0;
2264
                if (~write)
2265
                    if (A_PAT_2 && PATTERN_1)
2266
                        AS_SecSi_FP = 1'b1;
2267
                    else
2268
                        AS_SecSi_FP = 1'b0;
2269
            end
2270
 
2271
            Z001 :
2272
            begin
2273
            if (~write)
2274
                if (A_PAT_3 && PATTERN_2)
2275
                    begin
2276
                    end
2277
                else
2278
                    AS_SecSi_FP = 1'b0;
2279
            end
2280
 
2281
            PREL_SETBWB :
2282
            begin
2283
                if (~write)
2284
                begin
2285
                    if (A_PAT_1 && (DataByte==16'h20))
2286
                        ULBYPASS = 1'b1;
2287
                    else if (A_PAT_1 && (DataByte==16'h90))
2288
                        begin
2289
                            ULBYPASS = 1'b0;
2290
                            if (A_PAT_2)
2291
                                begin
2292
                                end
2293
                            else
2294
                                AS_SecSi_FP = 1'b0;
2295
                            if (AS_addr == 1'b0)
2296
                                begin
2297
                                    AS_ID = 1'b1;
2298
                                    AS_ID2= 1'b0;
2299
                                end
2300
                            else
2301
                                begin
2302
                                    AS_ID = 1'b0;
2303
                                    AS_ID2= 1'b1;
2304
                                end
2305
                        end
2306
                    else if (A_PAT_1 && (DataByte==16'h88))
2307
                      begin
2308
                        OTP_ACT   = 1;
2309
                        ULBYPASS = 1'b0;
2310
                      end
2311
                end
2312
            end
2313
 
2314
            PREL_ULBYPASS :
2315
            begin
2316
                if (~write)
2317
                begin
2318
                ULBYPASS = 1'b1;
2319
                   if (A_PAT_1 && (DataByte==16'h90))
2320
                        ULBYPASS = 1'b0;
2321
                end
2322
            end
2323
 
2324
            PREL_ULBYPASS_RESET :
2325
                if ((~write) && (DataByte != 16'h00 ))
2326
                        ULBYPASS = 1'b1;
2327
 
2328
            OTP_A0SEEN :
2329
            begin
2330
                if (~write)
2331
                begin
2332
                    if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
2333
                       (Address >= 16'hFF00))
2334
                    begin
2335
                        SecSiAddr = Address%(SecSiSize +1);
2336
                        OTP_ACT = 1;
2337
                        PSTART = 1'b1;
2338
                        PSTART <= #1 1'b0;
2339
 
2340
                        WBAddr = SecSiAddr;
2341
                        SA = SecAddr;
2342
                        temp = DataByte;
2343
                        Status[7] = ~temp[7];
2344
                        WBData = DataByte;
2345
                    end
2346
                    else
2347
                        $display ("Invalid program address in SecSi region:"
2348
                                  ,Address);
2349
                end
2350
            end
2351
 
2352
            OTP_PREL :
2353
            begin
2354
                if (~write)
2355
                    if (A_PAT_1 && (DataByte==16'h90))
2356
                       begin
2357
                           ULBYPASS = 1'b0;
2358
                           if (A_PAT_2)
2359
                               begin
2360
                               end
2361
                           else
2362
                               AS_SecSi_FP = 1'b0;
2363
                           if (AS_addr == 1'b0)
2364
                               begin
2365
                                   AS_ID = 1'b1;
2366
                                   AS_ID2= 1'b0;
2367
                               end
2368
                           else
2369
                               begin
2370
                                   AS_ID = 1'b0;
2371
                                   AS_ID2= 1'b1;
2372
                               end
2373
                       end
2374
 
2375
            end
2376
 
2377
           OTP_Z001 :
2378
           begin
2379
                if (~write)
2380
                    if (A_PAT_3 && PATTERN_2)
2381
                        begin
2382
                        end
2383
                    else
2384
                        AS_SecSi_FP = 1'b0;
2385
           end
2386
 
2387
           OTP :
2388
            begin
2389
                if (~write)
2390
                    if (A_PAT_2 && PATTERN_1)
2391
                        AS_SecSi_FP = 1'b1;
2392
                    else
2393
                        AS_SecSi_FP = 1'b0;
2394
                RY_zd = 1;
2395
            end
2396
 
2397
            AS :
2398
            begin
2399
                if (~write)
2400
                    if (DataByte==16'hF0)
2401
                        begin
2402
                            AS_SecSi_FP = 1'b0;
2403
                            AS_ID = 1'b0;
2404
                            AS_ID2 = 1'b0;
2405
                        end
2406
            end
2407
 
2408
            A0SEEN :
2409
            begin
2410
                if (~write)
2411
                begin
2412
                    PSTART = 1'b1;
2413
                    PSTART <= #1 1'b0;
2414
                    WBData = DataByte;
2415
                    WBAddr = Address;
2416
                    SA = SecAddr;
2417
                    Status[7] = ~DataByte[7];
2418
                end
2419
            end
2420
 
2421
            C8 :
2422
            begin
2423
            end
2424
 
2425
            C8_Z001 :
2426
            begin
2427
            end
2428
 
2429
            C8_PREL :
2430
            begin
2431
                if (~write)
2432
                    if (A_PAT_1 && (DataByte==16'h10))
2433
                    begin
2434
                        //Start Chip Erase
2435
                        ESTART = 1'b1;
2436
                        ESTART <= #1 1'b0;
2437
                        ESUSP  = 1'b0;
2438
                        ERES   = 1'b0;
2439
                        Ers_queue = ~(0);
2440
                        Status = 8'b00001000;
2441
                    end
2442
                    else if (DataByte==16'h30)
2443
                    begin
2444
                        //put selected sector to sec. ers. queue
2445
                        //start timeout
2446
                        Ers_queue = 0;
2447
                        Ers_queue[SecAddr] = 1'b1;
2448
                        disable TCTMOUTr;
2449
                        CTMOUT_in = 1'b0;
2450
                        #1 CTMOUT_in <= 1'b1;
2451
                     end
2452
            end
2453
 
2454
            ERS :
2455
            begin
2456
            end
2457
 
2458
            SERS :
2459
            begin
2460
                if (~write && ~CTMOUT)
2461
                begin
2462
                    if (DataByte == 16'hB0)
2463
                    begin
2464
                        //need to start erase process prior to suspend
2465
                        ESTART = 1'b1;
2466
                        ESTART = #1 1'b0;
2467
                        ESUSP  = #1 1'b0;
2468
                        ESUSP  = #1 1'b1;
2469
                        ESUSP  <= #2 1'b0;
2470
                        ERES   = 1'b0;
2471
                    end
2472
                    else if (DataByte==16'h30)
2473
                    begin
2474
                        disable TCTMOUTr;
2475
                        CTMOUT_in = 1'b0;
2476
                        #1 CTMOUT_in <= 1'b1;
2477
                        Ers_queue[SecAddr] = 1'b1;
2478
                    end
2479
                end
2480
            end
2481
 
2482
            SERS_EXEC :
2483
            begin
2484
            if (~write)
2485
                if (~EDONE && (EERR!=1'b1) && DataByte==16'hB0)
2486
                        START_T1_in = 1'b1;
2487
            end
2488
 
2489
            ESP :
2490
            begin
2491
                if (~write)
2492
                begin
2493
                    if (A_PAT_2 && PATTERN_1)
2494
                        AS_SecSi_FP = 1'b1;
2495
                    else
2496
                        AS_SecSi_FP = 1'b0;
2497
                    if (DataByte == 16'h30)
2498
                    begin
2499
                        ERES = 1'b1;
2500
                        ERES <= #1 1'b0;
2501
                    end
2502
                end
2503
            end
2504
 
2505
            ESP_Z001 :
2506
            begin
2507
                if (~write)
2508
                    if (A_PAT_3 && PATTERN_2)
2509
                        begin
2510
                        end
2511
                    else
2512
                        AS_SecSi_FP = 1'b0;
2513
            end
2514
 
2515
            ESP_PREL :
2516
            begin
2517
                if (~write)
2518
                    if (A_PAT_1 && (DataByte==16'h90))
2519
                       begin
2520
                           ULBYPASS = 1'b0;
2521
                           if (A_PAT_2)
2522
                               begin
2523
                               end
2524
                           else
2525
                               AS_SecSi_FP = 1'b0;
2526
                           if (AS_addr == 1'b0)
2527
                               begin
2528
                                   AS_ID = 1'b1;
2529
                                   AS_ID2= 1'b0;
2530
                               end
2531
                           else
2532
                               begin
2533
                                   AS_ID = 1'b0;
2534
                                   AS_ID2= 1'b1;
2535
                               end
2536
                       end
2537
            end
2538
 
2539
            ESP_A0SEEN :
2540
            begin
2541
                if (~write)
2542
                begin
2543
                    ESP_ACT = 1'b1;
2544
                    PSTART = 1'b1;
2545
                    PSTART <= #1 1'b0;
2546
                    WBData = DataByte;
2547
                    WBAddr = Address;
2548
                    SA = SecAddr;
2549
                    Status[7] = ~DataByte[7];
2550
                end
2551
            end
2552
 
2553
            ESP_AS :
2554
            begin
2555
            end
2556
 
2557
        endcase
2558
        end
2559
    end
2560
 
2561
    initial
2562
    begin
2563
        ///////////////////////////////////////////////////////////////////////
2564
        //CFI array data
2565
        ///////////////////////////////////////////////////////////////////////
2566
 
2567
            //CFI query identification string
2568
            for (i=16;i<92;i=i+1)
2569
                 CFI_array[i] = -1;
2570
 
2571
            CFI_array[16'h10] = 16'h51;
2572
            CFI_array[16'h11] = 16'h52;
2573
            CFI_array[16'h12] = 16'h59;
2574
            CFI_array[16'h13] = 16'h02;
2575
            CFI_array[16'h14] = 16'h00;
2576
            CFI_array[16'h15] = 16'h40;
2577
            CFI_array[16'h16] = 16'h00;
2578
            CFI_array[16'h17] = 16'h00;
2579
            CFI_array[16'h18] = 16'h00;
2580
            CFI_array[16'h19] = 16'h00;
2581
            CFI_array[16'h1A] = 16'h00;
2582
 
2583
            //system interface string
2584
            CFI_array[16'h1B] = 16'h27;
2585
            CFI_array[16'h1C] = 16'h36;
2586
            CFI_array[16'h1D] = 16'h00;
2587
            CFI_array[16'h1E] = 16'h00;
2588
            CFI_array[16'h1F] = 16'h04;
2589
            CFI_array[16'h20] = 16'h00;
2590
            CFI_array[16'h21] = 16'h0A;
2591
            CFI_array[16'h22] = 16'h00;
2592
            CFI_array[16'h23] = 16'h05;
2593
            CFI_array[16'h24] = 16'h00;
2594
            CFI_array[16'h25] = 16'h04;
2595
            CFI_array[16'h26] = 16'h00;
2596
            //device geometry definition
2597
            CFI_array[16'h27] = 16'h16;
2598
            CFI_array[16'h28] = 16'h00;
2599
            CFI_array[16'h29] = 16'h00;
2600
            CFI_array[16'h2A] = 16'h00;
2601
            CFI_array[16'h2B] = 16'h00;
2602
            CFI_array[16'h2C] = 16'h01;
2603
            CFI_array[16'h2D] = 16'h3F;
2604
            CFI_array[16'h2E] = 16'h00;
2605
            CFI_array[16'h2F] = 16'h00;
2606
            CFI_array[16'h30] = 16'h01;
2607
            CFI_array[16'h31] = 16'h00;
2608
            CFI_array[16'h32] = 16'h00;
2609
            CFI_array[16'h33] = 16'h00;
2610
            CFI_array[16'h34] = 16'h00;
2611
            CFI_array[16'h35] = 16'h00;
2612
            CFI_array[16'h36] = 16'h00;
2613
            CFI_array[16'h37] = 16'h00;
2614
            CFI_array[16'h38] = 16'h00;
2615
            CFI_array[16'h39] = 16'h00;
2616
            CFI_array[16'h3A] = 16'h00;
2617
            CFI_array[16'h3B] = 16'h00;
2618
            CFI_array[16'h3C] = 16'h00;
2619
 
2620
            //primary vendor-specific extended query
2621
            CFI_array[16'h40] = 16'h50;
2622
            CFI_array[16'h41] = 16'h52;
2623
            CFI_array[16'h42] = 16'h49;
2624
            CFI_array[16'h43] = 16'h31;
2625
            CFI_array[16'h44] = 16'h31;
2626
            CFI_array[16'h45] = 16'h01;
2627
            CFI_array[16'h46] = 16'h02;
2628
            CFI_array[16'h47] = 16'h01;
2629
            CFI_array[16'h48] = 16'h01;
2630
            CFI_array[16'h49] = 16'h04;
2631
            CFI_array[16'h4A] = 16'h00;
2632
            CFI_array[16'h4B] = 16'h00;
2633
            CFI_array[16'h4C] = 16'h00;
2634
            CFI_array[16'h4D] = 16'hB5;
2635
            CFI_array[16'h4E] = 16'hC5;
2636
            CFI_array[16'h4F] = 16'h00;
2637
 
2638
   end
2639
 
2640
    always @(current_state or reseted)
2641
    begin
2642
        if (reseted)
2643
            if (current_state==RESET)         RY_zd = 1'b1;
2644
            if (current_state==PREL_ULBYPASS) RY_zd = 1'b1;
2645
            if (current_state==A0SEEN)        RY_zd = 1'b1;
2646
            if (current_state==ERS)           RY_zd = 1'b0;
2647
            if (current_state==SERS)          RY_zd = 1'b0;
2648
            if (current_state==ESPS)          RY_zd = 1'b0;
2649
            if (current_state==SERS_EXEC)     RY_zd = 1'b0;
2650
            if (current_state==ESP)           RY_zd = 1'b1;
2651
            if (current_state==OTP)           RY_zd = 1'b1;
2652
            if (current_state==ESP_A0SEEN)    RY_zd = 1'b1;
2653
            if (current_state==PGMS)          RY_zd = 1'b0;
2654
    end
2655
 
2656
    always @(EERR or EDONE or current_state)
2657
    begin : ERS2
2658
    integer i;
2659
    integer j;
2660
        if (current_state==ERS  && EERR!=1'b1)
2661
            for (i=0;i<=SecNum;i=i+1)
2662
            begin
2663
                if (Sec_Prot[i]!=1'b1)
2664
                    for (j=0;j<=SecSize;j=j+1)
2665
                       Mem[sa(i)+j] = -1;
2666
            end
2667
        if (current_state==ERS  && EDONE)
2668
            for (i=0;i<=SecNum;i=i+1)
2669
            begin
2670
                if (Sec_Prot[i]!=1'b1)
2671
                    for (j=0;j<=SecSize;j=j+1)
2672
                         Mem[sa(i)+j] = MaxData;
2673
           end
2674
    end
2675
 
2676
    always @(CTMOUT or current_state)
2677
    begin : SERS2
2678
        if (current_state==SERS && CTMOUT)
2679
        begin
2680
            CTMOUT_in = 1'b0;
2681
            START_T1_in = 1'b0;
2682
            ESTART = 1'b1;
2683
            ESTART <= #1 1'b0;
2684
            ESUSP  = 1'b0;
2685
            ERES   = 1'b0;
2686
        end
2687
    end
2688
 
2689
    always @(START_T1 or current_state)
2690
    begin : ESPS2
2691
        if (current_state==ESPS && START_T1)
2692
        begin
2693
            ESP_ACT = 1'b1;
2694
            START_T1_in = 1'b0;
2695
        end
2696
    end
2697
 
2698
    always @(EERR or EDONE or current_state)
2699
    begin: SERS_EXEC2
2700
    integer i,j;
2701
        if (current_state==SERS_EXEC)
2702
        begin
2703
            if (EERR!=1'b1)
2704
            begin
2705
                for (i=0;i<=SecNum;i=i+1)
2706
                begin
2707
                    if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
2708
                        for (j=0;j<=SecSize;j=j+1)
2709
                            Mem[sa(i)+j] = -1;
2710
 
2711
                if (EDONE)
2712
                    for (i=0;i<=SecNum;i=i+1)
2713
                    begin
2714
                        if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
2715
                            for (j=0;j<=SecSize;j=j+1)
2716
                                Mem[sa(i)+j] = MaxData;
2717
                        end
2718
                    end
2719
            end
2720
        end
2721
    end
2722
 
2723
    always @(current_state or posedge PDONE)
2724
    begin: PGMS2
2725
    integer i,j;
2726
        if (current_state==PGMS)
2727
        begin
2728
            if (PERR!=1'b1)
2729
            begin
2730
                new_int = WBData;
2731
                if (OTP_ACT!=1'b1)   //mem write
2732
                   old_int=Mem[sa(SA) + WBAddr];
2733
                else
2734
                   old_int=SecSi[WBAddr];
2735
                   new_bit = new_int;
2736
                   if (old_int>-1)
2737
                   begin
2738
                       old_bit = old_int;
2739
                       for(j=0;j<=7;j=j+1)
2740
                           if (~old_bit[j])
2741
                               new_bit[j]=1'b0;
2742
                           new_int=new_bit;
2743
                   end
2744
                   WBData = new_int;
2745
                 if (OTP_ACT!=1'b1)   //mem write
2746
                   Mem[sa(SA) + WBAddr] = -1;
2747
                 else
2748
                   SecSi[WBAddr] = -1;
2749
                 if (PDONE && ~PSTART)
2750
                 begin
2751
                      if (OTP_ACT!=1'b1)   //mem write
2752
                        Mem[sa(SA) + WBAddr] = WBData;
2753
                      else
2754
                        SecSi[WBAddr] = WBData;
2755
                      WBData= -1;
2756
                 end
2757
            end
2758
        end
2759
    end
2760
 
2761
    always @(gOE_n or gCE_n or RESETNeg or RST )
2762
    begin
2763
        //Output Disable Control
2764
        if (gOE_n || gCE_n || (~RESETNeg && ~RST))
2765
            DOut_zd = 8'bZ;
2766
    end
2767
 
2768
    reg  BuffInOE , BuffInCE , BuffInADDR;
2769
    wire BuffOutOE, BuffOutCE, BuffOutADDR;
2770
 
2771
    BUFFER    BUFOE   (BuffOutOE, BuffInOE);
2772
    BUFFER    BUFCE   (BuffOutCE, BuffInCE);
2773
    BUFFER    BUFADDR (BuffOutADDR, BuffInADDR);
2774
    initial
2775
    begin
2776
        BuffInOE   = 1'b1;
2777
        BuffInCE   = 1'b1;
2778
        BuffInADDR = 1'b1;
2779
    end
2780
 
2781
    always @(posedge BuffOutOE)
2782
    begin
2783
        OEDQ_01 = $time;
2784
    end
2785
    always @(posedge BuffOutCE)
2786
    begin
2787
        CEDQ_01 = $time;
2788
    end
2789
    always @(posedge BuffOutADDR)
2790
    begin
2791
        ADDRDQ_01 = $time;
2792
    end
2793
 
2794
    function integer sa;
2795
    input [7:0] sect;
2796
    begin
2797
        sa = sect * (SecSize + 1);
2798
    end
2799
    endfunction
2800
 
2801
    task MemRead;
2802
    inout[7:0]  DOut_zd;
2803
    begin
2804
        if (Mem[sa(SecAddr)+Address]==-1)
2805
            DOut_zd = 8'bx;
2806
        else
2807
            DOut_zd = Mem[sa(SecAddr)+Address];
2808
    end
2809
    endtask
2810
endmodule
2811
 
2812
module BUFFER (OUT,IN);
2813
    input IN;
2814
    output OUT;
2815
    buf   ( OUT, IN);
2816
endmodule

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