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[/] [or1k/] [trunk/] [gcc/] [gcc-3.4.4/] [gcc-3.4.4-or32-unified.diff] - Blame information for rev 1765

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Line No. Rev Author Line
1 1639 rezso
diff -Nru gcc-3.4.4.orig/config.sub gcc-3.4.4-DONE/config.sub
2
--- gcc-3.4.4.orig/config.sub   2004-02-22 16:44:23.000000000 +0200
3
+++ gcc-3.4.4-DONE/config.sub   2005-12-13 17:38:35.000000000 +0200
4
@@ -256,7 +256,7 @@
5
        | mn10200 | mn10300 \
6
        | msp430 \
7
        | ns16k | ns32k \
8
-       | openrisc | or32 \
9
+       | or32 \
10
        | pdp10 | pdp11 | pj | pjl \
11
        | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
12
        | pyramid \
13
@@ -750,9 +750,8 @@
14
                basic_machine=hppa1.1-oki
15
                os=-proelf
16
                ;;
17
-       or32 | or32-*)
18
-               basic_machine=or32-unknown
19
-               os=-coff
20
+       or32 | or32-*)
21
+               basic_machine=or32-`echo $basic_machine | sed 's/^[^-]*-//'`
22
                ;;
23
        os400)
24
                basic_machine=powerpc-ibm
25
@@ -1355,8 +1354,8 @@
26
        mips*-*)
27
                os=-elf
28
                ;;
29
-       or32-*)
30
-               os=-coff
31
+       or32-*)
32
+               os=-elf
33
                ;;
34
        *-tti)  # must be before sparc entry or we get the wrong os.
35
                os=-sysv3
36
diff -Nru gcc-3.4.4.orig/configure.in gcc-3.4.4-DONE/configure.in
37
--- gcc-3.4.4.orig/configure.in 2005-03-08 19:31:40.000000000 +0200
38
+++ gcc-3.4.4-DONE/configure.in 2005-12-13 17:38:35.000000000 +0200
39
@@ -608,6 +608,9 @@
40
   mn10300-*-*)
41
     noconfigdirs="$noconfigdirs ${libgcj}"
42
     ;;
43
+  or32-*-*)
44
+    noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
45
+    ;;
46
   powerpc-*-aix*)
47
     # copied from rs6000-*-* entry
48
     noconfigdirs="$noconfigdirs gprof target-libgloss ${libgcj}"
49
diff -Nru gcc-3.4.4.orig/gcc/config/or32/default.h gcc-3.4.4-DONE/gcc/config/or32/default.h
50
--- gcc-3.4.4.orig/gcc/config/or32/default.h    1970-01-01 02:00:00.000000000 +0200
51
+++ gcc-3.4.4-DONE/gcc/config/or32/default.h    2005-11-29 16:23:09.000000000 +0200
52
@@ -0,0 +1,74 @@
53
+/* Definitions of target machine for GNU compiler for OR1K running Linux.
54
+   (Actually OR1K is not yet running Linux but eventually it will).
55
+   Copyright (C) 1996, 1997, 1998, 2005 Free Software Foundation, Inc.
56
+   Contributed by Damjan Lampret <damjanl@bsemi.com> in 1999.
57
+   Based upon the rs6000 port.
58
+
59
+This file is part of GNU CC.
60
+
61
+GNU CC is free software; you can redistribute it and/or modify
62
+it under the terms of the GNU General Public License as published by
63
+the Free Software Foundation; either version 2, or (at your option)
64
+any later version.
65
+
66
+GNU CC is distributed in the hope that it will be useful,
67
+but WITHOUT ANY WARRANTY; without even the implied warranty of
68
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
69
+GNU General Public License for more details.
70
+
71
+You should have received a copy of the GNU General Public License
72
+along with GNU CC; see the file COPYING.  If not, write to
73
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
74
+
75
+#undef CPP_PREDEFINES
76
+#define CPP_PREDEFINES \
77
+ "-DOR1K -D__or1k__ -D__OR1K__ -D__ELF__ -Dunix -Dlinux -Dor1k -Asystem(unix) -Asystem(linux) -Acpu(or1k) -Amachine(or1k)"
78
+
79
+#undef CPP_OS_DEFAULT_SPEC
80
+#define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
81
+
82
+#undef LINK_SPEC
83
+#define LINK_SPEC "-m elf32or32 %{G*} %{shared:-shared} \
84
+  %{!shared: \
85
+    %{!static: \
86
+      %{rdynamic:-export-dynamic} \
87
+      %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \
88
+    %{static:-static}}"
89
+
90
+#undef LIB_DEFAULT_SPEC
91
+#define LIB_DEFAULT_SPEC "%(lib_linux)"
92
+
93
+#undef STARTFILE_DEFAULT_SPEC
94
+#define STARTFILE_DEFAULT_SPEC "%(startfile_linux)"
95
+
96
+#undef ENDFILE_DEFAULT_SPEC
97
+#define ENDFILE_DEFAULT_SPEC "%(endfile_linux)"
98
+
99
+#undef LINK_START_DEFAULT_SPEC
100
+#define LINK_START_DEFAULT_SPEC "%(link_start_linux)"
101
+
102
+#undef LINK_OS_DEFAULT_SPEC
103
+#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
104
+
105
+#undef TARGET_VERSION
106
+#define TARGET_VERSION fprintf (stderr, " (OpenRISC 1000 GNU/Linux)");
107
+
108
+/* Define this macro as a C expression for the initializer of an
109
+   array of string to tell the driver program which options are
110
+   defaults for this target and thus do not need to be handled
111
+   specially when using `MULTILIB_OPTIONS'.
112
+
113
+   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
114
+   the target makefile fragment or if none of the options listed in
115
+   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
116
+
117
+#undef MULTILIB_DEFAULTS
118
+#define        MULTILIB_DEFAULTS { "mbig", "mcall-linux" }
119
+
120
+#undef DEFAULT_VTABLE_THUNKS
121
+#ifndef USE_GNULIBC_1
122
+#define DEFAULT_VTABLE_THUNKS 1
123
+#endif
124
+
125
+#undef JUMP_TABLES_IN_TEXT_SECTION
126
+#define JUMP_TABLES_IN_TEXT_SECTION 0
127
diff -Nru gcc-3.4.4.orig/gcc/config/or32/elf.h gcc-3.4.4-DONE/gcc/config/or32/elf.h
128
--- gcc-3.4.4.orig/gcc/config/or32/elf.h        1970-01-01 02:00:00.000000000 +0200
129
+++ gcc-3.4.4-DONE/gcc/config/or32/elf.h        2005-11-29 16:23:09.000000000 +0200
130
@@ -0,0 +1,45 @@
131
+/* Definitions for rtems targeting an OpenRisc OR32 using COFF
132
+   Copyright (C) 1996, 1997, 2005 Free Software Foundation, Inc.
133
+   Contributed by Joel Sherrill (joel@OARcorp.com).
134
+
135
+This file is part of GNU CC.
136
+
137
+GNU CC is free software; you can redistribute it and/or modify
138
+it under the terms of the GNU General Public License as published by
139
+the Free Software Foundation; either version 2, or (at your option)
140
+any later version.
141
+
142
+GNU CC is distributed in the hope that it will be useful,
143
+but WITHOUT ANY WARRANTY; without even the implied warranty of
144
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145
+GNU General Public License for more details.
146
+
147
+You should have received a copy of the GNU General Public License
148
+along with GNU CC; see the file COPYING.  If not, write to
149
+the Free Software Foundation, 59 Temple Place - Suite 330,
150
+Boston, MA 02111-1307, USA.  */
151
+
152
+#undef  TARGET_VERSION
153
+#define TARGET_VERSION  fputs (" (OR32/ELF)", stderr);
154
+
155
+/* Use ELF */
156
+#undef  OBJECT_FORMAT_ELF
157
+#define OBJECT_FORMAT_ELF
158
+
159
+/* use SDB debugging info and make it default */
160
+#undef  DBX_DEBUGGING_INFO
161
+#define DBX_DEBUGGING_INFO
162
+
163
+#undef  PREFERRED_DEBUGGING_TYPE
164
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
165
+
166
+#undef  PUT_SDB_DEF
167
+#define PUT_SDB_DEF
168
+
169
+/* Generate calls to memcpy, memcmp and memset.  */
170
+#ifndef TARGET_MEM_FUNCTIONS
171
+#  define TARGET_MEM_FUNCTIONS
172
+#endif
173
+
174
+#undef  USER_LABEL_PREFIX
175
+#define USER_LABEL_PREFIX "_"
176
diff -Nru gcc-3.4.4.orig/gcc/config/or32/linux-elf.h gcc-3.4.4-DONE/gcc/config/or32/linux-elf.h
177
--- gcc-3.4.4.orig/gcc/config/or32/linux-elf.h  1970-01-01 02:00:00.000000000 +0200
178
+++ gcc-3.4.4-DONE/gcc/config/or32/linux-elf.h  2005-11-29 16:23:09.000000000 +0200
179
@@ -0,0 +1,65 @@
180
+/* Definitions for or32 running Linux-based GNU systems using ELF
181
+   Copyright (C) 2002, 2005
182
+   Free Software Foundation, Inc.
183
+   Contributed by Marko Mlinar <markom@opencores.org>
184
+
185
+This file is part of GNU CC.
186
+
187
+GNU CC is free software; you can redistribute it and/or modify
188
+it under the terms of the GNU General Public License as published by
189
+the Free Software Foundation; either version 2, or (at your option)
190
+any later version.
191
+
192
+GNU CC is distributed in the hope that it will be useful,
193
+but WITHOUT ANY WARRANTY; without even the implied warranty of
194
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
195
+GNU General Public License for more details.
196
+
197
+You should have received a copy of the GNU General Public License
198
+along with this program; see the file COPYING.  If not, write to
199
+the Free Software Foundation, 59 Temple Place - Suite 330,
200
+Boston, MA 02111-1307, USA.  */
201
+
202
+/* elfos.h should have already been included.  Now just override
203
+   any conflicting definitions and add any extras.  */
204
+
205
+/* Run-time Target Specification.  */
206
+#undef  TARGET_VERSION
207
+#define TARGET_VERSION  fputs (" (OR32 GNU/Linux with ELF)", stderr);
208
+
209
+/* Do not assume anything about header files.  */
210
+#define NO_IMPLICIT_EXTERN_C
211
+
212
+#undef  USER_LABEL_PREFIX
213
+#define USER_LABEL_PREFIX "_"
214
+
215
+
216
+/* This is how we tell the assembler that two symbols have the same value.  */
217
+#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \
218
+  do                                       \
219
+    {                                      \
220
+      assemble_name (FILE, NAME1);         \
221
+      fputs (" = ", FILE);                 \
222
+      assemble_name (FILE, NAME2);         \
223
+      fputc ('\n', FILE);                  \
224
+    }                                      \
225
+    while (0)
226
+
227
+
228
+#if 0
229
+/* Node: Label Output */
230
+
231
+#define SET_ASM_OP      "\t.set\t"
232
+
233
+#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)  \
234
+  (*targetm.asm_out.globalize_label) (FILE, XSTR (FUN, 0))
235
+
236
+#define ASM_WEAKEN_LABEL(FILE, NAME)    \
237
+  do                                    \
238
+    {                                   \
239
+      fputs ("\t.weak\t", (FILE));      \
240
+      assemble_name ((FILE), (NAME));   \
241
+      fputc ('\n', (FILE));             \
242
+    }                                   \
243
+  while (0)
244
+#endif
245
diff -Nru gcc-3.4.4.orig/gcc/config/or32/linux-gas.h gcc-3.4.4-DONE/gcc/config/or32/linux-gas.h
246
--- gcc-3.4.4.orig/gcc/config/or32/linux-gas.h  1970-01-01 02:00:00.000000000 +0200
247
+++ gcc-3.4.4-DONE/gcc/config/or32/linux-gas.h  2005-11-29 16:23:09.000000000 +0200
248
@@ -0,0 +1,37 @@
249
+/* Definitions of target machine for GNU compiler.
250
+   Or32 Linux-based GNU systems version.
251
+   Copyright (C) 2002, 2005 Free Software Foundation, Inc.
252
+   Contributed by Marko Mlinar <markom@opencores.org>
253
+
254
+This file is part of GNU CC.
255
+
256
+GNU CC is free software; you can redistribute it and/or modify
257
+it under the terms of the GNU General Public License as published by
258
+the Free Software Foundation; either version 2, or (at your option)
259
+any later version.
260
+
261
+GNU CC is distributed in the hope that it will be useful,
262
+but WITHOUT ANY WARRANTY; without even the implied warranty of
263
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
264
+GNU General Public License for more details.
265
+
266
+You should have received a copy of the GNU General Public License
267
+along with this program; see the file COPYING.  If not, write to
268
+the Free Software Foundation, 59 Temple Place - Suite 330,
269
+Boston, MA 02111-1307, USA.  */
270
+
271
+/* Unsigned chars produces much better code than signed.  */
272
+#undef  DEFAULT_SIGNED_CHAR
273
+#define DEFAULT_SIGNED_CHAR 1
274
+
275
+/* Make gcc agree with <machine/ansi.h> */
276
+
277
+#define SIZE_TYPE "unsigned int"
278
+#define PTRDIFF_TYPE "int"
279
+#define WCHAR_TYPE "unsigned int"
280
+#define WCHAR_TYPE_SIZE 32
281
+
282
+
283
+/* Clear the instruction cache from `beg' to `end'.  This makes an
284
+   inline system call to SYS_cacheflush.  */
285
+#define CLEAR_INSN_CACHE(BEG, END) /* Do something here !!! */
286
diff -Nru gcc-3.4.4.orig/gcc/config/or32/or32.c gcc-3.4.4-DONE/gcc/config/or32/or32.c
287
--- gcc-3.4.4.orig/gcc/config/or32/or32.c       1970-01-01 02:00:00.000000000 +0200
288
+++ gcc-3.4.4-DONE/gcc/config/or32/or32.c       2005-11-29 16:23:09.000000000 +0200
289
@@ -0,0 +1,1260 @@
290
+/* Subroutines for insn-output.c for GNU compiler.  OpenRISC 1000 version.
291
+   Copyright (C) 1987, 1992, 1997, 1999, 2000, 2001, 2002, 2003, 2004,
292
+   2005  Free Software Foundation, Inc
293
+   Contributed by Damjan Lampret <damjanl@bsemi.com> in 1999.
294
+   Major optimizations by Matjaz Breskvar <matjazb@bsemi.com> in 2005.
295
+
296
+This file is part of GNU CC.
297
+
298
+GNU CC is free software; you can redistribute it and/or modify
299
+it under the terms of the GNU General Public License as published by
300
+the Free Software Foundation; either version 1, or (at your option)
301
+any later version.
302
+
303
+GNU CC is distributed in the hope that it will be useful,
304
+but WITHOUT ANY WARRANTY; without even the implied warranty of
305
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
306
+GNU General Public License for more details.
307
+
308
+You should have received a copy of the GNU General Public License
309
+along with GNU CC; see the file COPYING.  If not, write to
310
+the Free Software Foundation, 59 Temple Place - Suite 330,
311
+Boston, MA 02111-1307, USA.  */
312
+
313
+#include "config.h"
314
+#include "system.h"
315
+#include "coretypes.h"
316
+#include "tm.h"
317
+#include "rtl.h"
318
+#include "regs.h"
319
+#include "hard-reg-set.h"
320
+#include "real.h"
321
+#include "insn-config.h"
322
+#include "conditions.h"
323
+#include "insn-attr.h"
324
+#include "flags.h"
325
+#include "tree.h"
326
+#include "expr.h"
327
+#include "except.h"
328
+#include "function.h"
329
+#include "toplev.h"
330
+#include "recog.h"
331
+#include "tm_p.h"
332
+#include "debug.h"
333
+#include "output.h"
334
+#include "target.h"
335
+#include "target-def.h"
336
+#include "ggc.h"
337
+#include "optabs.h"
338
+
339
+/* Set thist to nonzero if you want l.nop instruction in delay slot
340
+   of l.jr instruction in epilogue. */
341
+#define  NOP_DELAY_SLOT_FILL 0
342
+
343
+/* This is the pseudo register number that holds the comparison flags */
344
+
345
+#define FLAGS_REG 32
346
+
347
+/* Save information from a "cmpxx" operation until the branch or scc is
348
+   emitted.  */
349
+rtx or32_compare_op0, or32_compare_op1;
350
+
351
+/* used in function prologue/epilogue generation */
352
+extern int leaf_function;
353
+
354
+/* Local function prototypes */
355
+static void or32_output_function_prologue (FILE * file, HOST_WIDE_INT vars);
356
+static void or32_output_function_epilogue (FILE * file, HOST_WIDE_INT vars);
357
+static bool or32_save_reg_p (int regno);
358
+HOST_WIDE_INT or32_compute_frame_size (HOST_WIDE_INT size);
359
+static rtx emit_frame_insn (rtx insn);
360
+static rtx indexed_memory (rtx base, HOST_WIDE_INT disp);
361
+void or32_expand_prologue (void);
362
+void or32_expand_epilogue (int sibcall);
363
+const char *or32_output_move_double (rtx * operands);
364
+enum rtx_code or32_reverse_condition (enum machine_mode mode,
365
+                                     enum rtx_code code);
366
+enum machine_mode or32_cc_mode (enum rtx_code code, rtx op0, rtx op1);
367
+rtx or32_expand_compare (enum rtx_code code, rtx op0, rtx op1);
368
+void or32_expand_branch (enum rtx_code code, rtx label);
369
+static int or32_emit_int_cmove (rtx dest, rtx op, rtx true_cond,
370
+                               rtx false_cond);
371
+int or32_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond);
372
+const char *output_cmov (rtx * operands);
373
+const char *output_bf (rtx * operands);
374
+void or32_emit_set_const32 (rtx op0, rtx op1);
375
+int or32_register_move_cost (enum machine_mode mode, enum reg_class from,
376
+                            enum reg_class to);
377
+int or32_memory_move_cost (enum machine_mode mode, enum reg_class class,
378
+                          int in);
379
+int or32_branch_cost ();
380
+
381
+
382
+#undef TARGET_ASM_FUNCTION_PROLOGUE
383
+#define TARGET_ASM_FUNCTION_PROLOGUE or32_output_function_prologue
384
+#undef TARGET_ASM_FUNCTION_EPILOGUE
385
+#define TARGET_ASM_FUNCTION_EPILOGUE or32_output_function_epilogue
386
+
387
+static bool or32_function_ok_for_sibcall (tree decl, tree exp);
388
+
389
+#undef TARGET_FUNCTION_OK_FOR_SIBCALL
390
+#define TARGET_FUNCTION_OK_FOR_SIBCALL or32_function_ok_for_sibcall
391
+
392
+
393
+/* Initialize the GCC target structure.  */
394
+struct gcc_target targetm = TARGET_INITIALIZER;
395
+
396
+/* Stack layout we use for pushing and poping saved registers */
397
+struct or32_frame_info
398
+{
399
+  bool save_lr_p;
400
+  int lr_save_offset;
401
+  bool save_fp_p;
402
+  int fp_save_offset;
403
+  int gpr_size;
404
+  int gpr_offset;
405
+  int total_size;
406
+  int vars_size;
407
+  int args_size;
408
+  HOST_WIDE_INT mask;
409
+};
410
+
411
+static struct or32_frame_info frame_info;
412
+
413
+/* Returns 1 if OP is either a pseudo-register or a register denoting a
414
+   CR field.  */
415
+
416
+int
417
+cc_reg_operand (rtx op, enum machine_mode mode)
418
+{
419
+  register_operand (op, mode);
420
+
421
+  if (GET_CODE (op) == REG && REGNO (op) == 32)
422
+    return 1;
423
+
424
+  return 0;
425
+}
426
+
427
+int
428
+sym_ref_mem_operand (op, mode)
429
+     register rtx op;
430
+     enum machine_mode mode ATTRIBUTE_UNUSED;
431
+{
432
+  if (GET_CODE (op) == MEM)
433
+    {
434
+      rtx t1 = XEXP (op, 0);
435
+      if (GET_CODE (t1) == SYMBOL_REF)
436
+       return 1;
437
+    }
438
+  return 0;
439
+}
440
+
441
+/* Return 1 if OP is a valid operand for the source of a move insn.  */
442
+
443
+int
444
+input_operand (rtx op, enum machine_mode mode)
445
+{
446
+
447
+  /* If both modes are non-void they must be the same.  */
448
+  if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
449
+    return 0;
450
+
451
+  /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1.  */
452
+  if (GET_CODE (op) == CONSTANT_P_RTX)
453
+    return 1;
454
+
455
+  /* Allow any one instruction integer constant, and all CONST_INT
456
+     variants when we are working in DImode and !arch64.  */
457
+  if (GET_MODE_CLASS (mode) == MODE_INT
458
+      && ((GET_CODE (op) == CONST_INT)
459
+         && (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
460
+             || CONST_OK_FOR_LETTER_P (INTVAL (op), 'M')
461
+             || CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))))
462
+    return 1;
463
+
464
+  if (register_operand (op, mode))
465
+    return 1;
466
+
467
+  /* If this is a SUBREG, look inside so that we handle
468
+     paradoxical ones.  */
469
+  if (GET_CODE (op) == SUBREG)
470
+    op = SUBREG_REG (op);
471
+
472
+
473
+  /* Check for valid MEM forms.  */
474
+  if (GET_CODE (op) == MEM)
475
+    return memory_address_p (mode, XEXP (op, 0));
476
+
477
+  return 0;
478
+}
479
+
480
+/* Test for a valid operand for a call instruction.  Don't allow the
481
+   arg pointer register or virtual regs since they may decay into
482
+   reg + const, which the patterns can't handle.  */
483
+
484
+int
485
+sibcall_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
486
+{
487
+
488
+
489
+  /* Disallow indirect through a virtual register.  This leads to
490
+     compiler aborts when trying to eliminate them.  */
491
+  if (GET_CODE (op) == REG
492
+      && (op == arg_pointer_rtx
493
+         || op == frame_pointer_rtx
494
+         || (REGNO (op) >= FIRST_PSEUDO_REGISTER
495
+             && REGNO (op) <= LAST_VIRTUAL_REGISTER)))
496
+    {
497
+
498
+      fprintf (stderr, "0\n");
499
+      return 0;
500
+    }
501
+
502
+  /* Explicitly allow SYMBOL_REF even if pic.  */
503
+  if (GET_CODE (op) == SYMBOL_REF)
504
+    return 1;
505
+
506
+  /* Otherwise we can only allow register operands.  */
507
+  return register_operand (op, Pmode);
508
+}
509
+
510
+
511
+/* Add a REG_MAYBE_DEAD note to the insn.  */
512
+static void
513
+or32_maybe_dead (rtx insn)
514
+{
515
+  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
516
+                                       const0_rtx, REG_NOTES (insn));
517
+}
518
+
519
+int
520
+print_operand_punct_valid_p (code)
521
+     int code;
522
+{
523
+  switch (code)
524
+    {
525
+    case '(':                  /* idea taken from sparc; output nop for %( if
526
+                                  not optimizing or the slot is not filled. */
527
+    case '%':
528
+      return 1;
529
+    }
530
+  return 0;
531
+}
532
+
533
+void
534
+print_operand_address (file, addr)
535
+     FILE *file;
536
+     register rtx addr;
537
+{
538
+  register rtx reg1, reg2, breg, ireg;
539
+  rtx offset;
540
+
541
+  switch (GET_CODE (addr))
542
+    {
543
+    case MEM:
544
+      if (GET_CODE (XEXP (addr, 0)) == REG)
545
+       fprintf (file, "%s", reg_names[REGNO (addr)]);
546
+      else
547
+       abort ();
548
+      break;
549
+
550
+    case REG:
551
+      fprintf (file, "0(%s)", reg_names[REGNO (addr)]);
552
+      break;
553
+
554
+    case PLUS:
555
+      reg1 = 0;
556
+      reg2 = 0;
557
+      ireg = 0;
558
+      breg = 0;
559
+      offset = 0;
560
+      if (GET_CODE (XEXP (addr, 0)) == REG)
561
+       {
562
+         offset = XEXP (addr, 1);
563
+         addr = XEXP (addr, 0);
564
+       }
565
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
566
+       {
567
+         offset = XEXP (addr, 0);
568
+         addr = XEXP (addr, 1);
569
+       }
570
+      output_address (offset);
571
+      fprintf (file, "(%s)", reg_names[REGNO (addr)]);
572
+      break;
573
+
574
+    default:
575
+      /* fprintf(file, "{%d}", GET_CODE (addr)); */
576
+      output_addr_const (file, addr);
577
+    }
578
+}
579
+
580
+/* Calulcate and return stack size for current function.  */
581
+static int
582
+calculate_stack_size (int vars, int *lr_save_area,
583
+                     int *fp_save_area, int *gpr_save_area, int *save_area)
584
+{
585
+  int regno;
586
+
587
+  *gpr_save_area = 0;
588
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
589
+    {
590
+      if (regs_ever_live[regno] && !call_used_regs[regno])
591
+       *gpr_save_area += 4;
592
+    }
593
+
594
+  *lr_save_area = (!current_function_is_leaf
595
+                  || regs_ever_live[LINK_REGNUM]) ? 4 : 0;
596
+  *fp_save_area = frame_pointer_needed ? 4 : 0;
597
+
598
+  *save_area = (OR32_ALIGN (current_function_outgoing_args_size, 4)
599
+               + *lr_save_area + *fp_save_area);
600
+
601
+  return
602
+    (OR32_ALIGN (current_function_outgoing_args_size, 4)
603
+     + *lr_save_area + *fp_save_area + *gpr_save_area + OR32_ALIGN (vars, 4));
604
+}
605
+
606
+/* Set up the stack and frame pointer (if desired) for the
607
+   function.  */
608
+static void
609
+or32_output_function_prologue (FILE * file, HOST_WIDE_INT vars)
610
+{
611
+  int save_area;
612
+  int gpr_save_area;
613
+  int lr_save_area;
614
+  int fp_save_area;
615
+  int stack_size;
616
+  int regno;
617
+
618
+  if (TARGET_SCHED_LOGUE)
619
+    return;
620
+
621
+#if 0
622
+  save_area = 0;
623
+
624
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
625
+    {
626
+      if (regs_ever_live[regno] && !call_used_regs[regno])
627
+       {
628
+         save_area += 1;
629
+       }
630
+    }
631
+
632
+  if (save_area != 0)
633
+    fprintf (file, "\tl.nop \t0x%x\n", 0x100 + save_area);
634
+
635
+  return;
636
+#endif
637
+
638
+  if (vars < 0)
639
+    abort ();
640
+
641
+  stack_size = calculate_stack_size
642
+    (vars, &lr_save_area, &fp_save_area, &gpr_save_area, &save_area);
643
+
644
+  fprintf (file,
645
+          "\n\t# gpr_save_area %d vars %ld current_function_outgoing_args_size %d\n",
646
+          gpr_save_area, vars, current_function_outgoing_args_size);
647
+
648
+  if (stack_size >= 0x8000)
649
+    {
650
+      fprintf (file, "\tl.movhi   \tr%d,hi(%d)\n", GP_ARG_RETURN, stack_size);
651
+      fprintf (file, "\tl.ori   \tr%d,r%d,lo(%d)\n", GP_ARG_RETURN,
652
+              GP_ARG_RETURN, stack_size);
653
+      fprintf (file, "\tl.sub   \tr%d,r%d,r%d\n", STACK_POINTER_REGNUM,
654
+              STACK_POINTER_REGNUM, GP_ARG_RETURN);
655
+    }
656
+  else if (stack_size > 0)
657
+    {
658
+      fprintf (file, "\tl.addi   \tr%d,r%d,%d\n", STACK_POINTER_REGNUM,
659
+              STACK_POINTER_REGNUM, -stack_size);
660
+    }
661
+
662
+  if (fp_save_area)
663
+    {
664
+      fprintf (file, "\tl.sw     \t%d(r%d),r%d\n",
665
+              OR32_ALIGN (current_function_outgoing_args_size, 4)
666
+              + lr_save_area, STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM);
667
+      if (stack_size >= 0x8000)
668
+       fprintf (file, "\tl.add   \tr%d,r%d,r%d\n", FRAME_POINTER_REGNUM,
669
+                STACK_POINTER_REGNUM, GP_ARG_RETURN);
670
+      else
671
+       fprintf (file, "\tl.addi   \tr%d,r%d,%d\n", FRAME_POINTER_REGNUM,
672
+                STACK_POINTER_REGNUM, stack_size);
673
+    }
674
+
675
+  if (lr_save_area)
676
+    {
677
+      fprintf (file, "\tl.sw     \t%d(r%d),r%d\n",
678
+              OR32_ALIGN (current_function_outgoing_args_size, 4),
679
+              STACK_POINTER_REGNUM, LINK_REGNUM);
680
+    }
681
+
682
+  save_area = (OR32_ALIGN (current_function_outgoing_args_size, 4)
683
+              + lr_save_area + fp_save_area);
684
+
685
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
686
+    {
687
+      if (regs_ever_live[regno] && !call_used_regs[regno])
688
+       {
689
+         fprintf (file, "\tl.sw    \t%d(r%d),r%d\n", save_area,
690
+                  STACK_POINTER_REGNUM, regno);
691
+         save_area += 4;
692
+       }
693
+    }
694
+}
695
+
696
+/* Do any necessary cleanup after a function to restore stack, frame,
697
+   and regs.  */
698
+static void
699
+or32_output_function_epilogue (FILE * file, HOST_WIDE_INT vars)
700
+{
701
+  int save_area;
702
+  int gpr_save_area;
703
+  int lr_save_area;
704
+  int fp_save_area;
705
+  int stack_size;
706
+  int regno;
707
+
708
+  if (TARGET_SCHED_LOGUE)
709
+    return;
710
+
711
+#if 0
712
+  save_area = 0;
713
+
714
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
715
+    {
716
+      if (regs_ever_live[regno] && !call_used_regs[regno])
717
+       {
718
+         save_area += 1;
719
+       }
720
+    }
721
+
722
+  fprintf (file, "\tl.nop \t0x%x\n", 0x200 + save_area);
723
+  return;
724
+#endif
725
+
726
+  stack_size = calculate_stack_size
727
+    (vars, &lr_save_area, &fp_save_area, &gpr_save_area, &save_area);
728
+
729
+  if (lr_save_area)
730
+    {
731
+      fprintf (file, "\tl.lwz    \tr%d,%d(r%d)\n", LINK_REGNUM,
732
+              OR32_ALIGN (current_function_outgoing_args_size, 4),
733
+              STACK_POINTER_REGNUM);
734
+    }
735
+  if (fp_save_area)
736
+    {
737
+      fprintf (file, "\tl.lwz    \tr%d,%d(r%d)\n", FRAME_POINTER_REGNUM,
738
+              OR32_ALIGN (current_function_outgoing_args_size, 4)
739
+              + lr_save_area, STACK_POINTER_REGNUM);
740
+    }
741
+  save_area = (OR32_ALIGN (current_function_outgoing_args_size, 4)
742
+              + lr_save_area + fp_save_area);
743
+
744
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
745
+    {
746
+      if (regs_ever_live[regno] && !call_used_regs[regno])
747
+       {
748
+         fprintf (file, "\tl.lwz    \tr%d,%d(r%d)\n", regno, save_area,
749
+                  STACK_POINTER_REGNUM);
750
+         save_area += 4;
751
+       }
752
+    }
753
+
754
+  if (stack_size >= 0x8000)
755
+    {
756
+      fprintf (file, "\tl.movhi   \tr3,hi(%d)\n", stack_size);
757
+      fprintf (file, "\tl.ori   \tr3,r3,lo(%d)\n", stack_size);
758
+
759
+      if (!TARGET_ALIGNED_JUMPS)
760
+       fprintf (file, "\tl.jr  \tr%d\n", LINK_REGNUM);
761
+      else
762
+       fprintf (file, "\t.balignl 0x8,0x15000015,0x4;l.jr  \tr%d\n",
763
+                LINK_REGNUM);
764
+
765
+      fprintf (file, "\tl.add   \tr%d,r%d,r3\n", STACK_POINTER_REGNUM,
766
+              STACK_POINTER_REGNUM);
767
+    }
768
+  else if (stack_size > 0)
769
+    {
770
+      if (!TARGET_ALIGNED_JUMPS)
771
+       fprintf (file, "\tl.jr  \tr%d\n", LINK_REGNUM);
772
+      else
773
+       fprintf (file, "\t.balignl 0x8,0x15000015,0x4;l.jr  \tr%d\n",
774
+                LINK_REGNUM);
775
+
776
+      fprintf (file, "\tl.addi   \tr%d,r%d,%d\n", STACK_POINTER_REGNUM,
777
+              STACK_POINTER_REGNUM, stack_size);
778
+    }
779
+  else
780
+    {
781
+      if (!TARGET_ALIGNED_JUMPS)
782
+       fprintf (file, "\tl.jr  \tr%d\n", LINK_REGNUM);
783
+      else
784
+       fprintf (file, "\t.balignl 0x8,0x15000015,0x4;l.jr  \tr%d\n",
785
+                LINK_REGNUM);
786
+
787
+      fprintf (file, "\tl.nop\n");
788
+    }
789
+
790
+#if 0
791
+  fprintf (file, ".endproc _%s\n", get_function_name ());
792
+#endif
793
+}
794
+
795
+/* Compuate full frame size and layout.  SIZE is the size of the
796
+   functions local variables.  Store information in FRAME_INFO and
797
+   return total size of stack frame.  */
798
+
799
+HOST_WIDE_INT
800
+or32_compute_frame_size (HOST_WIDE_INT size)
801
+{
802
+  HOST_WIDE_INT args_size;
803
+  HOST_WIDE_INT vars_size;
804
+  HOST_WIDE_INT stack_offset;
805
+  int regno;
806
+
807
+  args_size = current_function_outgoing_args_size;
808
+  vars_size = OR32_ALIGN (size, 4);
809
+
810
+  frame_info.args_size = args_size;
811
+  frame_info.vars_size = vars_size;
812
+
813
+  /* If the function has local variables, we're committed to
814
+     allocating it anyway.  Otherwise reclaim it here.  */
815
+  /* FIXME: Verify this.  Got if from the MIPS port.  */
816
+  if (vars_size == 0 && current_function_is_leaf)
817
+    args_size = 0;
818
+
819
+  stack_offset = args_size;
820
+
821
+  /* Save link register right after possible outgoing arguments.  */
822
+  if (or32_save_reg_p (LINK_REGNUM))
823
+    {
824
+      frame_info.lr_save_offset = stack_offset;
825
+      frame_info.save_lr_p = true;
826
+      stack_offset = stack_offset + UNITS_PER_WORD;
827
+    }
828
+  else
829
+    frame_info.save_lr_p = false;
830
+
831
+  /* Save frame pointer right after possible link register.  */
832
+  if (or32_save_reg_p (FRAME_POINTER_REGNUM))
833
+    {
834
+      frame_info.fp_save_offset = stack_offset;
835
+      frame_info.save_fp_p = true;
836
+      stack_offset = stack_offset + UNITS_PER_WORD;
837
+    }
838
+  else
839
+    frame_info.save_fp_p = false;
840
+
841
+  frame_info.gpr_size = 0;
842
+  frame_info.mask = 0;
843
+  frame_info.gpr_offset = stack_offset;
844
+
845
+  for (regno = 0; regno <= LAST_INT_REG; regno++)
846
+    {
847
+      if (regno == LINK_REGNUM || regno == FRAME_POINTER_REGNUM)
848
+       /* These has already been saved if so needed.  */
849
+       continue;
850
+
851
+      if (or32_save_reg_p (regno))
852
+       {
853
+         frame_info.gpr_size += UNITS_PER_WORD;
854
+         frame_info.mask |= (1 << regno);
855
+       }
856
+    }
857
+
858
+  frame_info.total_size = ((frame_info.save_fp_p ? UNITS_PER_WORD : 0)
859
+                          + (frame_info.save_lr_p ? UNITS_PER_WORD : 0)
860
+                          + args_size + frame_info.gpr_size + vars_size);
861
+
862
+  return frame_info.total_size;
863
+}
864
+
865
+
866
+/* Return true if current function must save REGNO.  */
867
+static bool
868
+or32_save_reg_p (int regno)
869
+{
870
+  /* No need to save the faked cc0 register.  */
871
+  if (regno == FLAGS_REG)
872
+    return false;
873
+
874
+  /* Check call-saved registers.  */
875
+  if (regs_ever_live[regno] && !call_used_regs[regno])
876
+    return true;
877
+
878
+  /* We need to save the old frame pointer before setting up a new
879
+     one.  */
880
+  if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
881
+    return true;
882
+
883
+  /* We need to save the incoming return address if it is ever clobbered
884
+     within the function.  */
885
+  if (regno == LINK_REGNUM && regs_ever_live[regno])
886
+    return true;
887
+
888
+  return false;
889
+}
890
+
891
+/* Emit a frame related insn.  Same as emit_insn, but sets
892
+   RTX_FRAME_RELATED_P to one.  */
893
+
894
+static rtx
895
+emit_frame_insn (rtx insn)
896
+{
897
+  insn = emit_insn (insn);
898
+  RTX_FRAME_RELATED_P (insn) = 1;
899
+  return (insn);
900
+}
901
+
902
+static rtx
903
+indexed_memory (rtx base, HOST_WIDE_INT disp)
904
+{
905
+  return gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, GEN_INT (disp)));
906
+}
907
+
908
+/* Called after register allocation to add any instructions needed for
909
+   the prologue.  Using a prologue insn is favored compared to putting
910
+   all of the instructions in output_function_prologue(), since it
911
+   allows the scheduler to intermix instructions with the saves of the
912
+   caller saved registers.  In some cases, it might be necessary to
913
+   emit a barrier instruction as the last insn to prevent such
914
+   scheduling.  */
915
+
916
+void
917
+or32_expand_prologue ()
918
+{
919
+  int total_size = or32_compute_frame_size (get_frame_size ());
920
+  rtx sp_rtx;
921
+  rtx value_rtx;
922
+
923
+  if (!total_size)
924
+    /* No frame needed.  */
925
+    return;
926
+
927
+  sp_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
928
+
929
+  if (total_size > 32767)
930
+    {
931
+      value_rtx = gen_rtx_REG (Pmode, GP_ARG_RETURN);
932
+      emit_frame_insn (gen_rtx_SET (Pmode, value_rtx, GEN_INT (total_size)));
933
+    }
934
+  else
935
+    value_rtx = GEN_INT (total_size);
936
+
937
+  /* Update the stack pointer to reflect frame size.  */
938
+  emit_frame_insn
939
+    (gen_rtx_SET (Pmode, stack_pointer_rtx,
940
+                 gen_rtx_MINUS (Pmode, stack_pointer_rtx, value_rtx)));
941
+
942
+  if (frame_info.save_fp_p)
943
+    {
944
+      emit_frame_insn
945
+       (gen_rtx_SET (Pmode,
946
+                     indexed_memory (stack_pointer_rtx,
947
+                                     frame_info.fp_save_offset),
948
+                     frame_pointer_rtx));
949
+
950
+      emit_frame_insn
951
+       (gen_rtx_SET (Pmode, frame_pointer_rtx,
952
+                     gen_rtx_PLUS (Pmode, frame_pointer_rtx, value_rtx)));
953
+    }
954
+  if (frame_info.save_lr_p)
955
+    {
956
+
957
+      emit_frame_insn
958
+       (gen_rtx_SET (Pmode,
959
+                     indexed_memory (stack_pointer_rtx,
960
+                                     frame_info.lr_save_offset),
961
+                     gen_rtx_REG (Pmode, LINK_REGNUM)));
962
+    }
963
+  if (frame_info.gpr_size)
964
+    {
965
+      int offset = 0;
966
+      int regno;
967
+
968
+      for (regno = 0; regno <= LAST_INT_REG; regno++)
969
+       {
970
+         HOST_WIDE_INT disp = frame_info.gpr_offset + offset;
971
+
972
+         if (!(frame_info.mask & (1 << regno)))
973
+           continue;
974
+
975
+         emit_frame_insn
976
+           (gen_rtx_SET (Pmode,
977
+                         indexed_memory (stack_pointer_rtx, disp),
978
+                         gen_rtx_REG (Pmode, regno)));
979
+         offset = offset + UNITS_PER_WORD;
980
+       }
981
+    }
982
+}
983
+
984
+/* Called after register allocation to add any instructions needed for
985
+   the epilogue.  Using an epilogue insn is favored compared to
986
+   putting all of the instructions in output_function_epilogue(),
987
+   since it allows the scheduler to intermix instructions with the
988
+   restores of the caller saved registers.  In some cases, it might be
989
+   necessary to emit a barrier instruction as the first insn to
990
+   prevent such scheduling.  */
991
+
992
+void
993
+or32_expand_epilogue (int sibcall)
994
+{
995
+  int total_size = or32_compute_frame_size (get_frame_size ());
996
+  rtx value_rtx;
997
+
998
+  if (total_size > 32767)
999
+    {
1000
+      value_rtx = gen_rtx_REG (Pmode, 3);
1001
+
1002
+      emit_insn (gen_rtx_SET (Pmode, value_rtx, GEN_INT (total_size)));
1003
+    }
1004
+  else
1005
+    value_rtx = GEN_INT (total_size);
1006
+
1007
+  if (frame_info.save_lr_p)
1008
+    {
1009
+      or32_maybe_dead
1010
+       (emit_insn
1011
+        (gen_rtx_SET (Pmode, gen_rtx_REG (Pmode, LINK_REGNUM),
1012
+                      indexed_memory (stack_pointer_rtx,
1013
+                                      frame_info.lr_save_offset))));
1014
+    }
1015
+  if (frame_info.save_fp_p)
1016
+    {
1017
+      emit_insn
1018
+       (gen_rtx_SET (Pmode, gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
1019
+                     indexed_memory (stack_pointer_rtx,
1020
+                                     frame_info.fp_save_offset)));
1021
+    }
1022
+
1023
+  if (frame_info.gpr_size)
1024
+    {
1025
+      int offset = 0;
1026
+      int regno;
1027
+
1028
+      for (regno = 0; regno <= LAST_INT_REG; regno++)
1029
+       {
1030
+         HOST_WIDE_INT disp = frame_info.gpr_offset + offset;
1031
+
1032
+         if (!(frame_info.mask & (1 << regno)))
1033
+           continue;
1034
+
1035
+         emit_insn
1036
+           (gen_rtx_SET (Pmode, gen_rtx_REG (Pmode, regno),
1037
+                         indexed_memory (stack_pointer_rtx, disp)));
1038
+         offset = offset + UNITS_PER_WORD;
1039
+       }
1040
+    }
1041
+
1042
+  if (total_size)
1043
+    {
1044
+      emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx,
1045
+                             gen_rtx_PLUS (Pmode,
1046
+                                           stack_pointer_rtx, value_rtx)));
1047
+    }
1048
+
1049
+  if (!sibcall)
1050
+    emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, 9)));
1051
+}
1052
+
1053
+
1054
+void
1055
+print_operand (FILE * file, rtx x, int code)
1056
+{
1057
+  if (code == 'r' && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == REG)
1058
+    fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
1059
+  else if (code == '(')
1060
+    {
1061
+      if (dbr_sequence_length ())
1062
+       fprintf (file, "\t# delay slot filled");
1063
+      else
1064
+       fprintf (file, "\n\tl.nop\t\t\t# nop delay slot");
1065
+    }
1066
+  else if (code == 'C')
1067
+    {
1068
+      switch (GET_CODE (x))
1069
+       {
1070
+       case EQ:
1071
+         fputs ("eq", file);
1072
+         break;
1073
+       case NE:
1074
+         fputs ("ne", file);
1075
+         break;
1076
+       case GT:
1077
+         fputs ("gts", file);
1078
+         break;
1079
+       case GE:
1080
+         fputs ("ges", file);
1081
+         break;
1082
+       case LT:
1083
+         fputs ("lts", file);
1084
+         break;
1085
+       case LE:
1086
+         fputs ("les", file);
1087
+         break;
1088
+       case GTU:
1089
+         fputs ("gtu", file);
1090
+         break;
1091
+       case GEU:
1092
+         fputs ("geu", file);
1093
+         break;
1094
+       case LTU:
1095
+         fputs ("ltu", file);
1096
+         break;
1097
+       case LEU:
1098
+         fputs ("leu", file);
1099
+         break;
1100
+       default:
1101
+         abort ();
1102
+       }
1103
+    }
1104
+  else if (code == 'H')
1105
+    {
1106
+      if (GET_CODE (x) == REG)
1107
+       fprintf (file, "%s", reg_names[REGNO (x) + 1]);
1108
+      else
1109
+       abort ();
1110
+    }
1111
+  else if (GET_CODE (x) == REG)
1112
+    fprintf (file, "%s", reg_names[REGNO (x)]);
1113
+  else if (GET_CODE (x) == MEM)
1114
+    output_address (XEXP (x, 0));
1115
+  else
1116
+    output_addr_const (file, x);
1117
+}
1118
+
1119
+/* Generate assembler code for a movdi/movdf */
1120
+
1121
+const char *
1122
+or32_output_move_double (rtx * operands)
1123
+{
1124
+  rtx xoperands[3];
1125
+
1126
+  switch (GET_CODE (operands[0]))
1127
+    {
1128
+    case REG:
1129
+      if (GET_CODE (operands[1]) == REG)
1130
+       {
1131
+         if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
1132
+           {
1133
+             output_asm_insn ("\tl.or    \t%H0, %H1, r0", operands);
1134
+             output_asm_insn ("\tl.or    \t%0, %1, r0", operands);
1135
+             return "";
1136
+           }
1137
+         else
1138
+           {
1139
+             output_asm_insn ("\tl.or    \t%0, %1, r0", operands);
1140
+             output_asm_insn ("\tl.or    \t%H0, %H1, r0", operands);
1141
+             return "";
1142
+           }
1143
+       }
1144
+      else if (GET_CODE (operands[1]) == MEM)
1145
+       {
1146
+         xoperands[1] = XEXP (operands[1], 0);
1147
+         if (GET_CODE (xoperands[1]) == REG)
1148
+           {
1149
+             xoperands[0] = operands[0];
1150
+             if (REGNO (xoperands[0]) == REGNO (xoperands[1]))
1151
+               {
1152
+                 output_asm_insn ("\tl.lwz   \t%H0, 4(%1)", xoperands);
1153
+                 output_asm_insn ("\tl.lwz   \t%0, 0(%1)", xoperands);
1154
+                 return "";
1155
+               }
1156
+             else
1157
+               {
1158
+                 output_asm_insn ("\tl.lwz   \t%0, 0(%1)", xoperands);
1159
+                 output_asm_insn ("\tl.lwz   \t%H0, 4(%1)", xoperands);
1160
+                 return "";
1161
+               }
1162
+           }
1163
+         else if (GET_CODE (xoperands[1]) == PLUS)
1164
+           {
1165
+             if (GET_CODE (xoperands[2] = XEXP (xoperands[1], 1)) == REG)
1166
+               {
1167
+                 xoperands[0] = operands[0];
1168
+                 xoperands[1] = XEXP (xoperands[1], 0);
1169
+                 if (REGNO (xoperands[0]) == REGNO (xoperands[2]))
1170
+                   {
1171
+                     output_asm_insn ("\tl.lwz   \t%H0, %1+4(%2)",
1172
+                                      xoperands);
1173
+                     output_asm_insn ("\tl.lwz   \t%0, %1(%2)", xoperands);
1174
+                     return "";
1175
+                   }
1176
+                 else
1177
+                   {
1178
+                     output_asm_insn ("\tl.lwz   \t%0, %1(%2)", xoperands);
1179
+                     output_asm_insn ("\tl.lwz   \t%H0, %1+4(%2)",
1180
+                                      xoperands);
1181
+                     return "";
1182
+                   }
1183
+               }
1184
+             else if (GET_CODE (xoperands[2] = XEXP (xoperands[1], 0)) ==
1185
+                      REG)
1186
+               {
1187
+                 xoperands[0] = operands[0];
1188
+                 xoperands[1] = XEXP (xoperands[1], 1);
1189
+                 if (REGNO (xoperands[0]) == REGNO (xoperands[2]))
1190
+                   {
1191
+                     output_asm_insn ("\tl.lwz   \t%H0, %1+4(%2)",
1192
+                                      xoperands);
1193
+                     output_asm_insn ("\tl.lwz   \t%0, %1(%2)", xoperands);
1194
+                     return "";
1195
+                   }
1196
+                 else
1197
+                   {
1198
+                     output_asm_insn ("\tl.lwz   \t%0, %1(%2)", xoperands);
1199
+                     output_asm_insn ("\tl.lwz   \t%H0, %1+4(%2)",
1200
+                                      xoperands);
1201
+                     return "";
1202
+                   }
1203
+               }
1204
+             else
1205
+               abort ();
1206
+           }
1207
+         else
1208
+           abort ();
1209
+       }
1210
+      else if (GET_CODE (operands[1]) == CONST_INT)
1211
+       {
1212
+         if (INTVAL (operands[1]) < 0)
1213
+           output_asm_insn ("\tl.addi  \t%0, r0, -1", operands);
1214
+         else
1215
+           output_asm_insn ("\tl.or    \t%0, r0, r0", operands);
1216
+         output_asm_insn ("\tl.movhi \t%H0, hi(%1)", operands);
1217
+         output_asm_insn ("\tl.ori   \t%H0, %H0, lo(%1)", operands);
1218
+         return "";
1219
+       }
1220
+      else
1221
+       abort ();
1222
+    case MEM:
1223
+      xoperands[0] = XEXP (operands[0], 0);
1224
+      if (GET_CODE (xoperands[0]) == REG)
1225
+       {
1226
+         xoperands[1] = operands[1];
1227
+         output_asm_insn ("\tl.sw    \t0(%0), %1", xoperands);
1228
+         output_asm_insn ("\tl.sw    \t4(%0), %H1", xoperands);
1229
+         return "";
1230
+       }
1231
+      else if (GET_CODE (xoperands[0]) == PLUS)
1232
+       {
1233
+         if (GET_CODE (xoperands[1] = XEXP (xoperands[0], 1)) == REG)
1234
+           {
1235
+             xoperands[0] = XEXP (xoperands[0], 0);
1236
+             xoperands[2] = operands[1];
1237
+             output_asm_insn ("\tl.sw    \t%0(%1), %2", xoperands);
1238
+             output_asm_insn ("\tl.sw    \t%0+4(%1), %H2", xoperands);
1239
+             return "";
1240
+           }
1241
+         else if (GET_CODE (xoperands[1] = XEXP (xoperands[0], 0)) == REG)
1242
+           {
1243
+             xoperands[0] = XEXP (xoperands[0], 1);
1244
+             xoperands[2] = operands[1];
1245
+             output_asm_insn ("\tl.sw    \t%0(%1), %2", xoperands);
1246
+             output_asm_insn ("\tl.sw    \t%0+4(%1), %H2", xoperands);
1247
+             return "";
1248
+           }
1249
+         else
1250
+           abort ();
1251
+       }
1252
+      else
1253
+       abort ();
1254
+    default:
1255
+      abort ();
1256
+    }
1257
+}
1258
+
1259
+enum rtx_code
1260
+or32_reverse_condition (enum machine_mode mode ATTRIBUTE_UNUSED,
1261
+                       enum rtx_code code)
1262
+{
1263
+  return reverse_condition (code);
1264
+}
1265
+
1266
+enum machine_mode
1267
+or32_cc_mode (enum rtx_code code,
1268
+             rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1269
+{
1270
+
1271
+  switch (code)
1272
+    {
1273
+    case EQ:
1274
+      return CCEQmode;
1275
+    case NE:
1276
+      return CCNEmode;
1277
+    case GEU:
1278
+      return CCGEUmode;
1279
+    case GTU:
1280
+      return CCGTUmode;
1281
+    case LTU:
1282
+      return CCLTUmode;
1283
+    case LEU:
1284
+      return CCLEUmode;
1285
+    case GE:
1286
+      return CCGEmode;
1287
+    case LT:
1288
+      return CCLTmode;
1289
+    case GT:
1290
+      return CCGTmode;
1291
+    case LE:
1292
+      return CCLEmode;
1293
+
1294
+    default:
1295
+      abort ();
1296
+    }
1297
+}
1298
+
1299
+/* Generate insn patterns to do an integer compare of OPERANDS.  */
1300
+
1301
+static rtx
1302
+or32_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
1303
+{
1304
+  enum machine_mode cmpmode;
1305
+  rtx tmp, flags;
1306
+
1307
+  cmpmode = SELECT_CC_MODE (code, op0, op1);
1308
+  flags = gen_rtx_REG (cmpmode, FLAGS_REG);
1309
+
1310
+  /* This is very simple, but making the interface the same as in the
1311
+     FP case makes the rest of the code easier.  */
1312
+  tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
1313
+  emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
1314
+
1315
+  /* Return the test that should be put into the flags user, i.e.
1316
+     the bcc, scc, or cmov instruction.  */
1317
+  return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
1318
+}
1319
+
1320
+rtx
1321
+or32_expand_compare (enum rtx_code code, rtx op0, rtx op1)
1322
+{
1323
+  return or32_expand_int_compare (code, op0, op1);
1324
+}
1325
+
1326
+void
1327
+or32_expand_branch (enum rtx_code code, rtx label)
1328
+{
1329
+  rtx tmp;
1330
+
1331
+  switch (GET_MODE (or32_compare_op0))
1332
+    {
1333
+    case SImode:
1334
+      tmp = or32_expand_compare (code, or32_compare_op0, or32_compare_op1);
1335
+      tmp = gen_rtx_IF_THEN_ELSE (VOIDmode,
1336
+                                 tmp,
1337
+                                 gen_rtx_LABEL_REF (VOIDmode, label),
1338
+                                 pc_rtx);
1339
+      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
1340
+      return;
1341
+
1342
+
1343
+    default:
1344
+      abort ();
1345
+    }
1346
+
1347
+}
1348
+
1349
+static int
1350
+or32_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
1351
+{
1352
+  rtx condition_rtx, cr;
1353
+
1354
+  if ((GET_MODE (or32_compare_op0) != SImode) &&
1355
+      (GET_MODE (or32_compare_op0) != HImode) &&
1356
+      (GET_MODE (or32_compare_op0) != QImode))
1357
+    return 0;
1358
+
1359
+  /* We still have to do the compare, because cmov doesn't do a
1360
+     compare, it just looks at the FLAG bit set by a previous compare
1361
+     instruction.  */
1362
+
1363
+  condition_rtx = or32_expand_compare (GET_CODE (op),
1364
+                                      or32_compare_op0, or32_compare_op1);
1365
+
1366
+  cr = XEXP (condition_rtx, 0);
1367
+
1368
+  emit_insn (gen_cmov (dest, condition_rtx, true_cond, false_cond, cr));
1369
+
1370
+  return 1;
1371
+}
1372
+
1373
+
1374
+/* Emit a conditional move: move TRUE_COND to DEST if OP of the
1375
+   operands of the last comparison is nonzero/true, FALSE_COND if it
1376
+   is zero/false.  Return 0 if the hardware has no such operation.  */
1377
+
1378
+int
1379
+or32_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
1380
+{
1381
+  enum machine_mode result_mode = GET_MODE (dest);
1382
+
1383
+  if (GET_MODE (true_cond) != result_mode)
1384
+    return 0;
1385
+
1386
+  if (GET_MODE (false_cond) != result_mode)
1387
+    return 0;
1388
+
1389
+  /* First, work out if the hardware can do this at all */
1390
+  return or32_emit_int_cmove (dest, op, true_cond, false_cond);
1391
+}
1392
+
1393
+const char *
1394
+output_bf (rtx * operands)
1395
+{
1396
+  enum rtx_code code;
1397
+  enum machine_mode mode_calc, mode_got;
1398
+
1399
+  code = GET_CODE (operands[1]);
1400
+  mode_calc = SELECT_CC_MODE (code, or32_compare_op0, or32_compare_op1);
1401
+  mode_got = GET_MODE (operands[2]);
1402
+
1403
+  if (!TARGET_ALIGNED_JUMPS)
1404
+    {
1405
+      if (mode_calc != mode_got)
1406
+       return "l.bnf   \t%l0%(";
1407
+      else
1408
+       return "l.bf    \t%l0%(";
1409
+    }
1410
+  else
1411
+    {
1412
+      if (mode_calc != mode_got)
1413
+       return "\t.balignl 0x8,0x15000015,0x4;l.bnf   \t%l0%(";
1414
+      else
1415
+       return "\t.balignl 0x8,0x15000015,0x4;l.bf    \t%l0%(";
1416
+    }
1417
+}
1418
+
1419
+const char *
1420
+output_cmov (rtx * operands)
1421
+{
1422
+  enum rtx_code code;
1423
+  enum machine_mode mode_calc, mode_got;
1424
+
1425
+  code = GET_CODE (operands[1]);
1426
+  mode_calc = SELECT_CC_MODE (code, or32_compare_op0, or32_compare_op1);
1427
+  mode_got = GET_MODE (operands[4]);
1428
+
1429
+  if (mode_calc != mode_got)
1430
+    return "l.cmov  \t%0,%3,%2";       /* reversed */
1431
+  else
1432
+    return "l.cmov  \t%0,%2,%3";
1433
+}
1434
+
1435
+/* Any function is ok for sibcall optimization if we allow this optimization
1436
+ */
1437
+static bool
1438
+or32_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
1439
+                             tree exp ATTRIBUTE_UNUSED)
1440
+{
1441
+  return TARGET_SIBCALL;
1442
+}
1443
+
1444
+/* For now this is very simple way for sibcall support */
1445
+
1446
+void
1447
+or32_expand_sibcall (rtx result, rtx addr, rtx args_size)
1448
+{
1449
+  emit_call_insn (gen_sibcall_internal (addr, args_size));
1450
+}
1451
+
1452
+
1453
+/* We know it can't be done in one insn when we get here,
1454
+   the movsi expander guarantees this.  */
1455
+void
1456
+or32_emit_set_const32 (rtx op0, rtx op1)
1457
+{
1458
+  enum machine_mode mode = GET_MODE (op0);
1459
+  rtx temp;
1460
+
1461
+
1462
+  if (GET_CODE (op1) == CONST_INT)
1463
+    {
1464
+      HOST_WIDE_INT value = INTVAL (op1);
1465
+
1466
+      if (CONST_OK_FOR_LETTER_P (value & GET_MODE_MASK (mode), 'K')
1467
+         || CONST_OK_FOR_LETTER_P (value, 'M')
1468
+         || CONST_OK_FOR_LETTER_P (value, 'I'))
1469
+       abort ();
1470
+    }
1471
+
1472
+
1473
+  /* Full 2-insn decomposition is needed.  */
1474
+  if (reload_in_progress || reload_completed)
1475
+    {
1476
+      temp = op0;
1477
+    }
1478
+  else
1479
+    temp = gen_reg_rtx (mode);
1480
+
1481
+  if (GET_CODE (op1) == CONST_INT)
1482
+    {
1483
+      /* Emit them as real moves instead of a HIGH/LO_SUM,
1484
+         this way CSE can see everything and reuse intermediate
1485
+         values if it wants.  */
1486
+      emit_insn (gen_rtx_SET (VOIDmode, temp,
1487
+                             GEN_INT (INTVAL (op1)
1488
+                                      & ~(HOST_WIDE_INT) 0xffff)));
1489
+
1490
+      emit_insn (gen_rtx_SET (VOIDmode,
1491
+                             op0,
1492
+                             gen_rtx_IOR (mode, temp,
1493
+                                          GEN_INT (INTVAL (op1) & 0xffff))));
1494
+    }
1495
+  else
1496
+    {
1497
+
1498
+#if 0
1499
+      /* A symbol, emit in the traditional way.  */
1500
+
1501
+      emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_HIGH (mode, op1)));
1502
+      emit_insn (gen_rtx_SET (VOIDmode,
1503
+                             op0, gen_rtx_LO_SUM (mode, temp, op1)));
1504
+#else
1505
+      /* since or32 bfd can not deal with relocs that are not of type
1506
+         OR32_CONSTH_RELOC + OR32_CONST_RELOC (ie move high must be
1507
+         followed by exactly one lo_sum)
1508
+       */
1509
+      emit_insn (gen_movsi_insn_big (op0, op1));
1510
+#endif
1511
+    }
1512
+}
1513
+
1514
+
1515
+/* Functions returning costs and making code size/performance tradeoffs */
1516
+
1517
+int
1518
+or32_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1519
+                        enum reg_class from ATTRIBUTE_UNUSED,
1520
+                        enum reg_class to ATTRIBUTE_UNUSED)
1521
+{
1522
+  return 2;
1523
+}
1524
+
1525
+/* A C expressions returning the cost of moving data of MODE from a register to
1526
+   or from memory.  */
1527
+
1528
+int
1529
+or32_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1530
+                      enum reg_class class ATTRIBUTE_UNUSED,
1531
+                      int in ATTRIBUTE_UNUSED)
1532
+{
1533
+  return 2;
1534
+}
1535
+
1536
+/* Specify the cost of a branch insn; roughly the number of extra insns that
1537
+   should be added to avoid a branch.
1538
+
1539
+   Set this to 3 on the or32 since that is roughly the average cost of an
1540
+   unscheduled conditional branch.
1541
+
1542
+   Cost of 2 and 3 give equal and ~0.7% bigger binaries
1543
+
1544
+*/
1545
+int
1546
+or32_branch_cost ()
1547
+{
1548
+  return 1;
1549
+}
1550
diff -Nru gcc-3.4.4.orig/gcc/config/or32/or32.h gcc-3.4.4-DONE/gcc/config/or32/or32.h
1551
--- gcc-3.4.4.orig/gcc/config/or32/or32.h       1970-01-01 02:00:00.000000000 +0200
1552
+++ gcc-3.4.4-DONE/gcc/config/or32/or32.h       2005-11-29 17:01:54.000000000 +0200
1553
@@ -0,0 +1,1361 @@
1554
+/* Definitions of target machine for GNU compiler.  OpenRISC 1000 version.
1555
+   Copyright (C) 1987, 1988, 1992, 1995, 1996, 1999, 2000, 2001, 2002,
1556
+   2003, 2004, 2005 Free Software Foundation, Inc.
1557
+   Contributed by Damjan Lampret <damjanl@bsemi.com> in 1999.
1558
+   Major optimizations by Matjaz Breskvar <matjazb@bsemi.com> in 2005.
1559
+
1560
+This file is part of GNU CC.
1561
+
1562
+GNU CC is free software; you can redistribute it and/or modify
1563
+it under the terms of the GNU General Public License as published by
1564
+the Free Software Foundation; either version 1, or (at your option)
1565
+any later version.
1566
+
1567
+GNU CC is distributed in the hope that it will be useful,
1568
+but WITHOUT ANY WARRANTY; without even the implied warranty of
1569
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1570
+GNU General Public License for more details.
1571
+
1572
+You should have received a copy of the GNU General Public License
1573
+along with GNU CC; see the file COPYING.  If not, write to
1574
+the Free Software Foundation, 59 Temple Place - Suite 330,
1575
+Boston, MA 02111-1307, USA.  */
1576
+
1577
+#ifndef _OR32_H_
1578
+#define _OR32_H_
1579
+
1580
+/* Target CPU builtins */
1581
+#define TARGET_CPU_CPP_BUILTINS()              \
1582
+  do                                           \
1583
+    {                                          \
1584
+      builtin_define_std ("OR1K");             \
1585
+      builtin_define_std ("or1k");             \
1586
+      builtin_assert ("cpu=or1k");             \
1587
+      builtin_assert ("machine=or1k");         \
1588
+    }                                          \
1589
+  while (0)
1590
+
1591
+#if 0
1592
+
1593
+/* Which library to get.  The only difference from the default is to get
1594
+   libsc.a if -sim is given to the driver.  Repeat -lc -lsysX
1595
+   {X=sim,linux}, because libsysX needs (at least) errno from libc, and
1596
+   then we want to resolve new unknowns in libc against libsysX, not
1597
+   libnosys.  */
1598
+/* Override previous definitions (linux.h).  */
1599
+#undef LIB_SPEC
1600
+#define LIB_SPEC \
1601
+ "%{sim*:-lc -lsyssim -lc -lsyssim}\
1602
+  %{!sim*:%{g*:-lg}\
1603
+    %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} -lbsp}\
1604
+  -lnosys"
1605
+#endif
1606
+
1607
+#define TARGET_VERSION fprintf (stderr, " (OpenRISC 1000)");
1608
+
1609
+/* Run-time compilation parameters selecting different hardware subsets.  */
1610
+
1611
+extern int target_flags;
1612
+
1613
+/* Enable hardware fp support. */
1614
+#define MASK_HARD_FLOAT                0x00000001
1615
+
1616
+/* Enable hardware div instruction. */
1617
+#define MASK_HARD_DIV          0x00000002
1618
+
1619
+/* Enable hardware mul instruction. */
1620
+#define MASK_HARD_MUL           0x00000004
1621
+
1622
+/* Use aligned jumps. */
1623
+#define MASK_ALIGNED_JUMPS      0x00000008
1624
+
1625
+/* Use l.extbs and l.exths instructions. */
1626
+#define MASK_SEXT               0x00000010
1627
+
1628
+/* Use l.cmov instruction. */
1629
+#define MASK_CMOV               0x00000020
1630
+
1631
+/* Emit prologue and epilogue. */
1632
+#define MASK_SCHED_LOGUE        0x00000040
1633
+
1634
+/* Emit prologue and epilogue. */
1635
+#define MASK_ROR                0x00000080
1636
+
1637
+/* Emit prologue and epilogue. */
1638
+#define MASK_SIBCALL            0x00000100
1639
+
1640
+
1641
+/* Macros used in the machine description to test the flags.  */
1642
+
1643
+#define TARGET_HARD_FLOAT      (target_flags & MASK_HARD_FLOAT)
1644
+#define TARGET_HARD_DIV                (target_flags & MASK_HARD_DIV)
1645
+#define TARGET_HARD_MUL         (target_flags & MASK_HARD_MUL)
1646
+#define TARGET_ALIGNED_JUMPS    (target_flags & MASK_ALIGNED_JUMPS)
1647
+#define TARGET_SEXT             (target_flags & MASK_SEXT)
1648
+#define TARGET_CMOV             (target_flags & MASK_CMOV)
1649
+#define TARGET_SCHED_LOGUE      (target_flags & MASK_SCHED_LOGUE)
1650
+#define TARGET_ROR              (target_flags & MASK_ROR)
1651
+#define TARGET_SIBCALL          (target_flags & MASK_SIBCALL)
1652
+
1653
+/* Macro to define tables used to set the flags.
1654
+   This is a list in braces of pairs in braces,
1655
+   each pair being { "NAME", VALUE }
1656
+   where VALUE is the bits to set or minus the bits to clear.
1657
+   An empty string NAME is used to identify the default VALUE.  */
1658
+
1659
+#define TARGET_SWITCHES                                                                         \
1660
+  { {"hard-float",     MASK_HARD_FLOAT,        N_("Use hardware floating point.")},     \
1661
+    {"soft-float",     - MASK_HARD_FLOAT,      N_("Use software floating point.")},     \
1662
+    {"hard-div",       MASK_HARD_DIV,          N_("Use hardware divison.")},            \
1663
+    {"soft-div",       - MASK_HARD_DIV,        N_("Use software divison.")},            \
1664
+    {"hard-mul",       MASK_HARD_MUL,          N_("Use hardware multiplication.")},     \
1665
+    {"soft-mul",       - MASK_HARD_MUL,        N_("Use software multiplication.")},     \
1666
+    {"aj",              MASK_ALIGNED_JUMPS,     N_("Use aligned jumps.")},               \
1667
+    {"no-aj",           - MASK_ALIGNED_JUMPS,   N_("Do not use aligned jumps.")},        \
1668
+    {"sext",            MASK_SEXT,              N_("Use sign extending instructions.")}, \
1669
+    {"no-sext",         - MASK_SEXT,            N_("Do not use sign extending insn.")},  \
1670
+    {"cmov",            MASK_CMOV,              N_("Use conditional move insn.")},       \
1671
+    {"no-cmov",         - MASK_CMOV,            N_("Do not use conditional move insn.")},\
1672
+    {"logue",           MASK_SCHED_LOGUE,       N_("Schedule pro/epi-logue.")},          \
1673
+    {"no-logue",        - MASK_SCHED_LOGUE,     N_("Do not schedule pro/epi-logue.")},   \
1674
+    {"ror",             MASK_ROR,               N_("Emit ror insns.")},                  \
1675
+    {"no-ror",          - MASK_ROR,             N_("Do not emit ror insns.")},           \
1676
+    {"sibcall",         MASK_SIBCALL,           N_("Enable sibcall optimization.")},     \
1677
+    {"no-sibcall",      - MASK_SIBCALL,         N_("Disable sibcall optimization.")},    \
1678
+    { "",              TARGET_DEFAULT,         0}}
1679
+
1680
+/* Default target_flags if no switches specified.  */
1681
+
1682
+#ifndef TARGET_DEFAULT
1683
+#define TARGET_DEFAULT (MASK_HARD_MUL)
1684
+#endif
1685
+
1686
+#undef TARGET_ASM_NAMED_SECTION
1687
+#define TARGET_ASM_NAMED_SECTION  default_elf_asm_named_section
1688
+
1689
+/* Target machine storage layout */
1690
+
1691
+/* Define this if most significant bit is lowest numbered
1692
+   in instructions that operate on numbered bit-fields.
1693
+   This is not true on the or1k.  */
1694
+#define BITS_BIG_ENDIAN 0
1695
+
1696
+/* Define this if most significant byte of a word is the lowest numbered.  */
1697
+#define BYTES_BIG_ENDIAN 1
1698
+
1699
+/* Define this if most significant word of a multiword number is numbered.  */
1700
+#define WORDS_BIG_ENDIAN 1
1701
+
1702
+/* Number of bits in an addressable storage unit */
1703
+#define BITS_PER_UNIT 8
1704
+
1705
+#define BITS_PER_WORD 32
1706
+#define SHORT_TYPE_SIZE 16
1707
+#define INT_TYPE_SIZE 32
1708
+#define LONG_TYPE_SIZE 32
1709
+#define LONG_LONG_TYPE_SIZE 64
1710
+#define FLOAT_TYPE_SIZE 32
1711
+#define DOUBLE_TYPE_SIZE 64
1712
+#define LONG_DOUBLE_TYPE_SIZE 64
1713
+
1714
+/* Width of a word, in units (bytes).  */
1715
+#define UNITS_PER_WORD 4
1716
+
1717
+/* Width in bits of a pointer.
1718
+   See also the macro `Pmode' defined below.  */
1719
+#define POINTER_SIZE 32
1720
+
1721
+/* Allocation boundary (in *bits*) for storing pointers in memory.  */
1722
+#define POINTER_BOUNDARY 32
1723
+
1724
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
1725
+#define PARM_BOUNDARY 32
1726
+
1727
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
1728
+#define STACK_BOUNDARY 32
1729
+
1730
+/* Allocation boundary (in *bits*) for the code of a function.  */
1731
+#define FUNCTION_BOUNDARY 32
1732
+
1733
+/* Alignment of field after `int : 0' in a structure.  */
1734
+#define EMPTY_FIELD_BOUNDARY 8
1735
+
1736
+/* Every structure's size must be a multiple of this.  */
1737
+#define STRUCTURE_SIZE_BOUNDARY 32
1738
+
1739
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
1740
+#define PCC_BITFIELD_TYPE_MATTERS 1
1741
+
1742
+/* No data type wants to be aligned rounder than this.  */
1743
+#define BIGGEST_ALIGNMENT 32
1744
+
1745
+/* The best alignment to use in cases where we have a choice.  */
1746
+#define FASTEST_ALIGNMENT 32
1747
+
1748
+/* Make strings word-aligned so strcpy from constants will be faster.  */
1749
+/*
1750
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)                                 \
1751
+  ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR)    \
1752
+    && (ALIGN) < FASTEST_ALIGNMENT                                     \
1753
+   ? FASTEST_ALIGNMENT : (ALIGN))
1754
+*/
1755
+
1756
+/* One use of this macro is to increase alignment of medium-size
1757
+   data to make it all fit in fewer cache lines.  Another is to
1758
+   cause character arrays to be word-aligned so that `strcpy' calls
1759
+   that copy constants to character arrays can be done inline.  */
1760
+/*
1761
+#define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
1762
+  ((((ALIGN) < FASTEST_ALIGNMENT)                                       \
1763
+    && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
1764
+        || TREE_CODE (TYPE) == UNION_TYPE                               \
1765
+        || TREE_CODE (TYPE) == RECORD_TYPE)) ? FASTEST_ALIGNMENT : (ALIGN))
1766
+*/ /* CHECK - btw code gets bigger with this one */
1767
+
1768
+/* Define this if move instructions will actually fail to work
1769
+   when given unaligned data.  */
1770
+#define STRICT_ALIGNMENT 1 /* CHECK */
1771
+
1772
+/* Align an address */
1773
+#define OR32_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1774
+
1775
+/* Define this macro if an argument declared as `char' or `short' in a
1776
+   prototype should actually be passed as an `int'.  In addition to
1777
+   avoiding errors in certain cases of mismatch, it also makes for
1778
+   better code on certain machines. */
1779
+#define PROMOTE_PROTOTYPES  1
1780
+
1781
+/* Define if operations between registers always perform the operation
1782
+   on the full register even if a narrower mode is specified.  */
1783
+#define WORD_REGISTER_OPERATIONS  /* CHECK */
1784
+
1785
+
1786
+/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1787
+   will either zero-extend or sign-extend.  The value of this macro should
1788
+   be the code that says which one of the two operations is implicitly
1789
+   done, NIL if none.  */
1790
+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1791
+
1792
+/* Define this macro if it is advisable to hold scalars in registers
1793
+   in a wider mode than that declared by the program.  In such cases,
1794
+   the value is constrained to be within the bounds of the declared
1795
+   type, but kept valid in the wider mode.  The signedness of the
1796
+   extension may differ from that of the type. */
1797
+
1798
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
1799
+  if (GET_MODE_CLASS (MODE) == MODE_INT         \
1800
+      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1801
+    (MODE) = SImode;
1802
+  /* CHECK */
1803
+
1804
+/* Define this if function arguments should also be promoted using the above
1805
+   procedure.  */
1806
+
1807
+#define PROMOTE_FUNCTION_ARGS
1808
+
1809
+/* Likewise, if the function return value is promoted.  */
1810
+
1811
+#define PROMOTE_FUNCTION_RETURN
1812
+
1813
+/*
1814
+ * brings 0.4% improvment in static size for linux
1815
+ *
1816
+#define PROMOTE_FOR_CALL_ONLY
1817
+*/
1818
+
1819
+/* Define this macro if it is as good or better to call a constant
1820
+   function address than to call an address kept in a register.  */
1821
+#define NO_FUNCTION_CSE 1 /* check */
1822
+
1823
+/* Define this macro if it is as good or better for a function to
1824
+   call itself with an explicit address than to call an address
1825
+   kept in a register.  */
1826
+#define NO_RECURSIVE_FUNCTION_CSE 1 /*check*/
1827
+
1828
+/* Standard register usage.  */
1829
+
1830
+/* Number of actual hardware registers.
1831
+   The hardware registers are assigned numbers for the compiler
1832
+   from 0 to just below FIRST_PSEUDO_REGISTER.
1833
+   All registers that the compiler knows about must be given numbers,
1834
+   even those that are not normally considered general registers.  */
1835
+#define FIRST_PSEUDO_REGISTER 33
1836
+#define LAST_INT_REG (FIRST_PSEUDO_REGISTER - 1)
1837
+
1838
+/* 1 for registers that have pervasive standard uses
1839
+   and are not available for the register allocator.
1840
+   On the or1k, these are r1 as stack pointer and
1841
+   r2 as frame/arg pointer.  */
1842
+#define FIXED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0,   0, 1, 0, 0, 0, 0, 0, 0, \
1843
+                        0, 0, 0, 0, 0, 0, 0, 0,   0, 0, 0, 0, 0, 0, 0, 0, 1}
1844
+/* 1 for registers not available across function calls.
1845
+   These must include the FIXED_REGISTERS and also any
1846
+   registers that can be used without being saved.
1847
+   The latter must include the registers where values are returned
1848
+   and the register where structure-value addresses are passed.
1849
+   Aside from that, you can include as many other registers as you like.  */
1850
+#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 1, 1, 1,  1, 1, 0, 1, 0, 1, 0, 1, \
1851
+                            0, 1, 0, 1, 0, 1, 0, 1,  0, 1, 0, 1, 0, 1, 0, 1, 1}
1852
+
1853
+/* stack pointer: must be FIXED and CALL_USED */
1854
+/* frame pointer: must be FIXED and CALL_USED */
1855
+
1856
+/* Return number of consecutive hard regs needed starting at reg REGNO
1857
+   to hold something of mode MODE.
1858
+   This is ordinarily the length in words of a value of mode MODE
1859
+   but can be less for certain modes in special long registers.
1860
+   On the or1k, all registers are one word long.  */
1861
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
1862
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1863
+
1864
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1865
+#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
1866
+
1867
+/* Value is 1 if it is a good idea to tie two pseudo registers
1868
+   when one has mode MODE1 and one has mode MODE2.
1869
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1870
+   for any hard reg, then this must be 0 for correct output.  */
1871
+#define MODES_TIEABLE_P(MODE1, MODE2)  1
1872
+
1873
+/* A C expression returning the cost of moving data from a register of class
1874
+   CLASS1 to one of CLASS2.  */
1875
+#define REGISTER_MOVE_COST or32_register_move_cost
1876
+
1877
+/* A C expressions returning the cost of moving data of MODE from a register to
1878
+   or from memory.  */
1879
+#define MEMORY_MOVE_COST or32_memory_move_cost
1880
+
1881
+/* Specify the cost of a branch insn; roughly the number of extra insns that
1882
+   should be added to avoid a branch. */
1883
+#define BRANCH_COST or32_branch_cost()
1884
+
1885
+/* Specify the registers used for certain standard purposes.
1886
+   The values of these macros are register numbers.  */
1887
+
1888
+/* Register to use for pushing function arguments.  */
1889
+#define STACK_POINTER_REGNUM 1
1890
+
1891
+/* Base register for access to local variables of the function.  */
1892
+#define FRAME_POINTER_REGNUM 2
1893
+
1894
+/* Link register. */
1895
+#define LINK_REGNUM 9
1896
+
1897
+/* Value should be nonzero if functions must have frame pointers.
1898
+   Zero means the frame pointer need not be set up (and parms
1899
+   may be accessed via the stack pointer) in functions that seem suitable.
1900
+   This is computed in `reload', in reload1.c.  */
1901
+#define FRAME_POINTER_REQUIRED 0
1902
+
1903
+/* De ne this macro if debugging can be performed even without a frame pointer.
1904
+   If this macro is de ned, GCC will turn on the `-fomit-frame-pointer' option
1905
+   whenever `-O' is specifed.
1906
+ */
1907
+/*
1908
+#define CAN_DEBUG_WITHOUT_FP
1909
+ */
1910
+
1911
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)                                            \
1912
+{ int regno;                                                                           \
1913
+  int offset = 0;                                                                      \
1914
+  for( regno=0; regno < FIRST_PSEUDO_REGISTER;  regno++ )                              \
1915
+    if( regs_ever_live[regno] && !call_used_regs[regno] )                              \
1916
+      offset += 4;                                                                     \
1917
+  (DEPTH) = (!current_function_is_leaf || regs_ever_live[LINK_REGNUM] ? 4 : 0) +       \
1918
+               (frame_pointer_needed ? 4 : 0)                                  +       \
1919
+               offset                                                          +       \
1920
+               OR32_ALIGN(current_function_outgoing_args_size,4)               +       \
1921
+               OR32_ALIGN(get_frame_size(),4);                                         \
1922
+}
1923
+
1924
+/* Base register for access to arguments of the function.  */
1925
+#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1926
+
1927
+/* Register in which static-chain is passed to a function.  */
1928
+#define STATIC_CHAIN_REGNUM 0
1929
+
1930
+/* Register in which address to store a structure value
1931
+   is passed to a function.  */
1932
+/*#define STRUCT_VALUE_REGNUM 0*/
1933
+
1934
+/* Pass address of result struct to callee as "invisible" first argument */
1935
+#define STRUCT_VALUE 0
1936
+
1937
+/* -----------------------[ PHX start ]-------------------------------- */
1938
+
1939
+/* Define the classes of registers for register constraints in the
1940
+   machine description.  Also define ranges of constants.
1941
+
1942
+   One of the classes must always be named ALL_REGS and include all hard regs.
1943
+   If there is more than one class, another class must be named NO_REGS
1944
+   and contain no registers.
1945
+
1946
+   The name GENERAL_REGS must be the name of a class (or an alias for
1947
+   another name such as ALL_REGS).  This is the class of registers
1948
+   that is allowed by "g" or "r" in a register constraint.
1949
+   Also, registers outside this class are allocated only when
1950
+   instructions express preferences for them.
1951
+
1952
+   GENERAL_REGS and BASE_REGS classess are the same on or32.
1953
+
1954
+   The classes must be numbered in nondecreasing order; that is,
1955
+   a larger-numbered class must never be contained completely
1956
+   in a smaller-numbered class.
1957
+
1958
+   For any two classes, it is very desirable that there be another
1959
+   class that represents their union.  */
1960
+
1961
+/* The or1k has only one kind of registers, so NO_REGS, GENERAL_REGS
1962
+   and ALL_REGS are the only classes.  */
1963
+
1964
+enum reg_class
1965
+{
1966
+  NO_REGS,
1967
+  GENERAL_REGS,
1968
+  CR_REGS,
1969
+  ALL_REGS,
1970
+  LIM_REG_CLASSES
1971
+};
1972
+
1973
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
1974
+
1975
+/* Give names of register classes as strings for dump file.   */
1976
+
1977
+#define REG_CLASS_NAMES                                                        \
1978
+{                                                                      \
1979
+  "NO_REGS",                                                           \
1980
+  "GENERAL_REGS",                                                      \
1981
+  "ALL_REGS"                                                           \
1982
+}
1983
+
1984
+
1985
+/* Define which registers fit in which classes.
1986
+   This is an initializer for a vector of HARD_REG_SET
1987
+   of length N_REG_CLASSES.  */
1988
+
1989
+/* An initializer containing the contents of the register classes,
1990
+   as integers which are bit masks.  The Nth integer specifies the
1991
+   contents of class N.  The way the integer MASK is interpreted is
1992
+   that register R is in the class if `MASK & (1 << R)' is 1.
1993
+
1994
+   When the machine has more than 32 registers, an integer does not
1995
+   suffice.  Then the integers are replaced by sub-initializers,
1996
+   braced groupings containing several integers.  Each
1997
+   sub-initializer must be suitable as an initializer for the type
1998
+   `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
1999
+
2000
+#define REG_CLASS_CONTENTS                          \
2001
+{                                                   \
2002
+  { 0x00000000, 0x00000000 }, /* NO_REGS */         \
2003
+  { 0xffffffff, 0x00000001 }, /* GENERAL_REGS */     \
2004
+  { 0xffffffff, 0x00000000 }  /* ALL_REGS */        \
2005
+}
2006
+
2007
+/* The same information, inverted:
2008
+   Return the class number of the smallest class containing
2009
+   reg number REGNO.  This could be a conditional expression
2010
+   or could index an array.  */
2011
+
2012
+#define REGNO_REG_CLASS(REGNO)                 \
2013
+ ((REGNO) < 32 ? GENERAL_REGS                  \
2014
+  : NO_REGS)
2015
+
2016
+/* The class value for index registers, and the one for base regs.  */
2017
+#define INDEX_REG_CLASS GENERAL_REGS
2018
+#define BASE_REG_CLASS GENERAL_REGS
2019
+
2020
+/* Get reg_class from a letter such as appears in the machine description.  */
2021
+
2022
+#define REG_CLASS_FROM_LETTER(C) NO_REGS
2023
+
2024
+#if 1
2025
+/* The letters I, J, K, L and M in a register constraint string
2026
+   can be used to stand for particular ranges of immediate operands.
2027
+   This macro defines what the ranges are.
2028
+   C is the letter, and VALUE is a constant value.
2029
+   Return 1 if VALUE is in the range specified by C.  */
2030
+
2031
+#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
2032
+    (  (C) == 'I' ? ((VALUE) >=-32768 && (VALUE) <=32767) \
2033
+     : (C) == 'J' ? ((VALUE) >=0 && (VALUE) <=0) \
2034
+     : (C) == 'K' ? ((VALUE) >=0 && (VALUE) <=65535) \
2035
+     : (C) == 'L' ? ((VALUE) >=0 && (VALUE) <=31) \
2036
+     : (C) == 'M' ? (((VALUE) & 0xffff) == 0 )         \
2037
+     : (C) == 'N' ? ((VALUE) >=-33554432 && (VALUE) <=33554431) \
2038
+     : (C) == 'O' ? ((VALUE) >=0 && (VALUE) <=0) \
2039
+     : 0 )
2040
+#else
2041
+
2042
+/* The letters I, J, K, L, M, N, and P in a register constraint string
2043
+   can be used to stand for particular ranges of immediate operands.
2044
+   This macro defines what the ranges are.
2045
+   C is the letter, and VALUE is a constant value.
2046
+   Return 1 if VALUE is in the range specified by C.
2047
+
2048
+   `I' is a signed 16-bit constant
2049
+   `J' is a constant with only the high-order 16 bits nonzero
2050
+   `K' is a constant with only the low-order 16 bits nonzero
2051
+   `L' is a signed 16-bit constant shifted left 16 bits
2052
+   `M' is a constant that is greater than 31
2053
+   `N' is a positive constant that is an exact power of two
2054
+   `O' is the constant zero
2055
+   `P' is a constant whose negation is a signed 16-bit constant */
2056
+
2057
+#define CONST_OK_FOR_LETTER_P(VALUE, C)                                        \
2058
+   ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000        \
2059
+   : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
2060
+   : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0          \
2061
+   : (C) == 'L' ? (((VALUE) & 0xffff) == 0                             \
2062
+                  && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0))      \
2063
+   : (C) == 'M' ? (VALUE) > 31                                         \
2064
+   : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0               \
2065
+   : (C) == 'O' ? (VALUE) == 0                                         \
2066
+   : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
2067
+   : 0)
2068
+#endif
2069
+
2070
+/* -----------------------[ PHX stop ]-------------------------------- */
2071
+
2072
+/* Similar, but for floating constants, and defining letters G and H.
2073
+   Here VALUE is the CONST_DOUBLE rtx itself.  */
2074
+
2075
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
2076
+
2077
+/* Given an rtx X being reloaded into a reg required to be
2078
+   in class CLASS, return the class of reg to actually use.
2079
+   In general this is just CLASS; but on some machines
2080
+   in some cases it is preferable to use a more restrictive class.  */
2081
+
2082
+#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
2083
+
2084
+/* Define the codes that are matched by predicates in or32.c.  */
2085
+
2086
+#define PREDICATE_CODES                                                    \
2087
+  {"cc_reg_operand", {SUBREG, REG}},                                      \
2088
+  {"branch_comparison_operator", {EQ, NE, LE, LT, GE,                     \
2089
+                                 GT, LEU, LTU, GEU, GTU,                  \
2090
+                                 UNORDERED, ORDERED,                      \
2091
+                                 UNGE, UNLE }},                           \
2092
+  {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}},                    \
2093
+  {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},                \
2094
+  {"sym_ref_mem_operand", {MEM} },
2095
+
2096
+/* Return the maximum number of consecutive registers
2097
+   needed to represent mode MODE in a register of class CLASS.  */
2098
+/* On the or1k, this is always the size of MODE in words,
2099
+   since all registers are the same size.  */
2100
+#define CLASS_MAX_NREGS(CLASS, MODE)   \
2101
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2102
+
2103
+/* Stack layout; function entry, exit and calling.  */
2104
+
2105
+/* Define this if pushing a word on the stack
2106
+   makes the stack pointer a smaller address.  */
2107
+#define STACK_GROWS_DOWNWARD
2108
+
2109
+/* Define this if the nominal address of the stack frame
2110
+   is at the high-address end of the local variables;
2111
+   that is, each additional local variable allocated
2112
+   goes at a more negative offset in the frame.  */
2113
+#define FRAME_GROWS_DOWNWARD
2114
+
2115
+/* Offset within stack frame to start allocating local variables at.
2116
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2117
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
2118
+   of the first local allocated.  */
2119
+#define STARTING_FRAME_OFFSET 0
2120
+
2121
+/* Offset of first parameter from the argument pointer register value.  */
2122
+#define FIRST_PARM_OFFSET(FNDECL) 0
2123
+
2124
+/* Define this if stack space is still allocated for a parameter passed
2125
+   in a register.  The value is the number of bytes allocated to this
2126
+   area.  */
2127
+/*
2128
+#define REG_PARM_STACK_SPACE(FNDECL) (UNITS_PER_WORD * GP_ARG_NUM_REG)
2129
+*/
2130
+/* Define this if the above stack space is to be considered part of the
2131
+   space allocated by the caller.  */
2132
+/*
2133
+#define OUTGOING_REG_PARM_STACK_SPACE
2134
+*/
2135
+/* Define this macro if `REG_PARM_STACK_SPACE' is defined, but the
2136
+   stack parameters don't skip the area specified by it. */
2137
+/*
2138
+#define STACK_PARMS_IN_REG_PARM_AREA
2139
+*/
2140
+/* Define this if the maximum size of all the outgoing args is to be
2141
+   accumulated and pushed during the prologue.  The amount can be
2142
+   found in the variable current_function_outgoing_args_size.  */
2143
+#define ACCUMULATE_OUTGOING_ARGS 1
2144
+
2145
+/* Value is 1 if returning from a function call automatically
2146
+   pops the arguments described by the number-of-args field in the call.
2147
+   FUNDECL is the declaration node of the function (as a tree),
2148
+   FUNTYPE is the data type of the function (as a tree),
2149
+   or for a library call it is an identifier node for the subroutine name.
2150
+
2151
+   On the Vax, the RET insn always pops all the args for any function.  */
2152
+/* SIMON */
2153
+/*#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)*/
2154
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2155
+
2156
+/* Minimum and maximum general purpose registers used to hold arguments.  */
2157
+#define GP_ARG_MIN_REG 3
2158
+#define GP_ARG_MAX_REG 8
2159
+#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
2160
+
2161
+/* Return registers */
2162
+#define GP_ARG_RETURN 11
2163
+
2164
+/* Define how to find the value returned by a function.
2165
+   VALTYPE is the data type of the value (as a tree).
2166
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
2167
+   otherwise, FUNC is 0.  */
2168
+
2169
+/* Return value is in R11.  */
2170
+#define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2171
+
2172
+/* Define how to find the value returned by a library function
2173
+   assuming the value has mode MODE.  */
2174
+
2175
+/* Return value is in R11.  */
2176
+
2177
+#define LIBCALL_VALUE(MODE)                                             \
2178
+  gen_rtx (REG,                                                                \
2179
+          ((GET_MODE_CLASS (MODE) != MODE_INT                          \
2180
+            || GET_MODE_SIZE (MODE) >= 4)                              \
2181
+           ? (MODE)                                                    \
2182
+           : SImode),                                                  \
2183
+           GP_ARG_RETURN)
2184
+
2185
+/* Define this if PCC uses the nonreentrant convention for returning
2186
+   structure and union values.  */
2187
+
2188
+/*#define PCC_STATIC_STRUCT_RETURN */
2189
+
2190
+/* 1 if N is a possible register number for a function value.
2191
+   R3 to R8 are possible (set to 1 in CALL_USED_REGISTERS)  */
2192
+
2193
+#define FUNCTION_VALUE_REGNO_P(N)  ((N) == GP_ARG_RETURN)
2194
+
2195
+/* 1 if N is a possible register number for function argument passing. */
2196
+
2197
+#define FUNCTION_ARG_REGNO_P(N) \
2198
+   ((N) >= GP_ARG_MIN_REG && (N) <= GP_ARG_MAX_REG)
2199
+
2200
+/* A code distinguishing the floating point format of the target
2201
+   machine.  There are three defined values: IEEE_FLOAT_FORMAT,
2202
+   VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT.  */
2203
+
2204
+#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2205
+#define FLOAT_WORDS_BIG_ENDIAN 1
2206
+
2207
+/* Define a data type for recording info about an argument list
2208
+   during the scan of that argument list.  This data type should
2209
+   hold all necessary information about the function itself
2210
+   and about the args processed so far, enough to enable macros
2211
+   such as FUNCTION_ARG to determine where the next arg should go.
2212
+
2213
+   On the vax, this is a single integer, which is a number of bytes
2214
+   of arguments scanned so far.  */
2215
+
2216
+#define CUMULATIVE_ARGS int
2217
+
2218
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
2219
+   for a call to a function whose data type is FNTYPE.
2220
+   For a library call, FNTYPE is 0.
2221
+
2222
+   On the vax, the offset starts at 0.  */
2223
+
2224
+/* The regs member is an integer, the number of arguments got into
2225
+   registers so far.  */
2226
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2227
+ (CUM = 0)
2228
+
2229
+/* Define intermediate macro to compute the size (in registers) of an argument
2230
+   for the or1k.  */
2231
+
2232
+/* The ROUND_ADVANCE* macros are local to this file.  */
2233
+/* Round SIZE up to a word boundary.  */
2234
+#define ROUND_ADVANCE(SIZE) \
2235
+(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2236
+
2237
+/* Round arg MODE/TYPE up to the next word boundary.  */
2238
+#define ROUND_ADVANCE_ARG(MODE, TYPE) \
2239
+((MODE) == BLKmode                             \
2240
+ ? ROUND_ADVANCE (int_size_in_bytes (TYPE))    \
2241
+ : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
2242
+
2243
+/* Round CUM up to the necessary point for argument MODE/TYPE.  */
2244
+/* This is either rounded to nearest reg or nearest double-reg boundary */
2245
+#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
2246
+((((MODE) == BLKmode ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) \
2247
+  > BITS_PER_WORD)     \
2248
+ ? (((CUM) + 1) & ~1)  \
2249
+ : (CUM))
2250
+
2251
+/* A C expression that indicates when an argument must be passed by
2252
+   reference.  If nonzero for an argument, a copy of that argument is
2253
+   made in memory and a pointer to the argument is passed instead of
2254
+   the argument itself.  The pointer is passed in whatever way is
2255
+   appropriate for passing a pointer to that type.  */
2256
+/* All aggregates and arguments greater than 8 bytes are passed this way.  */
2257
+#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2258
+(TYPE                                  \
2259
+ && (AGGREGATE_TYPE_P (TYPE)           \
2260
+     || int_size_in_bytes (TYPE) > 8))
2261
+
2262
+/* Update the data in CUM to advance over an argument
2263
+   of mode MODE and data type TYPE.
2264
+   (TYPE is null for libcalls where that information may not be available.)  */
2265
+
2266
+/* Update the data in CUM to advance over an argument
2267
+   of mode MODE and data type TYPE.
2268
+   (TYPE is null for libcalls where that information may not be available.)  */
2269
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2270
+((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
2271
+         + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
2272
+
2273
+/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
2274
+   a reg.  This includes arguments that have to be passed by reference as the
2275
+   pointer to them is passed in a reg if one is available (and that is what
2276
+   we're given).
2277
+   When passing arguments NAMED is always 1.  When receiving arguments NAMED
2278
+   is 1 for each argument except the last in a stdarg/varargs function.  In
2279
+   a stdarg function we want to treat the last named arg as named.  In a
2280
+   varargs function we want to treat the last named arg (which is
2281
+   `__builtin_va_alist') as unnamed.
2282
+   This macro is only used in this file.  */
2283
+#define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
2284
+((NAMED)                                                               \
2285
+ && ((ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))                                \
2286
+      + ROUND_ADVANCE_ARG ((MODE), (TYPE))                             \
2287
+      <= GP_ARG_NUM_REG)))
2288
+
2289
+/* Determine where to put an argument to a function.
2290
+   Value is zero to push the argument on the stack,
2291
+   or a hard register in which to store the argument.
2292
+
2293
+   MODE is the argument's machine mode.
2294
+   TYPE is the data type of the argument (as a tree).
2295
+    This is null for libcalls where that information may
2296
+    not be available.
2297
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
2298
+    the preceding args and about the function being called.
2299
+   NAMED is nonzero if this argument is a named parameter
2300
+    (otherwise it is an extra parameter matching an ellipsis).  */
2301
+/* On the ARC the first MAX_ARC_PARM_REGS args are normally in registers
2302
+   and the rest are pushed.  */
2303
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2304
+(PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))                                \
2305
+ ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) + GP_ARG_MIN_REG)    \
2306
+ : 0)
2307
+
2308
+/* For an arg passed partly in registers and partly in memory,
2309
+   this is the number of registers used.
2310
+   For args passed entirely in registers or entirely in memory, zero.  */
2311
+
2312
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)      0
2313
+
2314
+/* Output assembler code to FILE to increment profiler label # LABELNO
2315
+   for profiling a function entry.  */
2316
+
2317
+#define FUNCTION_PROFILER(FILE, LABELNO)  \
2318
+   fprintf (FILE, "\tl.load32u\tr0,LP%d\n\tcall\tmcount\n", (LABELNO));
2319
+
2320
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2321
+   the stack pointer does not matter.  The value is tested only in
2322
+   functions that have frame pointers.
2323
+   No definition is equivalent to always zero.  */
2324
+
2325
+#define EXIT_IGNORE_STACK 0
2326
+
2327
+/* If the memory address ADDR is relative to the frame pointer,
2328
+   correct it to be relative to the stack pointer instead.
2329
+   This is for when we don't use a frame pointer.
2330
+   ADDR should be a variable name.  */
2331
+
2332
+#define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
2333
+{ int offset = -1;                                                     \
2334
+  rtx regs = stack_pointer_rtx;                                                \
2335
+  if (ADDR == frame_pointer_rtx)                                       \
2336
+    offset = 0;                                                                \
2337
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx \
2338
+          && GET_CODE (XEXP (ADDR, 0)) == CONST_INT)                   \
2339
+    offset = INTVAL (XEXP (ADDR, 0));                                  \
2340
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
2341
+          && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)                   \
2342
+    offset = INTVAL (XEXP (ADDR, 1));                                  \
2343
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
2344
+    { rtx other_reg = XEXP (ADDR, 1);                                  \
2345
+      offset = 0;                                                      \
2346
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }    \
2347
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
2348
+    { rtx other_reg = XEXP (ADDR, 0);                                  \
2349
+      offset = 0;                                                      \
2350
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }    \
2351
+  if (offset >= 0)                                                     \
2352
+    { int regno;                                                       \
2353
+      extern char call_used_regs[];                                    \
2354
+      offset += 4; /* I don't know why??? */                           \
2355
+      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)          \
2356
+        if (regs_ever_live[regno] && ! call_used_regs[regno])          \
2357
+          offset += 4;                                                 \
2358
+      ADDR = plus_constant (regs, offset + (DEPTH)); } }
2359
+
2360
+
2361
+/* Addressing modes, and classification of registers for them.  */
2362
+
2363
+/* #define HAVE_POST_INCREMENT */
2364
+/* #define HAVE_POST_DECREMENT */
2365
+
2366
+/* #define HAVE_PRE_DECREMENT */
2367
+/* #define HAVE_PRE_INCREMENT */
2368
+
2369
+/* Macros to check register numbers against specific register classes.  */
2370
+
2371
+#define MAX_REGS_PER_ADDRESS 1
2372
+
2373
+/* True if X is an rtx for a constant that is a valid address.  */
2374
+#define CONSTANT_ADDRESS_P(X)                                          \
2375
+  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF              \
2376
+   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST                \
2377
+   || GET_CODE (X) == HIGH)
2378
+
2379
+#define REGNO_OK_FOR_BASE_P(REGNO)                                          \
2380
+((REGNO) < FIRST_PSEUDO_REGISTER ? ((REGNO) > 0 && (REGNO) <= LAST_INT_REG) \
2381
+ : (reg_renumber[REGNO] > 0 && (reg_renumber[REGNO] <= LAST_INT_REG )))
2382
+
2383
+#ifdef REG_OK_STRICT
2384
+/* Strict version, used in reload pass. This should not
2385
+ * accept pseudo registers.
2386
+ */
2387
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P(REGNO(X))
2388
+#else
2389
+/* Accept an int register or a pseudo reg. */
2390
+#define REG_OK_FOR_BASE_P(X) (REGNO(X) <= LAST_INT_REG || \
2391
+                              REGNO(X) >= FIRST_PSEUDO_REGISTER)
2392
+#endif
2393
+
2394
+/*
2395
+ * OR1K doesn't have any indexed addressing.
2396
+ */
2397
+#define REG_OK_FOR_INDEX_P(X) 0
2398
+#define REGNO_OK_FOR_INDEX_P(X) 0
2399
+
2400
+#define LEGITIMATE_ADDRESS_INTEGER_P(X,OFFSET)          \
2401
+ (GET_CODE (X) == CONST_INT && SMALL_INT(X))
2402
+
2403
+#define LEGITIMATE_OFFSET_ADDRESS_P(MODE,X)             \
2404
+ (GET_CODE (X) == PLUS                                  \
2405
+  && GET_CODE (XEXP (X, 0)) == REG                      \
2406
+  && REG_OK_FOR_BASE_P (XEXP (X, 0))                    \
2407
+  && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)      \
2408
+  && (((MODE) != DFmode && (MODE) != DImode)            \
2409
+      || LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4)))
2410
+
2411
+#define LEGITIMATE_NONOFFSET_ADDRESS_P(MODE,X)          \
2412
+             (GET_CODE(X) == REG && REG_OK_FOR_BASE_P(X))
2413
+/*
2414
+ * OR1K only has one addressing mode:
2415
+ * register + 16 bit signed offset.
2416
+ */
2417
+#define GO_IF_LEGITIMATE_ADDRESS(MODE,X,ADDR)           \
2418
+  if(LEGITIMATE_OFFSET_ADDRESS_P(MODE,X)) goto ADDR;    \
2419
+  if(LEGITIMATE_NONOFFSET_ADDRESS_P(MODE,X)) goto ADDR;
2420
+
2421
+/*
2422
+  if(GET_CODE(X) == SYMBOL_REF) goto ADDR;  */ /* If used, smaller code */
2423
+
2424
+/* Alternative */
2425
+#if 0
2426
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
2427
+{                                                                       \
2428
+  if (GET_CODE (X) == REG) goto ADDR;                                   \
2429
+  if (GET_CODE (X) == SYMBOL_REF) goto ADDR;                           \
2430
+  if (CONSTANT_ADDRESS_P (X)) goto ADDR;                                \
2431
+  if (GET_CODE (X) == PLUS)                                             \
2432
+    {                                                                   \
2433
+      /* Handle [index]<address> represented with index-sum outermost */\
2434
+      if (GET_CODE (XEXP (X, 0)) == REG                                 \
2435
+          && REG_OK_FOR_BASE_P (XEXP (X, 0))                            \
2436
+          && GET_CODE (XEXP (X, 1)) == CONST_INT)                       \
2437
+        goto ADDR;                                                      \
2438
+      if (GET_CODE (XEXP (X, 1)) == REG                                 \
2439
+          && REG_OK_FOR_BASE_P (XEXP (X, 0))                            \
2440
+          && GET_CODE (XEXP (X, 0)) == CONST_INT)                       \
2441
+        goto ADDR;                                                      \
2442
+    }                                                                   \
2443
+ }
2444
+#endif
2445
+/*
2446
+ * We have to force symbol_ref's into registers here
2447
+ * because nobody else seems to want to do that!
2448
+ */
2449
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
2450
+/*
2451
+{ if (GET_CODE (x) == SYMBOL_REF)                               \
2452
+    (X) = copy_to_reg (X);                                      \
2453
+  if (memory_address_p (MODE, X))                               \
2454
+    goto WIN;                                                   \
2455
+}
2456
+*/
2457
+
2458
+/*
2459
+ * OR1K addresses do not depend on the machine mode they are
2460
+ * being used in.
2461
+ */
2462
+#define GO_IF_MODE_DEPENDENT_ADDRESS(addr,label)
2463
+
2464
+/* OR1K has 16 bit immediates.
2465
+ */
2466
+#define SMALL_INT(X) (INTVAL(X) >= -32768 && INTVAL(X) <= 32767)
2467
+
2468
+#define LEGITIMATE_CONSTANT_P(x) (GET_CODE(x) != CONST_DOUBLE)
2469
+
2470
+/* Specify the machine mode that this machine uses
2471
+   for the index in the tablejump instruction.  */
2472
+#define CASE_VECTOR_MODE SImode
2473
+
2474
+/* Define as C expression which evaluates to nonzero if the tablejump
2475
+   instruction expects the table to contain offsets from the address of the
2476
+   table.
2477
+   Do not define this if the table should contain absolute addresses. */
2478
+/* #define CASE_VECTOR_PC_RELATIVE 1 */
2479
+
2480
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
2481
+#define DEFAULT_SIGNED_CHAR 1
2482
+
2483
+/* This flag, if defined, says the same insns that convert to a signed fixnum
2484
+   also convert validly to an unsigned one.  */
2485
+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
2486
+
2487
+/* Max number of bytes we can move from memory to memory
2488
+   in one reasonably fast instruction.  */
2489
+#define MOVE_MAX 4
2490
+
2491
+/* Define this if zero-extension is slow (more than one real instruction).  */
2492
+/* #define SLOW_ZERO_EXTEND */
2493
+
2494
+/* Nonzero if access to memory by bytes is slow and undesirable.
2495
+   For RISC chips, it means that access to memory by bytes is no
2496
+   better than access by words when possible, so grab a whole word
2497
+   and maybe make use of that.  */
2498
+#define SLOW_BYTE_ACCESS 1
2499
+
2500
+/* Define if shifts truncate the shift count
2501
+   which implies one can omit a sign-extension or zero-extension
2502
+   of a shift count.  */
2503
+/* #define SHIFT_COUNT_TRUNCATED */
2504
+
2505
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2506
+   is done just by pretending it is already truncated.  */
2507
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2508
+
2509
+/* Specify the machine mode that pointers have.
2510
+   After generation of rtl, the compiler makes no further distinction
2511
+   between pointers and any other objects of this machine mode.  */
2512
+#define Pmode SImode
2513
+
2514
+/* A function address in a call instruction
2515
+   is a byte address (for indexing purposes)
2516
+   so give the MEM rtx a byte's mode.  */
2517
+#define FUNCTION_MODE SImode
2518
+
2519
+/* Compute the cost of computing a constant rtl expression RTX
2520
+   whose rtx-code is CODE.  The body of this macro is a portion
2521
+   of a switch statement.  If the code is computed here,
2522
+   return it with a return statement.  Otherwise, break from the switch.  */
2523
+#if 0
2524
+__PHX__ cleanup
2525
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2526
+  case CONST_INT:                                              \
2527
+    /* Constant zero is super cheap due to clr instruction.  */        \
2528
+    if (RTX == const0_rtx) return 0;                           \
2529
+    if ((unsigned) INTVAL (RTX) < 077) return 1;               \
2530
+  case CONST:                                                  \
2531
+  case LABEL_REF:                                              \
2532
+  case SYMBOL_REF:                                             \
2533
+    return 3;                                                  \
2534
+  case CONST_DOUBLE:                                           \
2535
+    return 5;
2536
+#endif
2537
+
2538
+
2539
+/* Given a comparison code (EQ, NE, etc.) and the first operand of a
2540
+   COMPARE, return the mode to be used for the comparison.
2541
+*/
2542
+
2543
+#define SELECT_CC_MODE(OP, X, Y) or32_cc_mode ((OP), (X), (Y))
2544
+
2545
+/* Can the condition code MODE be safely reversed?  This is safe in
2546
+   all cases on this port, because at present it doesn't use the
2547
+   trapping FP comparisons (fcmpo).  */
2548
+#define REVERSIBLE_CC_MODE(MODE) 1
2549
+
2550
+/* Given a condition code and a mode, return the inverse condition.  */
2551
+#define REVERSE_CONDITION(CODE, MODE) or32_reverse_condition (MODE, CODE)
2552
+
2553
+
2554
+/* Control the assembler format that we output.  */
2555
+
2556
+/* A C string constant describing how to begin a comment in the target
2557
+   assembler language.  The compiler assumes that the comment will end at
2558
+   the end of the line.  */
2559
+#define ASM_COMMENT_START "#"
2560
+
2561
+/* Output at beginning of assembler file.  */
2562
+/*
2563
+__PHX__ clenup
2564
+#ifndef ASM_FILE_START
2565
+#define ASM_FILE_START(FILE) do {\
2566
+fprintf (FILE, "%s file %s\n", ASM_COMMENT_START, main_input_filename);\
2567
+fprintf (FILE, ".file\t");   \
2568
+  output_quoted_string (FILE, main_input_filename);\
2569
+  fputc ('\n', FILE);} while (0)
2570
+#endif
2571
+*/
2572
+/* Output to assembler file text saying following lines
2573
+   may contain character constants, extra white space, comments, etc.  */
2574
+
2575
+#define ASM_APP_ON ""
2576
+
2577
+/* Output to assembler file text saying following lines
2578
+   no longer contain unusual constructs.  */
2579
+
2580
+#define ASM_APP_OFF ""
2581
+
2582
+/* Switch to the text or data segment.  */
2583
+
2584
+/* Output before read-only data.  */
2585
+#define TEXT_SECTION_ASM_OP ".section .text"
2586
+
2587
+/* Output before writable data.  */
2588
+#define DATA_SECTION_ASM_OP ".section .data"
2589
+
2590
+/* Output before uninitialized data. */
2591
+#define BSS_SECTION_ASM_OP  ".section .bss"
2592
+
2593
+/* How to refer to registers in assembler output.
2594
+   This sequence is indexed by compiler's hard-register-number (see above).  */
2595
+
2596
+#define REGISTER_NAMES \
2597
+{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" \
2598
+, "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", "cc-flag"}
2599
+
2600
+
2601
+/* Define this to be the delimiter between SDB sub-sections.  The default
2602
+   is ";".  */
2603
+#define SDB_DELIM       "\n"
2604
+
2605
+/* Do not break .stabs pseudos into continuations.  */
2606
+#define DBX_CONTIN_LENGTH 0
2607
+
2608
+/* Don't try to use the  type-cross-reference character in DBX data.
2609
+   Also has the consequence of putting each struct, union or enum
2610
+   into a separate .stabs, containing only cross-refs to the others.  */
2611
+#define DBX_NO_XREFS
2612
+
2613
+/* How to renumber registers for dbx and gdb.
2614
+   Vax needs no change in the numeration.  */
2615
+
2616
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2617
+
2618
+/* This is the char to use for continuation (in case we need to turn
2619
+   continuation back on).  */
2620
+
2621
+#define DBX_CONTIN_CHAR '?'
2622
+
2623
+
2624
+
2625
+
2626
+
2627
+/* Node: Label Output */
2628
+
2629
+/* Globalizing directive for a label.  */
2630
+#define GLOBAL_ASM_OP "\t.global "
2631
+
2632
+#define SUPPORTS_WEAK 1
2633
+
2634
+/* This is how to output the definition of a user-level label named NAME,
2635
+   such as the label on a static function or variable NAME.  */
2636
+
2637
+#define ASM_OUTPUT_LABEL(FILE,NAME)    \
2638
+ { assemble_name (FILE, NAME); fputs (":\n", FILE); }
2639
+#if 0
2640
+/* This is how to output a command to make the user-level label named NAME
2641
+   defined for reference from other files.  */
2642
+/*
2643
+ __PHX__ CLEANUP
2644
+#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2645
+ { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE); }
2646
+*/
2647
+
2648
+/* SIMON */
2649
+/*#define ASM_OUTPUT_LABELREF(stream,name)                \
2650
+ { fputc('_',stream); fputs(name,stream); }
2651
+*/
2652
+#define ASM_OUTPUT_LABELREF(stream,name)                \
2653
+{if(name[0] == '*')                                    \
2654
+   fputs(name,stream);                                 \
2655
+else {                                                 \
2656
+   fputc('_',stream); fputs(name,stream);              \
2657
+}}
2658
+#endif
2659
+
2660
+/* The prefix to add to user-visible assembler symbols. */
2661
+
2662
+/* Remove any previous definition (elfos.h).  */
2663
+/* We use -fno-leading-underscore to remove it, when necessary.  */
2664
+#undef  USER_LABEL_PREFIX
2665
+#define USER_LABEL_PREFIX "_"
2666
+
2667
+/* Remove any previous definition (elfos.h).  */
2668
+#ifndef ASM_GENERATE_INTERNAL_LABEL
2669
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)        \
2670
+  sprintf (LABEL, "*%s%d", PREFIX, NUM)
2671
+#endif
2672
+
2673
+/* This is how to output an assembler line defining an `int' constant.  */
2674
+
2675
+#define ASM_OUTPUT_INT(FILE,VALUE)     \
2676
+(                                      \
2677
+       fprintf (FILE, "\t.word "),     \
2678
+  output_addr_const (FILE, (VALUE)),   \
2679
+  fprintf (FILE, "\n"))
2680
+
2681
+#define ASM_OUTPUT_FLOAT(stream,value) \
2682
+   { long l;                                 \
2683
+      REAL_VALUE_TO_TARGET_SINGLE(value,l); \
2684
+      fprintf(stream,"\t.word 0x%08x\t\n# float %26.7e\n",l,value); }
2685
+
2686
+#define ASM_OUTPUT_DOUBLE(stream,value)                         \
2687
+   { long l[2];                                                 \
2688
+      REAL_VALUE_TO_TARGET_DOUBLE(value,&l[0]);                 \
2689
+      fprintf(stream,"\t.word 0x%08x,0x%08x\t\n# float %26.16le\n",  \
2690
+              l[0],l[1],value); }
2691
+
2692
+#define ASM_OUTPUT_LONG_DOUBLE(stream,value) \
2693
+   { long l[4];                                 \
2694
+      REAL_VALUE_TO_TARGET_DOUBLE(value,&l[0]); \
2695
+      fprintf(stream,"\t.word 0x%08x,0x%08x,0x%08x,0x%08x\t\n# float %26.18lle\n", \
2696
+              l[0],l[1],l[2],l[3],value); }
2697
+
2698
+/* Likewise for `char' and `short' constants.  */
2699
+
2700
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
2701
+( fprintf (FILE, "\t.half "),                  \
2702
+  output_addr_const (FILE, (VALUE)),           \
2703
+  fprintf (FILE, "\n"))
2704
+
2705
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
2706
+( fprintf (FILE, "\t.byte "),                  \
2707
+  output_addr_const (FILE, (VALUE)),           \
2708
+  fprintf (FILE, "\n"))
2709
+
2710
+/* This is how to output an assembler line for a numeric constant byte.  */
2711
+
2712
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
2713
+  fprintf (FILE, "\t.byte 0x%02x\n", (VALUE))
2714
+
2715
+/* This is how to output an insn to push a register on the stack.
2716
+   It need not be very fast code.  */
2717
+
2718
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
2719
+  fprintf (FILE, "\tl.sub   \tr1,4\n\tl.sw    \t0(r1),%s\n", reg_names[REGNO])
2720
+
2721
+/* This is how to output an insn to pop a register from the stack.
2722
+   It need not be very fast code.  */
2723
+
2724
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
2725
+  fprintf (FILE, "\tl.lwz   \t%s,0(r1)\n\tl.addi   \tr1,4\n", reg_names[REGNO])
2726
+
2727
+/* This is how to output an element of a case-vector that is absolute.
2728
+   (The Vax does not use such vectors,
2729
+   but we must define this macro anyway.)  */
2730
+
2731
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
2732
+  fprintf (FILE, "\t.word .L%d\n", VALUE)
2733
+
2734
+/* This is how to output an element of a case-vector that is relative.  */
2735
+
2736
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
2737
+  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
2738
+
2739
+/* This is how to output an assembler line
2740
+   that says to advance the location counter
2741
+   to a multiple of 2**LOG bytes.  */
2742
+
2743
+#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
2744
+  if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG))
2745
+
2746
+/* This is how to output an assembler line
2747
+   that says to advance the location counter by SIZE bytes.  */
2748
+
2749
+#ifndef ASM_OUTPUT_SKIP
2750
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
2751
+  fprintf (FILE, "\t.space %d\n", (SIZE))
2752
+#endif
2753
+
2754
+/* Need to split up .ascii directives to avoid breaking
2755
+   the linker. */
2756
+
2757
+/* This is how to output a string.  */
2758
+#ifndef ASM_OUTPUT_ASCII
2759
+#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN)                           \
2760
+do {                                                                    \
2761
+  register int i, c, len = (LEN), cur_pos = 17;                         \
2762
+  register unsigned char *string = (unsigned char *)(STRING);           \
2763
+  fprintf ((STREAM), "\t.ascii\t\"");                                   \
2764
+  for (i = 0; i < len; i++)                                             \
2765
+    {                                                                   \
2766
+      register int c = string[i];                                       \
2767
+                                                                        \
2768
+      switch (c)                                                        \
2769
+        {                                                               \
2770
+        case '\"':                                                      \
2771
+        case '\\':                                                      \
2772
+          putc ('\\', (STREAM));                                        \
2773
+          putc (c, (STREAM));                                           \
2774
+          cur_pos += 2;                                                 \
2775
+          break;                                                        \
2776
+                                                                        \
2777
+        case TARGET_NEWLINE:                                            \
2778
+          fputs ("\\n", (STREAM));                                      \
2779
+          if (i+1 < len                                                 \
2780
+              && (((c = string[i+1]) >= '\040' && c <= '~')             \
2781
+                  || c == TARGET_TAB))                                  \
2782
+            cur_pos = 32767;            /* break right here */          \
2783
+          else                                                          \
2784
+            cur_pos += 2;                                               \
2785
+          break;                                                        \
2786
+                                                                        \
2787
+        case TARGET_TAB:                                                \
2788
+          fputs ("\\t", (STREAM));                                      \
2789
+          cur_pos += 2;                                                 \
2790
+          break;                                                        \
2791
+                                                                        \
2792
+        case TARGET_FF:                                                 \
2793
+          fputs ("\\f", (STREAM));                                      \
2794
+          cur_pos += 2;                                                 \
2795
+          break;                                                        \
2796
+                                                                        \
2797
+        case TARGET_BS:                                                 \
2798
+          fputs ("\\b", (STREAM));                                      \
2799
+          cur_pos += 2;                                                 \
2800
+          break;                                                        \
2801
+                                                                        \
2802
+        case TARGET_CR:                                                 \
2803
+          fputs ("\\r", (STREAM));                                      \
2804
+          cur_pos += 2;                                                 \
2805
+          break;                                                        \
2806
+                                                                        \
2807
+        default:                                                        \
2808
+          if (c >= ' ' && c < 0177)                                     \
2809
+            {                                                           \
2810
+              putc (c, (STREAM));                                       \
2811
+              cur_pos++;                                                \
2812
+            }                                                           \
2813
+          else                                                          \
2814
+            {                                                           \
2815
+              fprintf ((STREAM), "\\%03o", c);                          \
2816
+              cur_pos += 4;                                             \
2817
+            }                                                           \
2818
+        }                                                               \
2819
+                                                                        \
2820
+      if (cur_pos > 72 && i+1 < len)                                    \
2821
+        {                                                               \
2822
+          cur_pos = 17;                                                 \
2823
+          fprintf ((STREAM), "\"\n\t.ascii\t\"");                       \
2824
+        }                                                               \
2825
+    }                                                                   \
2826
+  fprintf ((STREAM), "\"\n");                                           \
2827
+} while (0)
2828
+#endif /* ASM_OUTPUT_ASCII */
2829
+
2830
+/* Invoked just before function output. */
2831
+
2832
+#define ASM_OUTPUT_FUNCTION_PREFIX(stream, fnname)              \
2833
+  fputs(".proc ",stream); assemble_name(stream,fnname);         \
2834
+  fputs("\n",stream);
2835
+
2836
+/* This says how to output an assembler line
2837
+   to define a global common symbol.  */
2838
+
2839
+#define ASM_OUTPUT_COMMON(stream,name,size,rounded)             \
2840
+{ data_section();                                               \
2841
+  fputs(".global\t",stream); assemble_name(stream,name);        \
2842
+  fputs("\n",stream); assemble_name(stream,name);               \
2843
+  fprintf(stream,":\n\t.space %d\n",rounded); }
2844
+
2845
+/* This says how to output an assembler line
2846
+   to define a local common symbol.  */
2847
+
2848
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
2849
+( fputs (".bss ", (FILE)),                     \
2850
+  assemble_name ((FILE), (NAME)),              \
2851
+  fprintf ((FILE), ",%d,%d\n", (SIZE),(ROUNDED)))
2852
+
2853
+/* This says how to output an assembler line to define a global common symbol
2854
+   with size SIZE (in bytes) and alignment ALIGN (in bits).  */
2855
+#ifndef ASM_OUTPUT_ALIGNED_COMMON
2856
+#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)     \
2857
+{ data_section();                                              \
2858
+  if ((ALIGN) > 8)                                             \
2859
+       fprintf(FILE, "\t.align %d\n", ((ALIGN) / BITS_PER_UNIT)); \
2860
+  fputs(".global\t", FILE); assemble_name(FILE, NAME);         \
2861
+  fputs("\n", FILE);                                           \
2862
+  assemble_name(FILE, NAME);                                   \
2863
+  fprintf(FILE, ":\n\t.space %d\n", SIZE);                     \
2864
+}
2865
+#endif /* ASM_OUTPUT_ALIGNED_COMMON */
2866
+
2867
+/* This says how to output an assembler line to define a local common symbol
2868
+   with size SIZE (in bytes) and alignment ALIGN (in bits).  */
2869
+
2870
+#ifndef ASM_OUTPUT_ALIGNED_LOCAL
2871
+#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
2872
+{ data_section();                                               \
2873
+  if ((ALIGN) > 8)                                              \
2874
+       fprintf(FILE, "\t.align %d\n", ((ALIGN) / BITS_PER_UNIT)); \
2875
+  assemble_name(FILE, NAME);                                    \
2876
+  fprintf(FILE, ":\n\t.space %d\n", SIZE);                     \
2877
+}
2878
+#endif /* ASM_OUTPUT_ALIGNED_LOCAL */
2879
+
2880
+/* Store in OUTPUT a string (made with alloca) containing
2881
+   an assembler-name for a local static variable named NAME.
2882
+   LABELNO is an integer which is different for each call.  */
2883
+
2884
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2885
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),   \
2886
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2887
+
2888
+/* Macro for %code validation. Returns nonzero if valid. */
2889
+#define PRINT_OPERAND_PUNCT_VALID_P(code) print_operand_punct_valid_p(code)
2890
+
2891
+/* Print an instruction operand X on file FILE.
2892
+   CODE is the code from the %-spec that requested printing this operand;
2893
+   if `%z3' was used to print operand 3, then CODE is 'z'.  */
2894
+
2895
+#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
2896
+
2897
+/* Print a memory operand whose address is X, on file FILE.
2898
+   This uses a function in output-vax.c.  */
2899
+
2900
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2901
+
2902
+/* These are stubs, and have yet to bee written. */
2903
+
2904
+#define TRAMPOLINE_SIZE 26
2905
+#define TRAMPOLINE_TEMPLATE(FILE)
2906
+#define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT)
2907
+
2908
+extern GTY(()) rtx or32_compare_op0;
2909
+extern GTY(()) rtx or32_compare_op1;
2910
+
2911
+/* We don't use libg.a */
2912
+#undef LIB_SPEC
2913
+#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
2914
+#endif /* _OR32_H_ */
2915
diff -Nru gcc-3.4.4.orig/gcc/config/or32/or32.md gcc-3.4.4-DONE/gcc/config/or32/or32.md
2916
--- gcc-3.4.4.orig/gcc/config/or32/or32.md      1970-01-01 02:00:00.000000000 +0200
2917
+++ gcc-3.4.4-DONE/gcc/config/or32/or32.md      2005-11-29 16:23:09.000000000 +0200
2918
@@ -0,0 +1,1281 @@
2919
+;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
2920
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
2921
+;; Contributed by Damjan Lampret <damjanl@bsemi.com> in 1999.
2922
+;; Major optimizations by Matjaz Breskvar <matjazb@bsemi.com> in 2005.
2923
+
2924
+;; This file is part of GNU CC.
2925
+
2926
+;; GNU CC is free software; you can redistribute it and/or modify
2927
+;; it under the terms of the GNU General Public License as published by
2928
+;; the Free Software Foundation; either version 1, or (at your option)
2929
+;; any later version.
2930
+
2931
+;; GNU CC is distributed in the hope that it will be useful,
2932
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
2933
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2934
+;; GNU General Public License for more details.
2935
+
2936
+;; You should have received a copy of the GNU General Public License
2937
+;; along with GNU CC; see the file COPYING.  If not, write to
2938
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
2939
+;; Boston, MA 02111-1307, USA.
2940
+
2941
+(define_attr "type"
2942
+  "unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
2943
+  (const_string "unknown"))
2944
+
2945
+;; Number of instructions
2946
+(define_attr "length" "" (const_int 1))
2947
+
2948
+(define_delay (eq_attr "type" "branch,jump")
2949
+               [(and (eq_attr "type" "!branch,jump")
2950
+                    (eq_attr "length" "1")) (nil) (nil)])
2951
+
2952
+;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
2953
+;;                       TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
2954
+;; MULTIPLICITY - Number of functional units of this type
2955
+;; SIMULTANEITY - Zero for pipelined functional unit
2956
+;; READY-DELAY - Number of cycles before result is available
2957
+;; ISSUE-DELAY - Number of cycles before unit can accept new instruction
2958
+;;
2959
+(define_function_unit "bit_unit" 1 0 (eq_attr "type" "shift") 3 1)
2960
+(define_function_unit "lsu" 1 0 (eq_attr "type" "load") 3 3)
2961
+(define_function_unit "lsu" 1 0 (eq_attr "type" "store") 2 1)
2962
+(define_function_unit "alu" 1 0 (eq_attr "type" "add,logic,extend,move,compare") 2 1)
2963
+(define_function_unit "mul_unit" 1 0 (eq_attr "type" "mul") 16 16)
2964
+
2965
+
2966
+;; Called after register allocation to add any instructions needed for the
2967
+;; prologue.  Using a prologue insn is favored compared to putting all of the
2968
+;; instructions in output_function_prologue(), since it allows the scheduler
2969
+;; to intermix instructions with the saves of the caller saved registers.  In
2970
+;; some cases, it might be necessary to emit a barrier instruction as the last
2971
+;; insn to prevent such scheduling.
2972
+
2973
+(define_expand "prologue"
2974
+  [(use (const_int 1))]
2975
+  "TARGET_SCHED_LOGUE"
2976
+{
2977
+  or32_expand_prologue ();
2978
+  DONE;
2979
+})
2980
+
2981
+;; Called after register allocation to add any instructions needed for the
2982
+;; epilogue.  Using an epilogue insn is favored compared to putting all of the
2983
+;; instructions in output_function_epilogue(), since it allows the scheduler
2984
+;; to intermix instructions with the restores of the caller saved registers.
2985
+;; In some cases, it might be necessary to emit a barrier instruction as the
2986
+;; first insn to prevent such scheduling.
2987
+(define_expand "epilogue"
2988
+  [(use (const_int 2))]
2989
+  "TARGET_SCHED_LOGUE"
2990
+{
2991
+  or32_expand_epilogue (false);
2992
+  DONE;
2993
+})
2994
+
2995
+(define_expand "sibcall_epilogue"
2996
+  [(use (const_int 2))]
2997
+  "TARGET_SCHED_LOGUE"
2998
+{
2999
+  or32_expand_epilogue (true);
3000
+  DONE;
3001
+})
3002
+
3003
+(define_insn "return_internal"
3004
+  [(return)
3005
+   (use (match_operand 0 "pmode_register_operand" ""))]
3006
+  "TARGET_SCHED_LOGUE"
3007
+  "l.jr    \t%0%("
3008
+  [(set_attr "type" "jump")
3009
+   (set_attr "length" "1")])
3010
+
3011
+;;
3012
+;; Sibcalls
3013
+;;
3014
+
3015
+(define_expand "sibcall"
3016
+  [(parallel [(call (match_operand 0 "" "")
3017
+                    (match_operand 1 "" ""))
3018
+              (use (match_operand 2 "" ""))     ;; next_arg_reg
3019
+              (use (match_operand 3 "" ""))])]  ;; struct_value_size_rtx
3020
+  "TARGET_SIBCALL"
3021
+  "
3022
+{
3023
+  or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
3024
+  DONE;
3025
+}")
3026
+
3027
+(define_expand "sibcall_value"
3028
+  [(set (match_operand 0 "" "")
3029
+                   (call (match_operand:SI 1 "" "")
3030
+                         (match_operand 2 "" "")))]
3031
+  "TARGET_SIBCALL"
3032
+  "
3033
+{
3034
+  or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
3035
+  DONE;
3036
+}")
3037
+
3038
+(define_insn "sibcall_internal"
3039
+  [(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,r"))
3040
+         (match_operand 1 "" ""))
3041
+   (use (reg:SI 9))]
3042
+  "TARGET_SIBCALL"
3043
+  "@
3044
+   l.j     \t%S0%(\t    # sibcall s
3045
+   l.jr    \t%0%(\t     # sibcall r"
3046
+  [(set_attr "type" "jump,jump")])
3047
+
3048
+
3049
+
3050
+;;
3051
+;; movQI
3052
+;;
3053
+
3054
+(define_expand "movqi"
3055
+  [(set (match_operand:QI 0 "general_operand" "")
3056
+       (match_operand:QI 1 "general_operand" ""))]
3057
+  ""
3058
+  "
3059
+      if (!no_new_pseudos)
3060
+        {
3061
+          if (GET_CODE (operands[1]) == CONST_INT)
3062
+           {
3063
+             rtx reg = gen_reg_rtx (SImode);
3064
+
3065
+             emit_insn (gen_movsi (reg, operands[1]));
3066
+             operands[1] = gen_lowpart (QImode, reg);
3067
+           }
3068
+         if (GET_CODE (operands[1]) == MEM && optimize > 0)
3069
+           {
3070
+             rtx reg = gen_reg_rtx (SImode);
3071
+
3072
+             emit_insn (gen_rtx_SET (SImode, reg,
3073
+                                 gen_rtx_ZERO_EXTEND (SImode,
3074
+                                                      operands[1])));
3075
+
3076
+             operands[1] = gen_lowpart (QImode, reg);
3077
+           }
3078
+          if (GET_CODE (operands[0]) != REG)
3079
+           operands[1] = force_reg (QImode, operands[1]);
3080
+        }
3081
+")
3082
+
3083
+(define_insn "*movqi_internal"
3084
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=m,r,r,r,r")
3085
+       (match_operand:QI 1 "general_operand"       "r,r,I,K,m"))]
3086
+  ""
3087
+  "@
3088
+   l.sb    \t%0,%1\t    # movqi
3089
+   l.ori   \t%0,%1,0\t  # movqi: move reg to reg
3090
+   l.addi  \t%0,r0,%1\t # movqi: move immediate
3091
+   l.ori   \t%0,r0,%1\t # movqi: move immediate
3092
+   l.lbz   \t%0,%1\t    # movqi"
3093
+  [(set_attr "type" "store,add,add,logic,load")])
3094
+
3095
+
3096
+;;
3097
+;; movHI
3098
+;;
3099
+
3100
+(define_expand "movhi"
3101
+  [(set (match_operand:HI 0 "general_operand" "")
3102
+       (match_operand:HI 1 "general_operand" ""))]
3103
+  ""
3104
+  "
3105
+      if (!no_new_pseudos)
3106
+        {
3107
+          if (GET_CODE (operands[1]) == CONST_INT)
3108
+           {
3109
+             rtx reg = gen_reg_rtx (SImode);
3110
+
3111
+             emit_insn (gen_movsi (reg, operands[1]));
3112
+             operands[1] = gen_lowpart (HImode, reg);
3113
+           }
3114
+         if (GET_CODE (operands[1]) == MEM && optimize > 0)
3115
+           {
3116
+             rtx reg = gen_reg_rtx (SImode);
3117
+
3118
+             emit_insn (gen_rtx_SET (SImode, reg,
3119
+                                     gen_rtx_ZERO_EXTEND (SImode,
3120
+                                                          operands[1])));
3121
+             operands[1] = gen_lowpart (HImode, reg);
3122
+           }
3123
+          if (GET_CODE (operands[0]) != REG)
3124
+           operands[1] = force_reg (HImode, operands[1]);
3125
+        }
3126
+")
3127
+
3128
+(define_insn "*movhi_internal"
3129
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r,r,r,r")
3130
+       (match_operand:HI 1 "general_operand"       "r,r,I,K,m"))]
3131
+  ""
3132
+  "@
3133
+   l.sh    \t%0,%1\t # movhi
3134
+   l.ori   \t%0,%1,0\t # movhi: move reg to reg
3135
+   l.addi  \t%0,r0,%1\t # movhi: move immediate
3136
+   l.ori   \t%0,r0,%1\t # movhi: move immediate
3137
+   l.lhz   \t%0,%1\t # movhi"
3138
+  [(set_attr "type" "store,add,add,logic,load")])
3139
+
3140
+(define_expand "movsi"
3141
+  [(set (match_operand:SI 0 "general_operand" "")
3142
+       (match_operand:SI 1 "general_operand" ""))]
3143
+  ""
3144
+{
3145
+  /* Working with CONST_INTs is easier, so convert
3146
+     a double if needed.  */
3147
+
3148
+     if (GET_CODE (operands[1]) == CONST_DOUBLE) {
3149
+          operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
3150
+  }
3151
+
3152
+  /* Handle sets of MEM first.  */
3153
+  if (GET_CODE (operands[0]) == MEM)
3154
+  {
3155
+   if (register_operand(operands[1], SImode)
3156
+                      || (operands[1] == const0_rtx))
3157
+       goto movsi_is_ok;
3158
+
3159
+      if (! reload_in_progress)
3160
+       {
3161
+         operands[0] = validize_mem (operands[0]);
3162
+         operands[1] = force_reg (SImode, operands[1]);
3163
+       }
3164
+    }
3165
+
3166
+  /* This makes sure we will not get rematched due to splittage.  */
3167
+  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
3168
+    ;
3169
+  else if (CONSTANT_P (operands[1])
3170
+          && GET_CODE (operands[1]) != HIGH
3171
+          && GET_CODE (operands[1]) != LO_SUM)
3172
+    {
3173
+      or32_emit_set_const32 (operands[0], operands[1]);
3174
+      DONE;
3175
+    }
3176
+ movsi_is_ok:
3177
+  ;
3178
+})
3179
+
3180
+;;
3181
+;; movSI
3182
+;;
3183
+
3184
+(define_insn "*movsi_insn"
3185
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
3186
+       (match_operand:SI 1 "input_operand"       "I,K,M,r,m,r"))]
3187
+  "(register_operand (operands[0], SImode)
3188
+    || register_operand (operands[1], SImode)
3189
+    || (operands[1] == const0_rtx))"
3190
+  "@
3191
+   l.addi  \t%0,r0,%1\t # move immediate I
3192
+   l.ori   \t%0,r0,%1\t # move immediate K
3193
+   l.movhi \t%0,hi(%1)\t # move immediate M
3194
+   l.ori   \t%0,%1,0\t # move reg to reg
3195
+   l.lwz   \t%0,%1\t # SI load
3196
+   l.sw    \t%0,%1\t # SI store"
3197
+  [(set_attr "type" "add,load,store,add,logic,move")
3198
+   (set_attr "length" "1,1,1,1,1,1")])
3199
+
3200
+(define_insn "*movsi_lo_sum"
3201
+  [(set (match_operand:SI 0 "register_operand" "=r")
3202
+       (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3203
+                   (match_operand:SI 2 "immediate_operand" "i")))]
3204
+  ""
3205
+  "l.ori   \t%0,%1,lo(%2)"
3206
+ [(set_attr "type" "logic")
3207
+   (set_attr "length" "1")])
3208
+
3209
+(define_insn "*movsi_high"
3210
+  [(set (match_operand:SI 0 "register_operand" "=r")
3211
+       (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
3212
+  ""
3213
+  "l.movhi  \t%0,hi(%1)"
3214
+[(set_attr "type" "move")
3215
+   (set_attr "length" "1")])
3216
+
3217
+(define_insn "movsi_insn_big"
3218
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
3219
+       (match_operand:SI 1 "immediate_operand" "i"))]
3220
+  "GET_CODE(operands[1]) != CONST_INT"
3221
+  "l.movhi \t%0,hi(%1)\;l.ori   \t%0,%0,lo(%1)"
3222
+  [(set_attr "type" "move")
3223
+   (set_attr "length" "2")])
3224
+
3225
+
3226
+;;
3227
+;; Conditional Branches & Moves
3228
+;;
3229
+
3230
+(define_expand "addsicc"
3231
+  [(match_operand:SI 0 "register_operand" "")
3232
+   (match_operand 1 "comparison_operator" "")
3233
+   (match_operand:SI 2 "register_operand" "")
3234
+   (match_operand:SI 3 "register_operand" "")]
3235
+  ""
3236
+  "FAIL;")
3237
+
3238
+(define_expand "addhicc"
3239
+  [(match_operand:HI 0 "register_operand" "")
3240
+   (match_operand 1 "comparison_operator" "")
3241
+   (match_operand:HI 2 "register_operand" "")
3242
+   (match_operand:HI 3 "register_operand" "")]
3243
+  ""
3244
+  "FAIL;")
3245
+
3246
+(define_expand "addqicc"
3247
+  [(match_operand:QI 0 "register_operand" "")
3248
+   (match_operand 1 "comparison_operator" "")
3249
+   (match_operand:QI 2 "register_operand" "")
3250
+   (match_operand:QI 3 "register_operand" "")]
3251
+  ""
3252
+  "FAIL;")
3253
+
3254
+
3255
+;;
3256
+;; conditional moves
3257
+;;
3258
+
3259
+(define_expand "movsicc"
3260
+   [(set (match_operand:SI 0 "register_operand" "")
3261
+        (if_then_else:SI (match_operand 1 "comparison_operator" "")
3262
+                         (match_operand:SI 2 "register_operand" "")
3263
+                         (match_operand:SI 3 "register_operand" "")))]
3264
+  "TARGET_CMOV"
3265
+  "
3266
+{
3267
+  if (or32_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
3268
+    DONE;
3269
+}")
3270
+
3271
+(define_expand "movhicc"
3272
+   [(set (match_operand:HI 0 "register_operand" "")
3273
+        (if_then_else:SI (match_operand 1 "comparison_operator" "")
3274
+                         (match_operand:HI 2 "register_operand" "")
3275
+                         (match_operand:HI 3 "register_operand" "")))]
3276
+  ""
3277
+  "
3278
+{
3279
+    FAIL;
3280
+}")
3281
+
3282
+(define_expand "movqicc"
3283
+   [(set (match_operand:QI 0 "register_operand" "")
3284
+        (if_then_else:SI (match_operand 1 "comparison_operator" "")
3285
+                         (match_operand:QI 2 "register_operand" "")
3286
+                         (match_operand:QI 3 "register_operand" "")))]
3287
+  ""
3288
+  "
3289
+{
3290
+    FAIL;
3291
+}")
3292
+
3293
+
3294
+;; We use the BASE_REGS for the cmov input operands because, if rA is
3295
+;; 0, the value of 0 is placed in rD upon truth.  Similarly for rB
3296
+;; because we may switch the operands and rB may end up being rA.
3297
+
3298
+(define_insn "cmov"
3299
+  [(set (match_operand:SI 0 "register_operand" "=r")
3300
+       (if_then_else:SI
3301
+        (match_operator 1 "comparison_operator"
3302
+                        [(match_operand 4 "cc_reg_operand" "")
3303
+                         (const_int 0)])
3304
+        (match_operand:SI 2 "register_operand" "r")
3305
+        (match_operand:SI 3 "register_operand" "r")))]
3306
+  "TARGET_CMOV"
3307
+  "*
3308
+{ output_cmov(operands); }")
3309
+
3310
+;;
3311
+;;  ....................
3312
+;;
3313
+;;     COMPARISONS
3314
+;;
3315
+;;  ....................
3316
+
3317
+;; Flow here is rather complex:
3318
+;;
3319
+;;  1) The cmp{si,di,sf,df} routine is called.  It deposits the
3320
+;;     arguments into the branch_cmp array, and the type into
3321
+;;     branch_type.  No RTL is generated.
3322
+;;
3323
+;;  2) The appropriate branch define_expand is called, which then
3324
+;;     creates the appropriate RTL for the comparison and branch.
3325
+;;     Different CC modes are used, based on what type of branch is
3326
+;;     done, so that we can constrain things appropriately.  There
3327
+;;     are assumptions in the rest of GCC that break if we fold the
3328
+;;     operands into the branches for integer operations, and use cc0
3329
+;;     for floating point, so we use the fp status register instead.
3330
+;;     If needed, an appropriate temporary is created to hold the
3331
+;;     of the integer compare.
3332
+
3333
+;; Compare insns are next.  Note that the RS/6000 has two types of compares,
3334
+;; signed & unsigned, and one type of branch.
3335
+;;
3336
+;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3337
+;; insns, and branches.  We store the operands of compares until we see
3338
+;; how it is used.
3339
+
3340
+(define_expand "cmpsi"
3341
+  [(set (reg:CC 32)
3342
+       (compare:CC (match_operand:SI 0 "register_operand" "")
3343
+                   (match_operand:SI 1 "nonmemory_operand" "")))]
3344
+  ""
3345
+{
3346
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3347
+    operands[0] = force_reg (SImode, operands[0]);
3348
+  or32_compare_op0 = operands[0];
3349
+  or32_compare_op1 = operands[1];
3350
+  DONE;
3351
+})
3352
+
3353
+
3354
+
3355
+;;
3356
+;; Conditional branches
3357
+;;
3358
+
3359
+(define_expand "beq"
3360
+  [(use (match_operand 0 "" ""))]
3361
+  ""
3362
+  "or32_expand_branch (EQ, operands[0]); DONE;")
3363
+
3364
+(define_expand "bne"
3365
+  [(use (match_operand 0 "" ""))]
3366
+  ""
3367
+  "or32_expand_branch (NE, operands[0]); DONE;")
3368
+
3369
+(define_expand "bgt"
3370
+  [(use (match_operand 0 "" ""))]
3371
+  ""
3372
+  "or32_expand_branch (GT, operands[0]); DONE;")
3373
+
3374
+(define_expand "bgtu"
3375
+  [(use (match_operand 0 "" ""))]
3376
+  ""
3377
+  "or32_expand_branch (GTU, operands[0]); DONE;")
3378
+
3379
+(define_expand "blt"
3380
+  [(use (match_operand 0 "" ""))]
3381
+  ""
3382
+  "or32_expand_branch (LT, operands[0]); DONE;")
3383
+
3384
+(define_expand "bltu"
3385
+  [(use (match_operand 0 "" ""))]
3386
+  ""
3387
+  "or32_expand_branch (LTU, operands[0]); DONE;")
3388
+
3389
+(define_expand "bge"
3390
+  [(use (match_operand 0 "" ""))]
3391
+  ""
3392
+  "or32_expand_branch (GE, operands[0]); DONE;")
3393
+
3394
+(define_expand "bgeu"
3395
+  [(use (match_operand 0 "" ""))]
3396
+  ""
3397
+  "or32_expand_branch (GEU, operands[0]); DONE;")
3398
+
3399
+(define_expand "ble"
3400
+  [(use (match_operand 0 "" ""))]
3401
+  ""
3402
+  "or32_expand_branch (LE, operands[0]); DONE;")
3403
+
3404
+(define_expand "bleu"
3405
+  [(use (match_operand 0 "" ""))]
3406
+  ""
3407
+  "or32_expand_branch (LEU, operands[0]); DONE;")
3408
+
3409
+
3410
+
3411
+;;
3412
+;; Setting a CCxx registers from comparision
3413
+;;
3414
+
3415
+
3416
+
3417
+;; Here are the actual compare insns.
3418
+(define_insn "*cmpsi_eq"
3419
+  [(set (reg:CCEQ 32)
3420
+       (compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
3421
+                     (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3422
+  ""
3423
+  "@
3424
+   l.sfeqi\t%0,%1
3425
+   l.sfeq \t%0,%1")
3426
+
3427
+(define_insn "*cmpsi_ne"
3428
+  [(set (reg:CCNE 32)
3429
+       (compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
3430
+                     (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3431
+  ""
3432
+  "@
3433
+   l.sfnei\t%0,%1
3434
+   l.sfne \t%0,%1")
3435
+
3436
+(define_insn "*cmpsi_gt"
3437
+  [(set (reg:CCGT 32)
3438
+       (compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
3439
+                     (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3440
+  ""
3441
+  "@
3442
+   l.sfgtsi\t%0,%1
3443
+   l.sfgts \t%0,%1")
3444
+
3445
+(define_insn "*cmpsi_gtu"
3446
+  [(set (reg:CCGTU 32)
3447
+       (compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
3448
+                      (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3449
+  ""
3450
+  "@
3451
+   l.sfgtui\t%0,%1
3452
+   l.sfgtu \t%0,%1")
3453
+
3454
+(define_insn "*cmpsi_lt"
3455
+  [(set (reg:CCLT 32)
3456
+       (compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
3457
+                     (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3458
+  ""
3459
+  "@
3460
+   l.sfltsi\t%0,%1
3461
+   l.sflts \t%0,%1")
3462
+
3463
+(define_insn "*cmpsi_ltu"
3464
+  [(set (reg:CCLTU 32)
3465
+       (compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
3466
+                      (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3467
+  ""
3468
+  "@
3469
+   l.sfltui\t%0,%1
3470
+   l.sfltu \t%0,%1")
3471
+
3472
+(define_insn "*cmpsi_ge"
3473
+  [(set (reg:CCGE 32)
3474
+       (compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
3475
+                     (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3476
+  ""
3477
+  "@
3478
+   l.sfgesi\t%0,%1
3479
+   l.sfges \t%0,%1")
3480
+
3481
+
3482
+(define_insn "*cmpsi_geu"
3483
+  [(set (reg:CCGEU 32)
3484
+       (compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
3485
+                      (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3486
+  ""
3487
+  "@
3488
+   l.sfgeui\t%0,%1
3489
+   l.sfgeu \t%0,%1")
3490
+
3491
+
3492
+(define_insn "*cmpsi_le"
3493
+  [(set (reg:CCLE 32)
3494
+       (compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
3495
+                     (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3496
+  ""
3497
+  "@
3498
+   l.sflesi\t%0,%1
3499
+   l.sfles \t%0,%1")
3500
+
3501
+(define_insn "*cmpsi_leu"
3502
+  [(set (reg:CCLEU 32)
3503
+       (compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
3504
+                      (match_operand:SI 1 "nonmemory_operand" "I,r")))]
3505
+  ""
3506
+  "@
3507
+   l.sfleui\t%0,%1
3508
+   l.sfleu \t%0,%1")
3509
+
3510
+(define_insn "*bf"
3511
+  [(set (pc)
3512
+       (if_then_else (match_operator 1 "comparison_operator"
3513
+                                     [(match_operand 2
3514
+                                                     "cc_reg_operand" "")
3515
+                                      (const_int 0)])
3516
+                     (label_ref (match_operand 0 "" ""))
3517
+                     (pc)))]
3518
+  ""
3519
+  "*
3520
+{ output_bf(operands); }"
3521
+  [(set_attr "type" "branch")
3522
+   (set_attr "length" "1")])
3523
+
3524
+;;
3525
+;;
3526
+;;
3527
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3528
+;;
3529
+;;
3530
+
3531
+
3532
+(define_insn "movdi"
3533
+        [(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m, r")
3534
+              (match_operand:DI 1 "general_operand"      " r, m, r, i"))]
3535
+        ""
3536
+        "*
3537
+         return or32_output_move_double (operands);
3538
+       "
3539
+       [(set_attr "length" "2,2,2,3")])
3540
+
3541
+(define_insn "movdf"
3542
+        [(set (match_operand:DF 0 "nonimmediate_operand" "=r, r, m, r")
3543
+              (match_operand:DF 1 "general_operand"      " r, m, r, i"))]
3544
+        ""
3545
+        "*
3546
+         return or32_output_move_double (operands);
3547
+        "
3548
+       [(set_attr "length" "2,2,2,3")])
3549
+
3550
+
3551
+(define_insn "movsf"
3552
+  [(set (match_operand:SF 0 "general_operand" "=r,r,m")
3553
+        (match_operand:SF 1 "general_operand"  "r,m,r"))]
3554
+  ""
3555
+  "@
3556
+   l.ori   \t%0,%1,0\t # movsf
3557
+   l.lwz   \t%0,%1\t # movsf
3558
+   l.sw    \t%0,%1\t # movsf"
3559
+[(set_attr "type" "move,load,store")
3560
+   (set_attr "length" "1,1,1")])
3561
+
3562
+;;
3563
+;; extendqisi2
3564
+;;
3565
+
3566
+(define_expand "extendqisi2"
3567
+  [(use (match_operand:SI 0 "register_operand" ""))
3568
+   (use (match_operand:QI 1 "nonimmediate_operand" ""))]
3569
+  ""
3570
+  "
3571
+{
3572
+  if (TARGET_SEXT)
3573
+    emit_insn (gen_extendqisi2_sext(operands[0], operands[1]));
3574
+  else {
3575
+    if ( GET_CODE(operands[1]) == MEM ) {
3576
+      emit_insn (gen_extendqisi2_no_sext_mem(operands[0], operands[1]));
3577
+    }
3578
+    else {
3579
+      emit_insn (gen_extendqisi2_no_sext_reg(operands[0], operands[1]));
3580
+    }
3581
+ }
3582
+ DONE;
3583
+}")
3584
+
3585
+(define_insn "extendqisi2_sext"
3586
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3587
+       (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
3588
+  "TARGET_SEXT"
3589
+  "@
3590
+   l.extbs \t%0,%1\t # extendqisi2_has_signed_extend
3591
+   l.lbs   \t%0,%1\t # extendqisi2_has_signed_extend"
3592
+  [(set_attr "length" "1,1")
3593
+   (set_attr "type" "extend,load")])
3594
+
3595
+(define_insn "extendqisi2_no_sext_mem"
3596
+  [(set (match_operand:SI 0 "register_operand" "=r")
3597
+        (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3598
+  "!TARGET_SEXT"
3599
+  "l.lbs   \t%0,%1\t # extendqisi2_no_sext_mem"
3600
+  [(set_attr "length" "1")
3601
+   (set_attr "type" "load")])
3602
+
3603
+(define_expand "extendqisi2_no_sext_reg"
3604
+  [(set (match_dup 2)
3605
+       (ashift:SI (match_operand:QI 1 "register_operand" "")
3606
+                  (const_int 24)))
3607
+   (set (match_operand:SI 0 "register_operand" "")
3608
+       (ashiftrt:SI (match_dup 2)
3609
+                    (const_int 24)))]
3610
+  "!TARGET_SEXT"
3611
+  "
3612
+{
3613
+  operands[1] = gen_lowpart (SImode, operands[1]);
3614
+  operands[2] = gen_reg_rtx (SImode); }")
3615
+
3616
+;;
3617
+;; extendhisi2
3618
+;;
3619
+
3620
+(define_expand "extendhisi2"
3621
+  [(use (match_operand:SI 0 "register_operand" ""))
3622
+   (use (match_operand:HI 1 "nonimmediate_operand" ""))]
3623
+  ""
3624
+  "
3625
+{
3626
+  if (TARGET_SEXT)
3627
+    emit_insn (gen_extendhisi2_sext(operands[0], operands[1]));
3628
+  else {
3629
+    if ( GET_CODE(operands[1]) == MEM ) {
3630
+      emit_insn (gen_extendhisi2_no_sext_mem(operands[0], operands[1]));
3631
+    }
3632
+    else {
3633
+      emit_insn (gen_extendhisi2_no_sext_reg(operands[0], operands[1]));
3634
+    }
3635
+ }
3636
+ DONE;
3637
+}")
3638
+
3639
+(define_insn "extendhisi2_sext"
3640
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3641
+       (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3642
+  "TARGET_SEXT"
3643
+  "@
3644
+   l.exths \t%0,%1\t # extendhisi2_has_signed_extend
3645
+   l.lhs   \t%0,%1\t # extendhisi2_has_signed_extend"
3646
+  [(set_attr "length" "1,1")
3647
+   (set_attr "type" "extend,load")])
3648
+
3649
+(define_insn "extendhisi2_no_sext_mem"
3650
+  [(set (match_operand:SI 0 "register_operand" "=r")
3651
+        (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3652
+  "!TARGET_SEXT"
3653
+  "l.lhs   \t%0,%1\t # extendhisi2_no_sext_mem"
3654
+  [(set_attr "length" "1")
3655
+   (set_attr "type" "load")])
3656
+
3657
+(define_expand "extendhisi2_no_sext_reg"
3658
+  [(set (match_dup 2)
3659
+       (ashift:SI (match_operand:HI 1 "register_operand" "")
3660
+                  (const_int 16)))
3661
+   (set (match_operand:SI 0 "register_operand" "")
3662
+       (ashiftrt:SI (match_dup 2)
3663
+                    (const_int 16)))]
3664
+  "!TARGET_SEXT"
3665
+  "
3666
+{
3667
+  operands[1] = gen_lowpart (SImode, operands[1]);
3668
+  operands[2] = gen_reg_rtx (SImode); }")
3669
+
3670
+
3671
+;;
3672
+;; zero_extend<m><n>2
3673
+;;
3674
+
3675
+(define_insn "zero_extendqisi2"
3676
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3677
+       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
3678
+  ""
3679
+  "@
3680
+   l.andi  \t%0,%1,0xff\t # zero_extendqisi2
3681
+   l.lbz   \t%0,%1\t # zero_extendqisi2"
3682
+  [(set_attr "type" "logic,load")
3683
+   (set_attr "length" "1,1")])
3684
+
3685
+
3686
+(define_insn "zero_extendhisi2"
3687
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3688
+       (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3689
+  ""
3690
+  "@
3691
+   l.andi  \t%0,%1,0xffff\t # zero_extendqisi2
3692
+   l.lhz   \t%0,%1\t # zero_extendqisi2"
3693
+  [(set_attr "type" "logic,load")
3694
+   (set_attr "length" "1,1")])
3695
+
3696
+;;
3697
+;; Shift/rotate operations
3698
+;;
3699
+
3700
+(define_insn "ashlsi3"
3701
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3702
+        (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
3703
+                   (match_operand:SI 2 "nonmemory_operand" "r,L")))]
3704
+  ""
3705
+  "@
3706
+   l.sll   \t%0,%1,%2
3707
+   l.slli  \t%0,%1,%2"
3708
+  [(set_attr "type" "shift,shift")
3709
+   (set_attr "length" "1,1")])
3710
+
3711
+(define_insn "ashrsi3"
3712
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3713
+        (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
3714
+                   (match_operand:SI 2 "nonmemory_operand" "r,L")))]
3715
+  ""
3716
+  "@
3717
+   l.sra   \t%0,%1,%2
3718
+   l.srai  \t%0,%1,%2"
3719
+  [(set_attr "type" "shift,shift")
3720
+   (set_attr "length" "1,1")])
3721
+
3722
+(define_insn "lshrsi3"
3723
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3724
+        (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
3725
+                   (match_operand:SI 2 "nonmemory_operand" "r,L")))]
3726
+  ""
3727
+  "@
3728
+   l.srl   \t%0,%1,%2
3729
+   l.srli  \t%0,%1,%2"
3730
+  [(set_attr "type" "shift,shift")
3731
+   (set_attr "length" "1,1")])
3732
+
3733
+(define_insn "rotrsi3"
3734
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3735
+        (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
3736
+                   (match_operand:SI 2 "nonmemory_operand" "r,L")))]
3737
+  "TARGET_ROR"
3738
+  "@
3739
+   l.ror   \t%0,%1,%2
3740
+   l.rori  \t%0,%1,%2"
3741
+  [(set_attr "type" "shift,shift")
3742
+   (set_attr "length" "1,1")])
3743
+
3744
+;;
3745
+;; Logical bitwise operations
3746
+;;
3747
+
3748
+(define_insn "andsi3"
3749
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3750
+       (and:SI (match_operand:SI 1 "register_operand" "%r,r")
3751
+               (match_operand:SI 2 "nonmemory_operand" "r,K")))]
3752
+  ""
3753
+  "@
3754
+   l.and   \t%0,%1,%2
3755
+   l.andi  \t%0,%1,%2"
3756
+  [(set_attr "type" "logic,logic")
3757
+   (set_attr "length" "1,1")])
3758
+
3759
+(define_insn "iorsi3"
3760
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3761
+       (ior:SI (match_operand:SI 1 "register_operand" "%r,r")
3762
+               (match_operand:SI 2 "nonmemory_operand" "r,K")))]
3763
+  ""
3764
+  "@
3765
+   l.or    \t%0,%1,%2
3766
+   l.ori   \t%0,%1,%2"
3767
+  [(set_attr "type" "logic,logic")
3768
+   (set_attr "length" "1,1")])
3769
+
3770
+(define_insn "xorsi3"
3771
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3772
+       (xor:SI (match_operand:SI 1 "register_operand" "%r,r")
3773
+               (match_operand:SI 2 "nonmemory_operand" "r,I")))]
3774
+  ""
3775
+  "@
3776
+   l.xor   \t%0,%1,%2
3777
+   l.xori  \t%0,%1,%2"
3778
+  [(set_attr "type" "logic,logic")
3779
+   (set_attr "length" "1,1")])
3780
+
3781
+(define_insn "one_cmplqi2"
3782
+  [(set (match_operand:QI 0 "register_operand" "=r")
3783
+       (not:QI (match_operand:QI 1 "register_operand" "r")))]
3784
+  ""
3785
+  "l.xori  \t%0,%1,0x00ff"
3786
+  [(set_attr "type" "logic")
3787
+   (set_attr "length" "1")])
3788
+
3789
+(define_insn "one_cmplsi2"
3790
+  [(set (match_operand:SI 0 "register_operand" "=r")
3791
+       (not:SI (match_operand:SI 1 "register_operand" "r")))]
3792
+  ""
3793
+  "l.xori  \t%0,%1,0xffff"
3794
+  [(set_attr "type" "logic")
3795
+   (set_attr "length" "1")])
3796
+
3797
+;;
3798
+;; Arithmetic operations
3799
+;;
3800
+
3801
+(define_insn "negsi2"
3802
+  [(set (match_operand:SI 0 "register_operand" "=r")
3803
+       (neg:SI (match_operand:SI 1 "register_operand" "r")))]
3804
+  ""
3805
+  "l.sub   \t%0,r0,%1"
3806
+  [(set_attr "type" "add")
3807
+   (set_attr "length" "1")])
3808
+
3809
+(define_insn "addsi3"
3810
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3811
+       (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3812
+                (match_operand:SI 2 "nonmemory_operand" "r,I")))]
3813
+  ""
3814
+  "@
3815
+   l.add   \t%0,%1,%2
3816
+   l.addi  \t%0,%1,%2"
3817
+  [(set_attr "type" "add,add")
3818
+   (set_attr "length" "1,1")])
3819
+
3820
+(define_insn "subsi3"
3821
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
3822
+       (minus:SI (match_operand:SI 1 "register_operand" "r,r")
3823
+                 (match_operand:SI 2 "nonmemory_operand" "r,I")))]
3824
+  ""
3825
+  "@
3826
+   l.sub   \t%0,%1,%2
3827
+   l.addi  \t%0,%1,%n2"
3828
+  [(set_attr "type" "add,add")]
3829
+)
3830
+
3831
+;;
3832
+;; mul and div
3833
+;;
3834
+
3835
+(define_insn "mulsi3"
3836
+  [(set (match_operand:SI 0 "register_operand" "=r")
3837
+        (mult:SI (match_operand:SI 1 "register_operand" "r")
3838
+                 (match_operand:SI 2 "register_operand" "r")))]
3839
+  "TARGET_HARD_MUL"
3840
+  "l.mul   \t%0,%1,%2"
3841
+  [(set_attr "type" "mul")
3842
+   (set_attr "length" "1")])
3843
+
3844
+(define_insn "divsi3"
3845
+  [(set (match_operand:SI 0 "register_operand" "=r")
3846
+        (div:SI (match_operand:SI 1 "register_operand" "r")
3847
+                 (match_operand:SI 2 "register_operand" "r")))]
3848
+  "TARGET_HARD_DIV"
3849
+  "l.div   \t%0,%1,%2"
3850
+  [(set_attr "type" "mul")
3851
+   (set_attr "length" "1")])
3852
+
3853
+(define_insn "udivsi3"
3854
+  [(set (match_operand:SI 0 "register_operand" "=r")
3855
+        (udiv:SI (match_operand:SI 1 "register_operand" "r")
3856
+                 (match_operand:SI 2 "register_operand" "r")))]
3857
+  "TARGET_HARD_DIV"
3858
+  "l.divu  \t%0,%1,%2"
3859
+  [(set_attr "type" "mul")
3860
+   (set_attr "length" "1")])
3861
+
3862
+;;
3863
+;; jumps
3864
+;;
3865
+
3866
+;; jump
3867
+
3868
+(define_expand "jump"
3869
+  [(set (pc)
3870
+       (label_ref (match_operand 0 "" "")))]
3871
+  ""
3872
+  "
3873
+{
3874
+  if (!TARGET_ALIGNED_JUMPS)
3875
+    emit_jump_insn (gen_jump_internal (operands[0]));
3876
+  else
3877
+    emit_jump_insn (gen_jump_aligned (operands[0]));
3878
+  DONE;
3879
+}")
3880
+
3881
+(define_insn "jump_internal"
3882
+  [(set (pc)
3883
+       (label_ref (match_operand 0 "" "")))]
3884
+  "!TARGET_ALIGNED_JUMPS"
3885
+  "l.j     \t%l0%("
3886
+  [(set_attr "type" "jump")
3887
+   (set_attr "length" "1")])
3888
+
3889
+(define_insn "jump_aligned"
3890
+  [(set (pc)
3891
+       (label_ref (match_operand 0 "" "")))]
3892
+  "TARGET_ALIGNED_JUMPS"
3893
+  ".balignl 0x8,0x15000015,0x4\;l.j     \t%l0%("
3894
+  [(set_attr "type" "jump")
3895
+   (set_attr "length" "1")])
3896
+
3897
+;; indirect jump
3898
+
3899
+(define_expand "indirect_jump"
3900
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3901
+  ""
3902
+  "
3903
+{
3904
+  if (!TARGET_ALIGNED_JUMPS)
3905
+    emit_jump_insn (gen_indirect_jump_internal (operands[0]));
3906
+  else
3907
+    emit_jump_insn (gen_indirect_jump_aligned (operands[0]));
3908
+  DONE;
3909
+
3910
+}")
3911
+
3912
+(define_insn "indirect_jump_internal"
3913
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3914
+  "!TARGET_ALIGNED_JUMPS"
3915
+  "l.jr    \t%0%("
3916
+  [(set_attr "type" "jump")
3917
+   (set_attr "length" "1")])
3918
+
3919
+(define_insn "indirect_jump_aligned"
3920
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3921
+  "TARGET_ALIGNED_JUMPS"
3922
+  ".balignl 0x8,0x15000015,0x4\;l.jr    \t%0%("
3923
+  [(set_attr "type" "jump")
3924
+   (set_attr "length" "1")])
3925
+
3926
+;;
3927
+;; calls
3928
+;;
3929
+
3930
+;; call
3931
+
3932
+(define_expand "call"
3933
+  [(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
3934
+                   (match_operand 1 "" "i"))
3935
+             (clobber (reg:SI 9))])]
3936
+  ""
3937
+  "
3938
+{
3939
+  if (!TARGET_ALIGNED_JUMPS)
3940
+    emit_call_insn (gen_call_internal (operands[0], operands[1]));
3941
+  else
3942
+    emit_call_insn (gen_call_aligned (operands[0], operands[1]));
3943
+  DONE;
3944
+}")
3945
+
3946
+(define_insn "call_internal"
3947
+[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
3948
+                  (match_operand 1 "" "i"))
3949
+            (clobber (reg:SI 9))])]
3950
+  "!TARGET_ALIGNED_JUMPS"
3951
+  "l.jal   \t%S0%("
3952
+  [(set_attr "type" "jump")
3953
+   (set_attr "length" "1")])
3954
+
3955
+(define_insn "call_aligned"
3956
+[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
3957
+                  (match_operand 1 "" "i"))
3958
+            (clobber (reg:SI 9))])]
3959
+  "TARGET_ALIGNED_JUMPS"
3960
+  ".balignl 0x8,0x15000015,0x4\;l.jal   \t%S0%("
3961
+  [(set_attr "type" "jump")
3962
+   (set_attr "length" "1")])
3963
+
3964
+;; call value
3965
+
3966
+(define_expand "call_value"
3967
+  [(parallel [(set (match_operand 0 "register_operand" "=r")
3968
+                  (call (match_operand:SI 1 "sym_ref_mem_operand" "")
3969
+                        (match_operand 2 "" "i")))
3970
+             (clobber (reg:SI 9))])]
3971
+  ""
3972
+  "
3973
+{
3974
+  if (!TARGET_ALIGNED_JUMPS)
3975
+    emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
3976
+  else
3977
+    emit_call_insn (gen_call_value_aligned (operands[0], operands[1], operands[2]));
3978
+  DONE;
3979
+}")
3980
+
3981
+(define_insn "call_value_internal"
3982
+[(parallel [(set (match_operand 0 "register_operand" "=r")
3983
+                  (call (match_operand:SI 1 "sym_ref_mem_operand" "")
3984
+                        (match_operand 2 "" "i")))
3985
+            (clobber (reg:SI 9))])]
3986
+  "!TARGET_ALIGNED_JUMPS"
3987
+  "l.jal   \t%S1%("
3988
+  [(set_attr "type" "jump")
3989
+   (set_attr "length" "1")])
3990
+
3991
+(define_insn "call_value_aligned"
3992
+[(parallel [(set (match_operand 0 "register_operand" "=r")
3993
+                  (call (match_operand:SI 1 "sym_ref_mem_operand" "")
3994
+                        (match_operand 2 "" "i")))
3995
+            (clobber (reg:SI 9))])]
3996
+  "TARGET_ALIGNED_JUMPS"
3997
+  ".balignl 0x8,0x15000015,0x4\;l.jal   \t%S1%("
3998
+  [(set_attr "type" "jump")
3999
+   (set_attr "length" "1")])
4000
+
4001
+;; indirect call value
4002
+
4003
+(define_expand "call_value_indirect"
4004
+  [(parallel [(set (match_operand 0 "register_operand" "=r")
4005
+                   (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
4006
+                         (match_operand 2 "" "i")))
4007
+              (clobber (reg:SI 9))])]
4008
+  ""
4009
+  "
4010
+{
4011
+  if (!TARGET_ALIGNED_JUMPS)
4012
+    emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
4013
+  else
4014
+    emit_call_insn (gen_call_value_indirect_aligned (operands[0], operands[1], operands[2]));
4015
+  DONE;
4016
+}")
4017
+
4018
+(define_insn "call_value_indirect_internal"
4019
+  [(parallel [(set (match_operand 0 "register_operand" "=r")
4020
+                   (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
4021
+                         (match_operand 2 "" "i")))
4022
+              (clobber (reg:SI 9))])]
4023
+  "!TARGET_ALIGNED_JUMPS"
4024
+  "l.jalr  \t%1%("
4025
+  [(set_attr "type" "jump")
4026
+   (set_attr "length" "1")])
4027
+
4028
+(define_insn "call_value_indirect_aligned"
4029
+  [(parallel [(set (match_operand 0 "register_operand" "=r")
4030
+                   (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
4031
+                         (match_operand 2 "" "i")))
4032
+              (clobber (reg:SI 9))])]
4033
+  "TARGET_ALIGNED_JUMPS"
4034
+  ".balignl 0x8,0x15000015,0x4\;l.jalr  \t%1%("
4035
+  [(set_attr "type" "jump")
4036
+   (set_attr "length" "1")])
4037
+
4038
+;; indirect call
4039
+
4040
+(define_expand "call_indirect"
4041
+  [(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
4042
+                   (match_operand 1 "" "i"))
4043
+              (clobber (reg:SI 9))])]
4044
+  ""
4045
+  "
4046
+{
4047
+  if (!TARGET_ALIGNED_JUMPS)
4048
+    emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
4049
+  else
4050
+    emit_call_insn (gen_call_indirect_aligned (operands[0], operands[1]));
4051
+  DONE;
4052
+}")
4053
+
4054
+(define_insn "call_indirect_internal"
4055
+[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
4056
+                  (match_operand 1 "" "i"))
4057
+              (clobber (reg:SI 9))])]
4058
+  "!TARGET_ALIGNED_JUMPS"
4059
+  "l.jalr  \t%0%("
4060
+  [(set_attr "type" "jump")
4061
+   (set_attr "length" "1")])
4062
+
4063
+(define_insn "call_indirect_aligned"
4064
+[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
4065
+                  (match_operand 1 "" "i"))
4066
+              (clobber (reg:SI 9))])]
4067
+  "TARGET_ALIGNED_JUMPS"
4068
+  ".balignl 0x8,0x15000015,0x4\;l.jalr  \t%0%("
4069
+  [(set_attr "type" "jump")
4070
+   (set_attr "length" "1")])
4071
+
4072
+;; table jump
4073
+
4074
+(define_expand "tablejump"
4075
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
4076
+   (use (label_ref (match_operand 1 "" "")))]
4077
+   ""
4078
+  "
4079
+{
4080
+  if (!TARGET_ALIGNED_JUMPS)
4081
+    emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
4082
+  else
4083
+    emit_jump_insn (gen_tablejump_aligned (operands[0], operands[1]));
4084
+  DONE;
4085
+}")
4086
+
4087
+(define_insn "tablejump_internal"
4088
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
4089
+   (use (label_ref (match_operand 1 "" "")))]
4090
+  "!TARGET_ALIGNED_JUMPS"
4091
+  "l.jr    \t%0%("
4092
+  [(set_attr "type" "jump")
4093
+   (set_attr "length" "1")])
4094
+
4095
+(define_insn "tablejump_aligned"
4096
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
4097
+   (use (label_ref (match_operand 1 "" "")))]
4098
+  "TARGET_ALIGNED_JUMPS"
4099
+  ".balignl 0x8,0x15000015,0x4\;l.jr    \t%0%("
4100
+  [(set_attr "type" "jump")
4101
+   (set_attr "length" "1")])
4102
+
4103
+
4104
+;; no-op
4105
+
4106
+(define_insn "nop"
4107
+  [(const_int 0)]
4108
+  ""
4109
+  "l.nop"
4110
+  [(set_attr "type" "logic")
4111
+   (set_attr "length" "1")])
4112
+
4113
+;;
4114
+;; floating point
4115
+;;
4116
+
4117
+(define_insn "addsf3"
4118
+  [(set (match_operand:SF 0 "register_operand" "=r")
4119
+        (plus:SF (match_operand:SF 1 "register_operand" "r")
4120
+                 (match_operand:SF 2 "register_operand" "r")))]
4121
+  "TARGET_HARD_FLOAT"
4122
+  "lf.add.s\t%0,%1,%2"
4123
+  [(set_attr "type"     "fp")
4124
+   (set_attr "length"   "1")])
4125
+
4126
+(define_insn "adddf3"
4127
+  [(set (match_operand:DF 0 "register_operand" "=r")
4128
+        (plus:DF (match_operand:DF 1 "register_operand" "r")
4129
+                 (match_operand:DF 2 "register_operand" "r")))]
4130
+  "TARGET_HARD_FLOAT"
4131
+  "lf.add.d\t%0,%1,%2"
4132
+  [(set_attr "type"     "fp")
4133
+   (set_attr "length"   "1")])
4134
+
4135
+(define_insn "subsf3"
4136
+  [(set (match_operand:SF 0 "register_operand" "=r")
4137
+        (minus:SF (match_operand:SF 1 "register_operand" "r")
4138
+                 (match_operand:SF 2 "register_operand" "r")))]
4139
+  "TARGET_HARD_FLOAT"
4140
+  "lf.sub.s\t%0,%1,%2"
4141
+  [(set_attr "type"     "fp")
4142
+   (set_attr "length"   "1")])
4143
+
4144
+(define_insn "subdf3"
4145
+  [(set (match_operand:DF 0 "register_operand" "=r")
4146
+        (minus:DF (match_operand:DF 1 "register_operand" "r")
4147
+                 (match_operand:DF 2 "register_operand" "r")))]
4148
+  "TARGET_HARD_FLOAT"
4149
+  "lf.sub.d\t%0,%1,%2"
4150
+  [(set_attr "type"     "fp")
4151
+   (set_attr "length"   "1")])
4152
+
4153
+(define_insn "mulsf3"
4154
+  [(set (match_operand:SF 0 "register_operand" "=r")
4155
+        (mult:SF (match_operand:SF 1 "register_operand" "r")
4156
+                 (match_operand:SF 2 "register_operand" "r")))]
4157
+  "TARGET_HARD_FLOAT"
4158
+  "lf.mul.s\t%0,%1,%2"
4159
+  [(set_attr "type"     "fp")
4160
+   (set_attr "length"   "1")])
4161
+
4162
+(define_insn "muldf3"
4163
+  [(set (match_operand:DF 0 "register_operand" "=r")
4164
+        (mult:DF (match_operand:DF 1 "register_operand" "r")
4165
+                 (match_operand:DF 2 "register_operand" "r")))]
4166
+  "TARGET_HARD_FLOAT"
4167
+  "lf.mul.d\t%0,%1,%2"
4168
+  [(set_attr "type"     "fp")
4169
+   (set_attr "length"   "1")])
4170
+
4171
+(define_insn "divsf3"
4172
+  [(set (match_operand:SF 0 "register_operand" "=r")
4173
+        (div:SF (match_operand:SF 1 "register_operand" "r")
4174
+                 (match_operand:SF 2 "register_operand" "r")))]
4175
+  "TARGET_HARD_FLOAT"
4176
+  "lf.div.s\t%0,%1,%2"
4177
+  [(set_attr "type"     "fp")
4178
+   (set_attr "length"   "1")])
4179
+
4180
+(define_insn "divdf3"
4181
+  [(set (match_operand:DF 0 "register_operand" "=r")
4182
+        (div:DF (match_operand:DF 1 "register_operand" "r")
4183
+                 (match_operand:DF 2 "register_operand" "r")))]
4184
+  "TARGET_HARD_FLOAT"
4185
+  "lf.div.d\t%0,%1,%2"
4186
+  [(set_attr "type"     "fp")
4187
+   (set_attr "length"   "1")])
4188
+
4189
+
4190
+;; Local variables:
4191
+;; mode:emacs-lisp
4192
+;; comment-start: ";; "
4193
+;; eval: (set-syntax-table (copy-sequence (syntax-table)))
4194
+;; eval: (modify-syntax-entry ?[ "(]")
4195
+;; eval: (modify-syntax-entry ?] ")[")
4196
+;; eval: (modify-syntax-entry ?{ "(}")
4197
+;; eval: (modify-syntax-entry ?} "){")
4198
+;; eval: (setq indent-tabs-mode t)
4199
+;; End:
4200
diff -Nru gcc-3.4.4.orig/gcc/config/or32/or32-modes.def gcc-3.4.4-DONE/gcc/config/or32/or32-modes.def
4201
--- gcc-3.4.4.orig/gcc/config/or32/or32-modes.def       1970-01-01 02:00:00.000000000 +0200
4202
+++ gcc-3.4.4-DONE/gcc/config/or32/or32-modes.def       2005-11-29 16:23:09.000000000 +0200
4203
@@ -0,0 +1,39 @@
4204
+/* Definitions of target machine for GNU compiler, for IBM RS/6000.
4205
+   Copyright (C) 2002, 2003 Free Software Foundation, Inc.
4206
+   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4207
+
4208
+   This file is part of GCC.
4209
+
4210
+   GCC is free software; you can redistribute it and/or modify it
4211
+   under the terms of the GNU General Public License as published
4212
+   by the Free Software Foundation; either version 2, or (at your
4213
+   option) any later version.
4214
+
4215
+   GCC is distributed in the hope that it will be useful, but WITHOUT
4216
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
4217
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
4218
+   License for more details.
4219
+
4220
+   You should have received a copy of the GNU General Public License
4221
+   along with GCC; see the file COPYING.  If not, write to the
4222
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston,
4223
+   MA 02111-1307, USA.  */
4224
+
4225
+/* Add any extra modes needed to represent the condition code.
4226
+ */
4227
+
4228
+CC_MODE (CCEQ);
4229
+CC_MODE (CCNE);
4230
+
4231
+CC_MODE (CCLE);
4232
+CC_MODE (CCGE);
4233
+CC_MODE (CCLT);
4234
+CC_MODE (CCGT);
4235
+
4236
+CC_MODE (CCLEU);
4237
+CC_MODE (CCGEU);
4238
+CC_MODE (CCLTU);
4239
+CC_MODE (CCGTU);
4240
+
4241
+CC_MODE(CCFP);
4242
+CC_MODE(CCUNS);
4243
diff -Nru gcc-3.4.4.orig/gcc/config/or32/or32-protos.h gcc-3.4.4-DONE/gcc/config/or32/or32-protos.h
4244
--- gcc-3.4.4.orig/gcc/config/or32/or32-protos.h        1970-01-01 02:00:00.000000000 +0200
4245
+++ gcc-3.4.4-DONE/gcc/config/or32/or32-protos.h        2005-11-29 16:23:09.000000000 +0200
4246
@@ -0,0 +1,37 @@
4247
+/* Definitions of target machine for GNU compiler, Argonaut ARC cpu.
4248
+   Copyright (C) 2000 Free Software Foundation, Inc.
4249
+
4250
+This file is part of GNU CC.
4251
+
4252
+GNU CC is free software; you can redistribute it and/or modify
4253
+it under the terms of the GNU General Public License as published by
4254
+the Free Software Foundation; either version 2, or (at your option)
4255
+any later version.
4256
+
4257
+GNU CC is distributed in the hope that it will be useful,
4258
+but WITHOUT ANY WARRANTY; without even the implied warranty of
4259
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4260
+GNU General Public License for more details.
4261
+
4262
+You should have received a copy of the GNU General Public License
4263
+along with GNU CC; see the file COPYING.  If not, write to
4264
+the Free Software Foundation, 59 Temple Place - Suite 330,
4265
+Boston, MA 02111-1307, USA.  */
4266
+
4267
+#ifdef RTX_CODE
4268
+#ifdef TREE_CODE
4269
+#endif /* TREE_CODE */
4270
+
4271
+extern void print_operand PARAMS ((FILE *, rtx, int));
4272
+extern void print_operand_address PARAMS ((FILE *, register rtx));
4273
+extern const char *or1k_output_move_double PARAMS ((rtx *operands));
4274
+
4275
+extern rtx or1k_cmp_op[];
4276
+
4277
+#endif /* RTX_CODE */
4278
+
4279
+#ifdef TREE_CODE
4280
+
4281
+#endif /* TREE_CODE */
4282
+
4283
+extern int print_operand_punct_valid_p PARAMS ((int));
4284
diff -Nru gcc-3.4.4.orig/gcc/config/or32/or32.S gcc-3.4.4-DONE/gcc/config/or32/or32.S
4285
--- gcc-3.4.4.orig/gcc/config/or32/or32.S       1970-01-01 02:00:00.000000000 +0200
4286
+++ gcc-3.4.4-DONE/gcc/config/or32/or32.S       2005-11-29 16:23:09.000000000 +0200
4287
@@ -0,0 +1,182 @@
4288
+/*
4289
+ * Assembly functions for software multiplication and devision.
4290
+ */
4291
+
4292
+#define ENTRY(symbol)  \
4293
+       .align 4        ;\
4294
+       .global symbol  ;\
4295
+symbol:
4296
+
4297
+#ifdef L__mulsi3
4298
+ENTRY(___mulsi3)
4299
+       l.addi r11,r0,0x0
4300
+       l.sfne r3,r11
4301
+       l.bnf 3f
4302
+       l.ori r5,r3,0x0
4303
+       l.addi r6,r0,0x0
4304
+1:
4305
+       l.andi r3,r5,0x1
4306
+       l.sfeq r3,r6
4307
+       l.bf 2f
4308
+       l.srli r5,r5,0x1
4309
+       l.add r11,r11,r4
4310
+2:
4311
+       l.sfne r5,r6
4312
+       l.bf 1b
4313
+       l.slli r4,r4,0x1
4314
+3:
4315
+       l.jr r9
4316
+       l.nop 0x0
4317
+#endif
4318
+
4319
+#ifdef L__udivsi3
4320
+ENTRY(___udivsi3)
4321
+       l.addi          r1,r1,-4
4322
+        l.sw            0(r1),r9
4323
+        l.addi          r11,r0,0
4324
+        l.addi          r8,r4,0
4325
+        l.addi          r5,r3,0
4326
+        l.sfne          r8,r11
4327
+        l.bnf           4f
4328
+        l.addi          r7,r0,0
4329
+        l.sfgtu         r8,r5
4330
+        l.bf            5f
4331
+        l.sfeq          r8,r5
4332
+        l.bf            6f
4333
+        l.sfltu         r11,r8
4334
+        l.bnf           2f
4335
+        l.addi          r13,r0,32
4336
+        l.movhi         r9,hi(0x80000000)
4337
+        l.addi          r6,r0,-1
4338
+1:
4339
+        l.and           r3,r5,r9
4340
+        l.slli          r4,r7,1
4341
+        l.addi          r15,r5,0
4342
+        l.srli          r3,r3,31
4343
+        l.add           r13,r13,r6
4344
+        l.or            r7,r4,r3
4345
+        l.sfltu         r7,r8
4346
+        l.bf            1b
4347
+        l.slli          r5,r5,1
4348
+2:
4349
+        l.srli          r7,r7,1
4350
+        l.addi          r13,r13,1
4351
+        l.addi          r9,r0,0
4352
+        l.sfltu         r9,r13
4353
+        l.bnf           4f
4354
+        l.addi          r5,r15,0
4355
+        l.movhi         r15,hi(0x80000000)
4356
+        l.addi          r17,r0,0
4357
+3:
4358
+        l.and           r3,r5,r15
4359
+        l.slli          r4,r7,1
4360
+        l.srli          r3,r3,31
4361
+        l.or            r7,r4,r3
4362
+        l.sub           r6,r7,r8
4363
+        l.and           r3,r6,r15
4364
+        l.srli          r3,r3,31
4365
+        l.addi          r4,r0,0
4366
+        l.sfne          r3,r4
4367
+        l.bf            1f
4368
+        l.slli          r3,r11,1
4369
+        l.addi          r4,r0,1
4370
+1:
4371
+        l.slli          r5,r5,1
4372
+        l.sfne          r4,r17
4373
+        l.bnf           2f
4374
+        l.or            r11,r3,r4
4375
+        l.addi          r7,r6,0
4376
+2:
4377
+        l.addi          r9,r9,1
4378
+        l.sfltu         r9,r13
4379
+        l.bf            3b
4380
+        l.nop           0
4381
+       l.j             4f
4382
+       l.nop           0
4383
+6:
4384
+       l.j             4f
4385
+       l.addi          r11,r0,1
4386
+5:
4387
+       l.addi          r7,r5,0
4388
+4:
4389
+        l.lwz           r9,0(r1)
4390
+        l.jr            r9
4391
+        l.addi          r1,r1,4
4392
+#endif
4393
+
4394
+
4395
+#ifdef L__divsi3
4396
+ENTRY(___divsi3)
4397
+       l.addi          r1,r1,-8
4398
+        l.sw            0(r1),r9
4399
+        l.sw            4(r1),r10
4400
+        l.addi          r5,r3,0
4401
+        l.addi          r10,r0,0
4402
+        l.sflts         r5,r0
4403
+        l.bnf           1f
4404
+        l.addi          r3,r0,0
4405
+        l.addi          r10,r0,1
4406
+        l.sub           r5,r0,r5
4407
+1:
4408
+        l.sflts         r4,r0
4409
+        l.bnf           1f
4410
+        l.nop           0
4411
+        l.addi          r10,r10,1
4412
+        l.sub           r4,r0,r4
4413
+1:
4414
+        l.jal           ___udivsi3
4415
+        l.addi          r3,r5,0
4416
+        l.sfeqi         r10,1
4417
+        l.bnf           1f
4418
+        l.nop           0
4419
+        l.sub           r11,r0,r11
4420
+1:
4421
+        l.lwz           r9,0(r1)
4422
+        l.lwz           r10,4(r1)
4423
+        l.jr            r9
4424
+        l.addi          r1,r1,8
4425
+#endif
4426
+
4427
+
4428
+#ifdef L__umodsi3
4429
+ENTRY(___umodsi3)
4430
+       l.addi          r1,r1,-4
4431
+       l.sw            0(r1),r9
4432
+       l.jal           ___udivsi3
4433
+       l.nop           0
4434
+       l.addi          r11,r7,0
4435
+       l.lwz           r9,0(r1)
4436
+       l.jr            r9
4437
+       l.addi          r1,r1,4
4438
+#endif
4439
+
4440
+
4441
+#ifdef L__modsi3
4442
+ENTRY(___modsi3)
4443
+        l.addi          r1,r1,-8
4444
+        l.sw            0(r1),r9
4445
+        l.sw            4(r1),r10
4446
+        l.addi          r10,r0,0
4447
+        l.sflts         r3,r0
4448
+        l.bnf           1f
4449
+        l.nop           0
4450
+        l.addi          r10,r0,1
4451
+        l.sub           r3,r0,r3
4452
+1:
4453
+        l.sflts         r4,r0
4454
+        l.bnf           1f
4455
+        l.nop           0
4456
+        l.sub           r4,r0,r4
4457
+1:
4458
+        l.jal           ___udivsi3
4459
+        l.nop           0
4460
+        l.sfeqi         r10,1
4461
+        l.bnf           1f
4462
+        l.addi         r11,r7,0
4463
+        l.sub           r11,r0,r11
4464
+1:
4465
+        l.lwz           r9,0(r1)
4466
+        l.lwz           r10,4(r1)
4467
+        l.jr            r9
4468
+        l.addi          r1,r1,8
4469
+#endif
4470
diff -Nru gcc-3.4.4.orig/gcc/config/or32/rtems.h gcc-3.4.4-DONE/gcc/config/or32/rtems.h
4471
--- gcc-3.4.4.orig/gcc/config/or32/rtems.h      1970-01-01 02:00:00.000000000 +0200
4472
+++ gcc-3.4.4-DONE/gcc/config/or32/rtems.h      2005-11-29 16:23:09.000000000 +0200
4473
@@ -0,0 +1,37 @@
4474
+/* Definitions for rtems targeting an OpenRisc OR32 using COFF
4475
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
4476
+   Contributed by Joel Sherrill (joel@OARcorp.com).
4477
+
4478
+This file is part of GNU CC.
4479
+
4480
+GNU CC is free software; you can redistribute it and/or modify
4481
+it under the terms of the GNU General Public License as published by
4482
+the Free Software Foundation; either version 2, or (at your option)
4483
+any later version.
4484
+
4485
+GNU CC is distributed in the hope that it will be useful,
4486
+but WITHOUT ANY WARRANTY; without even the implied warranty of
4487
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4488
+GNU General Public License for more details.
4489
+
4490
+You should have received a copy of the GNU General Public License
4491
+along with GNU CC; see the file COPYING.  If not, write to
4492
+the Free Software Foundation, 59 Temple Place - Suite 330,
4493
+Boston, MA 02111-1307, USA.  */
4494
+
4495
+/* Specify predefined symbols in preprocessor.  */
4496
+
4497
+#undef CPP_PREDEFINES
4498
+#define CPP_PREDEFINES "-DOR1K -Dor1k -D__or1k__ -D__OR1K__ \
4499
+  -Drtems -D__rtems__ -Asystem(rtems) -Acpu(or1k) -Amachine(or1k)"
4500
+
4501
+/* Generate calls to memcpy, memcmp and memset.  */
4502
+#ifndef TARGET_MEM_FUNCTIONS
4503
+#define TARGET_MEM_FUNCTIONS
4504
+#endif
4505
+
4506
+/* We use COFF, so we need SDB format.  */
4507
+#define SDB_DEBUGGING_INFO
4508
+
4509
+/* Get machine-independent configuration parameters for RTEMS.  */
4510
+#include <rtems.h>
4511
diff -Nru gcc-3.4.4.orig/gcc/config/or32/t-default gcc-3.4.4-DONE/gcc/config/or32/t-default
4512
--- gcc-3.4.4.orig/gcc/config/or32/t-default    1970-01-01 02:00:00.000000000 +0200
4513
+++ gcc-3.4.4-DONE/gcc/config/or32/t-default    2005-11-29 16:23:09.000000000 +0200
4514
@@ -0,0 +1,34 @@
4515
+#
4516
+# t-default is Makefile fragment to be included when
4517
+#           building gcc for or32 target
4518
+#
4519
+
4520
+# we don't support -g so don't use it
4521
+LIBGCC2_DEBUG_CFLAGS =
4522
+
4523
+TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer
4524
+
4525
+LIB1ASMSRC = or32/or32.S
4526
+LIB1ASMFUNCS = __mulsi3 __udivsi3 __divsi3 __umodsi3 __modsi3
4527
+
4528
+# These are really part of libgcc1, but this will cause them to be
4529
+# built correctly, so... [taken from t-sparclite]
4530
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
4531
+
4532
+dp-bit.c: $(srcdir)/config/fp-bit.c
4533
+       cat $(srcdir)/config/fp-bit.c > dp-bit.c
4534
+
4535
+fp-bit.c: $(srcdir)/config/fp-bit.c
4536
+       echo '#define FLOAT' > fp-bit.c
4537
+       cat $(srcdir)/config/fp-bit.c >> fp-bit.c
4538
+
4539
+# Build the libraries for both hard and soft floating point
4540
+
4541
+#MULTILIB_OPTIONS = msoft-float
4542
+#MULTILIB_DIRNAMES = soft-float
4543
+
4544
+#LIBGCC = stmp-multilib
4545
+#INSTALL_LIBGCC = install-multilib
4546
+
4547
+#LIBGCC =
4548
+#INSTALL_LIBGCC =
4549
diff -Nru gcc-3.4.4.orig/gcc/config.gcc gcc-3.4.4-DONE/gcc/config.gcc
4550
--- gcc-3.4.4.orig/gcc/config.gcc       2005-04-25 07:47:59.000000000 +0300
4551
+++ gcc-3.4.4-DONE/gcc/config.gcc       2005-12-13 17:38:36.000000000 +0200
4552
@@ -1681,6 +1681,21 @@
4553
        extra_parts=""
4554
        use_collect2=yes
4555
        ;;
4556
+or32-*-coff*)
4557
+       tm_file="${tm_file} or32/or32.h"
4558
+       tmake_file=or32/t-default
4559
+       ;;
4560
+or32-*-elf*)
4561
+       tm_file="${tm_file} dbxelf.h elfos.h or32/or32.h or32/elf.h"
4562
+       tmake_file=or32/t-default
4563
+       if test x$enable_threads = xyes; then
4564
+         thread_file='rtems'
4565
+       fi
4566
+       ;;
4567
+or32-*linux*)
4568
+       tm_file="${tm_file} dbxelf.h elfos.h or32/or32.h or32/elf.h or32/linux-gas.h or32/linux-elf.h"
4569
+       tmake_file=or32/t-default
4570
+       ;;
4571
 pdp11-*-bsd)
4572
        tm_file="${tm_file} pdp11/2bsd.h"
4573
        use_fixproto=yes

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