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Orka |
/*
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ORSoC GFX accelerator core
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Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
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PER-PIXEL COLORING MODULE, alpha blending
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This file is part of orgfx.
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orgfx is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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orgfx is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with orgfx. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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This module performs alpha blending by fetching the pixel from the target and mixing it with the texel based on the current alpha value.
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The exact formula is:
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alpha = global_alpha_i * alpha_i
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color_out = color_in * alpha + color_target * (1-alpha) , where alpha is defined from 0 to 1
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alpha_i[7:0] is used, so the actual span is 0 (transparent) to 255 (opaque)
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If alpha blending is disabled (blending_enable_i == 1'b0) the module just passes on the input pixel.
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*/
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module gfx_blender(clk_i, rst_i,
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blending_enable_i, target_base_i, target_size_x_i, target_size_y_i, color_depth_i,
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x_counter_i, y_counter_i, z_i, alpha_i, global_alpha_i, write_i, ack_o, // from fragment
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target_ack_i, target_addr_o, target_data_i, target_sel_o, target_request_o, wbm_busy_i, // from/to wbm reader
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pixel_x_o, pixel_y_o, pixel_z_o, pixel_color_i, pixel_color_o, write_o, ack_i // to render
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);
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parameter point_width = 16;
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input clk_i;
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input rst_i;
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input blending_enable_i;
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input [31:2] target_base_i;
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input [point_width-1:0] target_size_x_i;
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input [point_width-1:0] target_size_y_i;
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input [1:0] color_depth_i;
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// from fragment
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input [point_width-1:0] x_counter_i;
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input [point_width-1:0] y_counter_i;
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input signed [point_width-1:0] z_i;
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input [7:0] alpha_i;
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input [7:0] global_alpha_i;
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input [31:0] pixel_color_i;
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input write_i;
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output reg ack_o;
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// Interface against wishbone master (reader)
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input target_ack_i;
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output [31:2] target_addr_o;
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input [31:0] target_data_i;
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output reg [3:0] target_sel_o;
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output reg target_request_o;
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input wbm_busy_i;
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//to render
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output reg [point_width-1:0] pixel_x_o;
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output reg [point_width-1:0] pixel_y_o;
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output reg signed [point_width-1:0] pixel_z_o;
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output reg [31:0] pixel_color_o;
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output reg write_o;
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input ack_i;
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// State machine
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reg [1:0] state;
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parameter wait_state = 2'b00,
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target_read_state = 2'b01,
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write_pixel_state = 2'b10;
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// Calculate alpha
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reg [15:0] combined_alpha_reg;
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wire [7:0] alpha = combined_alpha_reg[15:8];
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// Calculate address of target pixel
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// Addr[31:2] = Base + (Y*width + X) * ppb
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wire [31:0] pixel_offset;
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assign pixel_offset = (color_depth_i == 2'b00) ? (target_size_x_i*y_counter_i + {16'h0, x_counter_i}) : // 8 bit
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(color_depth_i == 2'b01) ? (target_size_x_i*y_counter_i + {16'h0, x_counter_i}) << 1 : // 16 bit
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(target_size_x_i*y_counter_i + {16'h0, x_counter_i}) << 2 ; // 32 bit
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assign target_addr_o = target_base_i + pixel_offset[31:2];
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// Split colors for alpha blending (render color)
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wire [7:0] blend_color_r = (color_depth_i == 2'b00) ? pixel_color_i[7:0] :
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(color_depth_i == 2'b01) ? pixel_color_i[15:11] :
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pixel_color_i[23:16];
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wire [7:0] blend_color_g = (color_depth_i == 2'b00) ? pixel_color_i[7:0] :
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(color_depth_i == 2'b01) ? pixel_color_i[10:5] :
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pixel_color_i[15:8];
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wire [7:0] blend_color_b = (color_depth_i == 2'b00) ? pixel_color_i[7:0] :
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(color_depth_i == 2'b01) ? pixel_color_i[4:0] :
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pixel_color_i[7:0];
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// Split colors for alpha blending (from target surface)
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wire [7:0] target_color_r = (color_depth_i == 2'b00) ? dest_color[7:0] :
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(color_depth_i == 2'b01) ? dest_color[15:11] :
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target_data_i[23:16];
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wire [7:0] target_color_g = (color_depth_i == 2'b00) ? dest_color[7:0] :
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(color_depth_i == 2'b01) ? dest_color[10:5] :
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target_data_i[15:8];
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wire [7:0] target_color_b = (color_depth_i == 2'b00) ? dest_color[7:0] :
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(color_depth_i == 2'b01) ? dest_color[4:0] :
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target_data_i[7:0];
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// Alpha blending (per color channel):
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// rgb = (alpha1)(rgb1) + (1-alpha1)(rgb2)
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wire [15:0] alpha_color_r = blend_color_r * alpha + target_color_r * (8'hff - alpha);
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wire [15:0] alpha_color_g = blend_color_g * alpha + target_color_g * (8'hff - alpha);
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wire [15:0] alpha_color_b = blend_color_b * alpha + target_color_b * (8'hff - alpha);
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wire [31:0] dest_color;
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// Memory to color converter
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memory_to_color memory_proc(
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.color_depth_i (color_depth_i),
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.mem_i (target_data_i),
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.mem_lsb_i (x_counter_i[1:0]),
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.color_o (dest_color),
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.sel_o ()
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);
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// Acknowledge when a command has completed
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always @(posedge clk_i or posedge rst_i)
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begin
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// reset, init component
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if(rst_i)
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begin
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ack_o <= 1'b0;
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write_o <= 1'b0;
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pixel_x_o <= 1'b0;
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pixel_y_o <= 1'b0;
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pixel_z_o <= 1'b0;
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pixel_color_o <= 1'b0;
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target_request_o <= 1'b0;
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target_sel_o <= 4'b1111;
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end
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// Else, set outputs for next cycle
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else
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begin
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case (state)
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wait_state:
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begin
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ack_o <= 1'b0;
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if(write_i)
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begin
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if(!blending_enable_i)
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begin
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pixel_x_o <= x_counter_i;
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pixel_y_o <= y_counter_i;
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pixel_z_o <= z_i;
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pixel_color_o <= pixel_color_i;
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write_o <= 1'b1;
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end
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else
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begin
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target_request_o <= !wbm_busy_i;
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combined_alpha_reg <= alpha_i * global_alpha_i;
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end
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end
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end
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// Read pixel color at target (request is sent through the wbm reader arbiter).
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target_read_state:
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if(target_ack_i)
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begin
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// When we receive an ack from memory, calculate the combined color and send the pixel forward in the pipeline (go to write state)
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write_o <= 1'b1;
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pixel_x_o <= x_counter_i;
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pixel_y_o <= y_counter_i;
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pixel_z_o <= z_i;
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target_request_o <= 1'b0;
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// Recombine colors
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pixel_color_o <= (color_depth_i == 2'b00) ? {alpha_color_r[15:8]} : // 8 bit grayscale
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(color_depth_i == 2'b01) ? {alpha_color_r[12:8], alpha_color_g[13:8], alpha_color_b[12:8]} : // 16 bit
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{alpha_color_r[15:8], alpha_color_g[15:8], alpha_color_b[15:8]}; // 32 bit
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end
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else
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target_request_o <= !wbm_busy_i | target_request_o;
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// Ack and return to wait state
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write_pixel_state:
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begin
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write_o <= 1'b0;
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if(ack_i)
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ack_o <= 1'b1;
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end
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endcase
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end
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end
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// State machine
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always @(posedge clk_i or posedge rst_i)
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begin
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// reset, init component
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if(rst_i)
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state <= wait_state;
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// Move in statemachine
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else
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case (state)
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wait_state:
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if(write_i & blending_enable_i)
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state <= target_read_state;
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else if(write_i)
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state <= write_pixel_state;
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target_read_state:
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if(target_ack_i)
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state <= write_pixel_state;
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write_pixel_state:
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if(ack_i)
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state <= wait_state;
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endcase
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end
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endmodule
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