Subversion Repositories p9813_rgb_led_string_driver

--------------------------------------------------------------------------

-- Package of bit sync and DPLL components

--

--

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

package bit_sync_pack is

-- Component declarations not provided any more.

-- With VHDL '93 and newer, component declarations are allowed,

-- but not required.

--

-- Please to use direct instantiation instead, for example:

--

--   instance_name : entity work.entity_name(beh)

--

end bit_sync_pack;

-------------------------------------------------------------------------------

-- Maximum-cycle Linear Feedback Shift Register (MLFSR)

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : Dec. 18, 2015 Started Coding, drawing inspiration from online

--                       resources.

--         Apr. 19, 2018 Corrected the entity name to actually match the

--                       module name : mlfsr

--

-- Description

-------------------------------------------------------------------------------

-- This module applies a modulo 2 polynomial as feedback to a shift register

-- in order to generate a maximum-cycle pseudo random sequence.

-- The maximum cycle is length 2^N-1 bits, where N is the number of bits

-- in the shift register.

--

-- Generic parameters control the length of the shift register, and the

-- particular polynomial taps applied.  The polynomial is not completely

-- generic, in the sense that only up to four taps can be implemented.

-- This constraint was deemed acceptable, since for any shift register

-- of length N stages, a maximum cycle output can be obtained using either

-- two or four taps.

--

-- The polynomials are assumed to have two or four non-zero terms, in addition

-- to the zeroth order term, which is always a 1.

--

-- For those who are curious, the binary Galois representation is used here.

--

-- The tap inputs are natural numbers which represent the position of the tap

-- within the shift register.  If tap position is set to zero, then the tap is

-- not used.  Please don't get funky with this.  If you are implementing a

-- polynomial with two terms only, set POLY_C and POLY_D to zero.  POLY_A

-- sets the length of the shift register, so it must not be set to zero.

-- Is this copascetic with you?

--

-- In order to obtain a maximum cycle output, there must always be an even

-- number of taps used, and the positions of the taps must be relatively prime.

-- Note that these conditions are necessary, but not sufficient, to produce

-- the maximum-cycle output.  Any polynomial which *does* produce the maximum

-- cycle output is called "primitive." 

--

-- Many examples of primitive polynomials are listed in various tables.

-- This module was coded while referring to "Table of Linear Feedback Shift

-- Registers" by Roy Ward and Tim Molteno.

--

-- Some "primitive polynomials" are:

--   2,1

--   3,2

--   4,3

--   5,3

--   5,4,3,2

--   6,5

--   6,5,3,2

--   7,6

--   7,6,5,4

--   16,14,13,11

--   24,23,21,20

--   32,30,26,25

--   64,63,61,60

--   128,127,126,121

--   255,203

--   256,254,251,246

--   511,501

--   512,510,507,504

--   785,693

--   1024,1015,1002,1001

--   2048,2035,2034,2029

--   4096,4095,4081,4069

--

--   The number of bits in the shift register is equal to the polynomial's

--   order, and also equal to the highest tap position number.

-- 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

entity mlfsr is

    generic(

      POLY_A : natural := 8; -- Polynomial tap, also number of bits in shift register

      POLY_B : natural := 6; -- Polynomial tap, less than POLY_A

      POLY_C : natural := 5; -- Polynomial tap, less than POLY_B

      POLY_D : natural := 4  -- Polynomial tap, less than POLY_C

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- Sequence Output

      pn_seq_o   : out std_logic

    );

end mlfsr;

architecture beh of mlfsr is

  -- Constants

  -- Functions & associated types

  -- Signal Declarations

  signal sr : unsigned(POLY_A-1 downto 0);

  signal sr_next : unsigned(POLY_A-1 downto 0);

begin

process (sys_clk, sys_rst_n)

begin

  if (sys_rst_n='0') then

    sr <= (others=>'1');

  elsif (sys_clk'event and sys_clk='1') then

    if (sys_clk_en='1') then

      sr <= sr_next;

    end if; -- sys_clk_en

  end if; -- sys_clk

end process;

gen_sr_next : for i in 0 to POLY_A-2 generate

  sr_next(i) <= sr(i+1) xor sr(0) when (i=POLY_B or i=POLY_C or i=POLY_D) else

                sr(i+1);

end generate gen_sr_next;

sr_next(sr_next'length-1) <= sr(0);

pn_seq_o <= sr(0);

end beh;

-------------------------------------------------------------------------------

-- PCM signal bit period detector

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : Jan. 31, 2012 Started Coding, drawing from various other sources.

--                       Created description.

--         Feb.  6, 2012 Simulated and refined code.  Added output register.

--         Mar. 16, 2012 Made load_o a registered signal, so that the load

--                       pulses emerge when the new period information does.

--                 

--

-- Description

-------------------------------------------------------------------------------

-- This module applies a finite state machine controlled series of

-- measurements to an incoming digital data signal, and uses the measurements

-- to arrive at an estimate of the incoming signal's bit rate.

--

-- A successive approximation technique is used.

--

-- The way it works is as follows:  There are synchronizing flip-flops placed

-- to prevent metastability issues with the incoming signal.  Edge detectors

-- are then created using the outputs of these flip-flops.

--

-- The number of sys_clks between edges is then directly measured using a

-- counter, and these counts are fed into a successive approximation loop by

-- which the Baud interval (shortest interval between pulses) is first measured.

-- Then, based on this measurement, another measurement is taken over two Baud

-- intervals.  This measurement is then used as the basis for a new measurement

-- covering four Baud intervals, and so forth.  Each new measurement covers the

-- a period of 2^N Baud intervals, or bit times, where the highest N is set by

-- generics.

--

-- Note that noise can cause the initial Baud interval to be incorrect, which

-- will eventually cause the subsequent measurements to fail, and the state

-- machine will revert back and take a new Baud interval measurement.  Therefore,

-- no attempt is made to average several initial Baud interval measurements.

--

-- The result of the ultimate 2^N bit times measurement can be interpreted as a

-- measurement of the bit-period of the incoming data or clock signal, made

-- more accurate through averaging over 2^N intervals.  Therefore, the final

-- measurement of 2^Nmax Baud intervals is composed of an integer portion and

-- a fractional portion, the fractional portion being the Nmax least significant

-- bits of the period output.

--

-- By setting Nmax and taking the requisite amount of time to make the full 2^Nmax

-- bit-period measurement, results of "arbitrary precision" can therefore be

-- obtained.

--

-- The successive approximation approach is used in order to effectively home

-- in on the correct measurement, incrementally approaching the value by starting

-- with a direct measurement of the shortest interval - which is understood to

-- represent a single bit-period.  Since the signal might not have a transition

-- at every bit-period, there is a statistical component to the way in which the

-- successive approximation works.

--

-- Essentially, a number of attempts are made, starting at any given edge, and

-- extending through 2^N of the best-estimate "baud intervals" and looking for

-- another edge at around the expected time.  The edge may occur earlier or later

-- than the predicted time, and so the approach takes this into account.  Each

-- successful measurement is then multiplied by two via bit-shifting, and used

-- as the basis for the succeeding measurement.  So each measurement uses the

-- current best estimate of period, to take a new measurement which covers twice

-- as many bit times, so that each new result is essentially twice as precise

-- as its predecessor.

--

-- The number of attempts to be made for each measurement step is determined by

-- a generic setting.  The assumption is that edges are expected to be present

-- approximately 50% of the time, and so the probability of performing any given

-- measurement successfully is 1-(1/2^READS).  By setting READS sufficiently

-- high, as compared to Nmax, the overall probability of successfully 

-- "bootstrapping" all the way into a precise final bit-period measurement can

-- be made high enough to become practical and useful.

--

-- One of the important practical assumptions made about the incoming signal is

-- that the amount of jitter present in the signal edges is small compared to

-- the overall desired measurement precision.  Another assumption is that the

-- frequency drift of the incoming signal is low.  There is a "window" of

-- allowed variation from the expected edge location which this module considers

-- as "valid" measurements.  When the sum of jitter and phase variation due to

-- frequency drift produces edges that fall outside that window, the measurement

-- will fail despite the reasonably high probability that an edge is lurking

-- somewhere just outside the allowed window.

--

-- The size of the window is set via generics, and it is implemented as a +/-

-- tolerance through a clever technique in which the measurement counter during

-- the "HONE" state is allowed to count down to zero, after which it begins to

-- count up again.  At the time of the closing edge, the value in the counter is

-- compared with the window threshold, and the counter value then represents the

-- absolute value of the variation of the overall measured 2^N bit-time interval

-- from its expectation value.

--

-- It is intended that this module be instantiated multiple times inside a digital

-- bit-sync module, once for measuring the bit-period of the reference PCM data

-- signal, and once for measuring the bit-period of the generated clock.  In that

-- way the measurements will be "apples to apples" and any bias present in one

-- measurement should be identical in the other.

--

-- By comparing the measured periods, the clock signal can then be adjusted so that

-- its frequency tracks that of the incoming data signal for slow variations,

-- without requiring Fourier analysis, or the use of mathematical multipliers or

-- dividers.

--

-- This frequency tracking loop is to be a slow outer loop within the bit-sync,

-- with a faster phase tracking loop as the inner feedback loop.

-- 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

library work;

use work.function_pack.all;

entity bit_period_detector is

    generic(

      USE_ANY_EDGE   : integer := 1; -- 0=Rising edges only, 1=Use any edge

      WINDOW_SIZE    : integer := 2; -- sys_clk variation allowed around closing edge

      IDLE_CLOCKS    : integer := 511; -- sys_clk periods before input "idle" is called

      BAUD_READS     : integer := 255; -- Number of baud interval transition measurements tried

      INTERVAL_READS : integer := 16; -- Number of 2^N interval read attempts to make

      INTEGER_WIDTH  : integer := 16; -- Bits in integer part of period measurement

      FRACTION_WIDTH : integer := 4  -- Bits in fractional part of period measurement

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- Signal input

      signal_i   : in  std_logic;

      -- outputs

      s_edge_o   : out std_logic; -- Strobe marking edges of signal_i which are used.

      period_o   : out unsigned(INTEGER_WIDTH+FRACTION_WIDTH-1 downto 0);

      load_o     : out std_logic;

      idle_o     : out std_logic

    );

end bit_period_detector;

architecture beh of bit_period_detector is

  -- Constants

  constant IDLE_COUNT_WIDTH     : integer := timer_width(IDLE_CLOCKS);

  constant BAUD_COUNT_WIDTH     : integer := timer_width(BAUD_READS);

  constant INTERVAL_COUNT_WIDTH : integer := bit_width(INTERVAL_READS);

  constant PERIOD_WIDTH         : integer := INTEGER_WIDTH+FRACTION_WIDTH;

  constant N_WIDTH              : integer := timer_width(FRACTION_WIDTH);

  -- Functions & associated types

  -- Signal Declarations

  signal period       : unsigned(PERIOD_WIDTH-1 downto 0);

  signal s_r1         : std_logic;

  signal s_r2         : std_logic;

  signal s_edge       : std_logic;

  signal c_count      : unsigned(PERIOD_WIDTH-1 downto 0); -- Used to count sys_clks between transitions

  signal c_count_next : unsigned(PERIOD_WIDTH-1 downto 0); -- This is c_count+1

  signal c_count_x2   : unsigned(PERIOD_WIDTH-1 downto 0);

  signal p_count      : unsigned(PERIOD_WIDTH-1 downto 0); -- Used to count sys_clks to window closure

  signal p_count_dir  : std_logic; -- High=counting up, Low=counting down

  signal baud_tries   : unsigned(BAUD_COUNT_WIDTH-1 downto 0); -- Counts baud interval assessments

  signal period_tries : unsigned(INTERVAL_COUNT_WIDTH-1 downto 0); -- Counts period interval assessments

  signal idle_count   : unsigned(IDLE_COUNT_WIDTH-1 downto 0); -- Counts sys_clk periods with no signal transition

  type P_STATE_TYPE is (IDLE, MEASURE_BAUD, HONE);

  signal p_state      : P_STATE_TYPE;

  signal n            : unsigned(N_WIDTH-1 downto 0);

begin

c_count_next <= c_count+1;

--c_count_x2   <= c_count_next(c_count_next'length-2 downto 0) & '0';

--c_count_x2   <= c_count_next + c_count; -- An attempt to "dither" or eliminate bias...

c_count_x2 <= c_count(c_count'length-2 downto 0) & '1';

process (sys_clk, sys_rst_n)

begin

  if (sys_rst_n='0') then

    s_r1         <= '0';

    s_r2         <= '0';

    c_count      <= (others=>'0');

    p_count      <= (others=>'1');

    p_count_dir  <= '0'; -- Counts down, until zero is reached...

    baud_tries   <= (others=>'0');

    period_tries <= (others=>'0');

    idle_count   <= to_unsigned(IDLE_CLOCKS,idle_count'length);

    period       <= (others=>'0');

    p_state      <= IDLE;

    n            <= (others=>'0');

    period_o     <= (others=>'1');

    load_o       <= '0';

  elsif (sys_clk'event and sys_clk='1') then

    if (sys_clk_en='1') then

      -- Defaults

      load_o <= '0';

      -- Two layers of flip-flops, to mitigate metastability

      s_r1 <= signal_i;

      s_r2 <= s_r1;

      -- Update the period counter

      -- It can be cleared by other logic statements below

      c_count <= c_count_next;

      -- Update the window counter

      -- It can be cleared by other logic statements below

      if (p_count_dir='1') then

        p_count <= p_count+1;

      else

        -- When counting down, there is a counter direction reversal

        -- which is used for implementing the tracking window +/-

        if (p_count=0) then

          p_count_dir <= p_count_dir xor '1';

          p_count <= p_count+1;

        else

          p_count <= p_count-1;

        end if;

      end if;

      -- Period State Machine

      case (p_state) is

        when IDLE =>

          if (s_edge='1') then

            p_state     <= MEASURE_BAUD;

            period      <= (others=>'1');

            p_count     <= (others=>'1');

            p_count_dir <= '0';

            c_count     <= (others=>'0');

            n           <= (others=>'0');

          end if;

        when MEASURE_BAUD =>

          if (s_edge='1') then

            if (baud_tries=BAUD_READS) then

              baud_tries   <= (others=>'0');

              period_tries <= (others=>'0');

              p_state      <= HONE;

              p_count      <= period;

              p_count_dir  <= '0'; -- Count down for HONE

              c_count      <= (others=>'0');

            else

              baud_tries <= baud_tries+1;

              if (c_count_next<period) then

                period <= c_count_next;

              end if;

              c_count <= (others=>'0');

            end if;

          end if;

        when HONE =>

          -- look for edges

          if (s_edge='1') then

            if (p_count <= WINDOW_SIZE) then

              if (n<FRACTION_WIDTH) then

                period      <= c_count_x2;

                p_count     <= c_count_x2;

                p_count_dir <= '0'; -- Count down

                c_count     <= (others=>'0');

                n           <= n+1;

              elsif n=FRACTION_WIDTH then

                p_state     <= MEASURE_BAUD;

                period      <= (others=>'1');

                p_count     <= (others=>'1');

                p_count_dir <= '0';

                c_count     <= (others=>'0');

                n           <= (others=>'0');

                period_o    <= c_count;

                load_o      <= '1';

              end if;

            elsif (p_count_dir='1') then -- If the window has passed...

              if (period_tries<INTERVAL_READS-1) then

                period_tries <= period_tries+1;

                -- Adjust the period slightly, to improve odds of success with a tight window...

                --p_count      <= period-1;

                p_count      <= period;

                p_count_dir  <= '0'; -- Count down

                c_count      <= (others=>'0');

              else

                p_state     <= MEASURE_BAUD;

                period      <= (others=>'1');

                p_count     <= (others=>'1');

                p_count_dir <= '0';

                c_count     <= (others=>'0');

                n           <= (others=>'0');

              end if;

            end if;

          end if; -- s_edge='1'

      end case;

      -- Update the idle counter

      -- This must follow the state transition logic, since it can

      -- override it, and force the state to IDLE

      if (s_edge='1') then

        idle_count <= to_unsigned(IDLE_CLOCKS,idle_count'length);

      else

        if (idle_count=0) then

          p_state <= IDLE;

        else

          idle_count <= idle_count-1;

        end if;

      end if;

    end if; -- sys_clk_en

  end if; -- sys_clk

end process;

-- Implement edge detector.  Generic determines if all edges are used, or

-- just the rising edges.

s_edge <= s_r1 xor s_r2 when (USE_ANY_EDGE=1) else s_r1 and not s_r2;

s_edge_o <= s_edge;

idle_o <= '1' when p_state=IDLE else '0';

end beh;

-------------------------------------------------------------------------------

-- PCM signal period histogram checker

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : May   8, 2013 Copied code from bit_period_detector,

--                       Created description.

--         May  16, 2013 Checked the unit using simulation, and it

--                       looks pretty good.  Added ODD_N_LIMIT generic

--                       to prevent long intervals from always ending

--                       up in the oddball bin, due to uncertainty

--                       in measurement of the Baud interval.

--         Aug.  8, 2013 Corrected mathematical error in the averaging

--                       signal, and added i_count_b resets during

--                       Baud interval measurements, to prevent idle

--                       detection logic from triggering erroneously.

--         July 21, 2015 Added logic to prevent freq accumulator from

--                       missing counts when i_count_b>=ODD_N_LIMIT.

--

-- Description

-------------------------------------------------------------------------------

-- This module uses a finite state machine and some counters and comparators

-- to measure the Baud interval of an incoming signal.  In other words, it

-- measures the shortest interval between signal edges, in units of sys_clks.

--

-- The unit takes measurements constantly.  However, when the input is

-- idle, then no histogram data is updated as the unit remains in the

-- Baud interval measurement mode.

--

-- Once activity is detected on the selected signal input, a series of

-- intrvls_i intervals is measured with the true signal to find a Baud

-- interval measurement.  Following this, another series of the same

-- number of intervals is taken, but this time with the input signal

-- inverted.  The two results are compared.  If the two results differ by

-- more than +/- window_i sys_clks, then the signal is declared to have a

-- duty cycle which is unacceptably far from 50%, and the bad_duty_o

-- output is asserted.

--

-- After an acceptable duty cycle is found, the Baud interval is calculated

-- as the average of both the true and inverted signal Baud interval

-- measurements, and this value is updated to the output baud_o.

--

-- Following the baud interval cycle, the unit switches into histogram

-- and frequency measurement mode.  The internal histogram bin counters

-- are reset, and a set of intrvls_i intervals is measured.  Each

-- interval is analyzed to see if it is within +/- window_i sys_clks of

-- an integer multiple N of the Baud interval.  Based on the N value

-- found by the analysis, the appropriate histogram bin count is incremented.

-- Each interval found which is outside the allowable +/- variation is

-- an "oddball" interval, resulting in incrementing the bo_count value.

--

-- <<<Editorial Note>>>

-- (Skip this note if you don't feel super excited about the analysis of

--  PCM telemetry waveforms.)

--

-- During simulation, it was found that the uncertainty in measuring long

-- intervals, being cumulative, causes the oddball count bin to be

-- incremented when in the purest sense it should not be.  This is due

-- to the inability of this module to measure Baud intervals with

-- fractional accuracy.  Although more precise Baud average measurements

-- could be performed fairly easily, it would neccesitate a complete

-- rewrite of this unit in order to divide a measured interval by the

-- precise Baud interval.  Such subtlety is beyond the scope of this

-- effort.  Therefore, the "oddball" bin count will only be incremented

-- for N values less than the constant ODD_N_LIMIT.  Intervals longer

-- than this will not be considered oddball, effectively allowing

-- them to be properly counted in the bn_count bin.

-- <<<End Editorial Note>>>

--

-- When the entire set of intrvls_i intervals have been measured and

-- analyzed, the histogram counts are updated to the outputs, and the

-- process is repeated again.

--

-- Histogram bins are defined as follows:

--

--   b1_count = # of intervals equal to the Baud interval

--   b2_count = # of intervals equal to 2x the Baud interval

--   b3_count = # of intervals in which N is in the range [3..bo_limit_i]

--   bn_count = # of intervals in which N exceeds bo_limit_i

--   bo_count = # of oddball intervals

--

-- The idea behind this histogram is that squarewave clocks, such as the

-- self-test 10kHz "IO_sense" signal, result in histograms with high

-- totals in the b1 bin only, while biphase signals result in histograms

-- with high totals in the b1 and b2 bins, with an expected equal split.

-- NRZ-L and RNRZ-L will produce non-zero counts in the b3 bin.  NRZ-L

-- can produce non-negligible counts in the bn bin, depending on the

-- longest runs of zero or one present in the signal, while the RNRZ-L

-- input will yield a zero value in the bn bin, for suitably chosen

-- n_value_i.

--

-- Whenever bo_count exceeds the bo_limit_i threshold, the unit exits

-- histogram and frequency measurement mode, and reverts back to the

-- baud interval and duty cycle checking mode, without erasing any

-- previous measurements which are present at the outputs.

-- 

-- While in histogram population mode, a simultaneous frequency

-- measurement is being performed.  After each successful interval analysis,

-- the resulting N value is accumulated into a running total.  After

-- one second of operation, the accumulator value represents the frequency

-- of baud intervals per second, hence the symbol frequency from which

-- bit rate can be immediately deduced.  Each one second interval frequency

-- reading is updated to the output register, the accumulator is cleared,

-- and the frequency measurement process proceeds onward for another

-- second.

-- 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

library work;

use work.function_pack.all;

entity period_histogram_checker is

    generic(

      SYS_CLK_RATE   : real    := 50000000.0;

      NUM_CHAN       : natural := 8;  -- Number of channels to select from

      LOG2_NUM_CHAN  : natural := 3;  -- Bits needed for channel selection

      ODD_N_LIMIT    : natural := 4;  -- Upper cutoff for bo_count_o intervals to be tallied

      PERIOD_BITS    : natural := 14; -- Number of bits in Baud interval measurement

      HIST_BITS      : natural := 8   -- Number of bits in histogram bin counters

    );

    port (

      -- System Clock and Clock Enable

      sys_rst_n  : in  std_logic;

      sys_clk    : in  std_logic;

      sys_clk_en : in  std_logic;

      -- PCM signal inputs

      pcm_i      : in  unsigned(NUM_CHAN-1 downto 0);

      -- Settings & Control

      pcm_sel_i  : in  unsigned(LOG2_NUM_CHAN-1 downto 0);

      window_i   : in  unsigned(3 downto 0); -- sys_clks of variation allowed when checking intervals

      intrvls_i  : in  unsigned(HIST_BITS-1 downto 0); -- Number of intervals per histogram

      bo_limit_i : in  unsigned(HIST_BITS-1 downto 0); -- Number of oddball intervals tolerated per histogram cycle.

      n_value_i  : in  unsigned(4 downto 0); -- N value for bn_count histogram bin

      -- outputs

      bad_duty_o : out std_logic;

      b1_count_o : out unsigned(HIST_BITS-1 downto 0);

      b2_count_o : out unsigned(HIST_BITS-1 downto 0);

      b3_count_o : out unsigned(HIST_BITS-1 downto 0);

      bn_count_o : out unsigned(HIST_BITS-1 downto 0);

      bo_count_o : out unsigned(HIST_BITS-1 downto 0);

      baud_o     : out unsigned(PERIOD_BITS-1 downto 0);

      freq_o     : out unsigned(31 downto 0);

      idle_o     : out std_logic; -- High indicates signal is inactive for too long.

      new_o      : out std_logic  -- High pulse indicates new measurements were posted.

    );

end period_histogram_checker;

architecture beh of period_histogram_checker is

  -- Constants

  constant SECOND_BITS : natural := timer_width(SYS_CLK_RATE);

  -- Functions & associated types

  -- Signal Declarations

  signal baud_count   : unsigned(PERIOD_BITS-1 downto 0);

  signal baud_p_val   : unsigned(PERIOD_BITS-1 downto 0);

  signal baud_n_val   : unsigned(PERIOD_BITS-1 downto 0);

  signal baud_delta   : unsigned(3 downto 0);

  signal intrvl_delta : unsigned(3 downto 0);

  signal baud_sum     : unsigned(PERIOD_BITS downto 0);

  signal baud_avg     : unsigned(PERIOD_BITS-1 downto 0);

  signal i_count_a    : unsigned(PERIOD_BITS-1 downto 0);

  signal i_count_b    : unsigned(10 downto 0); -- up to 2047 symbol periods per interval

  signal baud_num     : unsigned(HIST_BITS-1 downto 0);

  signal intrvl_num   : unsigned(HIST_BITS-1 downto 0);

  signal b1_count     : unsigned(HIST_BITS-1 downto 0);

  signal b2_count     : unsigned(HIST_BITS-1 downto 0);

  signal b3_count     : unsigned(HIST_BITS-1 downto 0);

  signal bn_count     : unsigned(HIST_BITS-1 downto 0);

  signal bo_count     : unsigned(HIST_BITS-1 downto 0);

  signal freq         : unsigned(31 downto 0);

  signal second_count : unsigned(SECOND_BITS-1 downto 0);

  type P_STATE_TYPE is (BAUD_P1, BAUD_P2, BAUD_N1, BAUD_N2, DUTY_CHECK, HISTO1, HISTO2);

  signal p_state      : P_STATE_TYPE;

  signal s_r1         : std_logic;

  signal s_r2         : std_logic;

  signal s_edge       : std_logic;

  signal s_rising     : std_logic;

  signal s_falling    : std_logic;

  signal idle         : std_logic;

  signal pcm_sel_r1   : unsigned(LOG2_NUM_CHAN-1 downto 0);

begin

-- Provide outputs

baud_sum <= resize(baud_p_val,baud_sum'length) + resize(baud_n_val,baud_sum'length);

baud_avg <= baud_sum(baud_sum'length-1 downto 1); -- Divide by 2

idle_o <= idle;

-- Form edge detectors

s_edge <= s_r1 xor s_r2;

s_rising <= '1' when s_r1='1' and s_r2='0' else '0';

s_falling <= '1' when s_r1='0' and s_r2='1' else '0';

-- Form difference between positive and negative Baud intervals

baud_delta <= resize(unsigned(abs(signed(baud_p_val)-signed(baud_n_val))),baud_delta'length);

-- Form difference between interval subtraction remainder and Baud intervals

intrvl_delta <= resize(baud_avg-i_count_a,intrvl_delta'length);

-- State machine

process (sys_clk, sys_rst_n)