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jclaytons |
-- A package containing various conversion functions
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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package function_pack is
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------------------------------------------------------------------------------------
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-- function calls
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------------------------------------------------------------------------------------
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function char2u(in_char : character) return unsigned;
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function str2u(in_string : string; out_size:integer) return unsigned;
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function asciichar2u2(d:character) return unsigned; -- Loosely based on code in Thesis by Rudi Rughoonundon, 11-1-1996
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function str2u(s: string) return unsigned;
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function u_reverse(in_vect : unsigned) return unsigned;
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function u_recursive_parity ( x : unsigned ) return std_logic;
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function bit_width (maxval : integer) return integer;
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function bit_width (maxval : real) return integer;
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function timer_width (maxval : integer) return integer;
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function timer_width (maxval : real) return integer;
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end function_pack;
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package body function_pack is
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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function char2u(in_char : character) return unsigned is
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variable out_vec : unsigned(3 downto 0);
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begin
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case in_char is
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when '0' => out_vec := "0000";
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when '1' => out_vec := "0001";
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when '2' => out_vec := "0010";
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when '3' => out_vec := "0011";
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when '4' => out_vec := "0100";
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when '5' => out_vec := "0101";
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when '6' => out_vec := "0110";
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when '7' => out_vec := "0111";
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when '8' => out_vec := "1000";
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when '9' => out_vec := "1001";
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when 'A' | 'a' => out_vec := "1010";
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when 'B' | 'b' => out_vec := "1011";
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when 'C' | 'c' => out_vec := "1100";
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when 'D' | 'd' => out_vec := "1101";
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when 'E' | 'e' => out_vec := "1110";
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when 'F' | 'f' => out_vec := "1111";
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when others =>
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out_vec := "0000";
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end case;
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return out_vec;
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end char2u;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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function str2u(in_string : string; out_size:integer) return unsigned is
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variable uval : unsigned(out_size-1 downto 0);
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variable nibble : unsigned(3 downto 0);
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begin
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uval := (others=>'0');
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for j in in_string'range loop
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uval(uval'length-1 downto 4) := uval(uval'length-5 downto 0);
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uval(3 downto 0) := char2u(in_string(j));
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end loop;
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return uval;
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end str2u;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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function asciichar2u2(d:character) return unsigned is
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variable dout : unsigned(0 to 7);
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variable ascii_int : integer := 0;
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variable val : integer := 0;
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begin
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-- Get integer value of the character
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ascii_int := character'pos(d);
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for index in dout'range loop
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val := ascii_int rem 2;
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ascii_int := ascii_int/2;
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if val=0 then
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dout(dout'high-index):='0';
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else
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dout(dout'high-index):='1';
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end if;
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end loop;
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return dout;
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end asciichar2u2;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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-- converts a string into std_logic_vector
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function str2u(s: string) return unsigned is
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variable uv: unsigned(8*s'high-1 downto 0);
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variable k: integer;
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begin
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k := s'high-s'low;
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for i in s'range loop
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-- uv(8*k+7 downto 8*k) := unsigned(chartobyte(s(i)));
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uv(8*k+7 downto 8*k) := asciichar2u2(s(i));
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k := k - 1;
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end loop;
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return uv;
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end str2u;
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------------------------------------------------------------------------------------
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-- Bit Reverses the input vector
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------------------------------------------------------------------------------------
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function u_reverse(in_vect : unsigned) return unsigned is
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variable i : integer;
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variable o_vect : unsigned(in_vect'length-1 downto 0);
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begin
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for i in in_vect'length-1 downto 0 loop
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o_vect(in_vect'length-1-i) := in_vect(i);
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end loop;
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return(o_vect);
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end u_reverse;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--* Title : TEST_PARITY
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--* Filename & Ext : test_parity.vhdl
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--* Author : David Bishop X-66788
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--* Created : 3/18/97
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--* Version : 1.2
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--* Revision Date : 97/04/15
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--* SCCSid : 1.2 04/15/97 test_parity.vhdl
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--* WORK Library : testchip
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--* Mod History :
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--* Description : This is a parity generator which is written recursively
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--* : It is designed to test the ability of Simulation and
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--* : Synthesis tools to check this capability.
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--* Known Bugs :
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--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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function u_recursive_parity ( x : unsigned ) return std_logic is
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variable Upper, Lower : std_logic;
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variable Half : integer;
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variable BUS_int : unsigned( x'length-1 downto 0 );
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variable Result : std_logic;
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begin
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BUS_int := x;
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if ( BUS_int'length = 1 ) then
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Result := BUS_int ( BUS_int'left );
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elsif ( BUS_int'length = 2 ) then
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Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left );
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else
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Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
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Upper := u_recursive_parity ( BUS_int ( BUS_int'left downto Half ));
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Lower := u_recursive_parity ( BUS_int ( Half - 1 downto BUS_int'right ));
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Result := Upper xor Lower;
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end if;
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return Result;
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end;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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function bit_width (maxval : integer) return integer is
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variable w : integer;
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begin
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if (maxval<2) then
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w := 1;
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else
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w := integer(ceil(log2(real(maxval))));
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end if;
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return w;
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end bit_width;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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function bit_width (maxval : real) return integer is
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variable w : integer;
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begin
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if (maxval<2.0) then
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w := 1;
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else
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w := integer(ceil(log2(maxval)));
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end if;
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return w;
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end bit_width;
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------------------------------------------------------------------------------------
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-- Timer width differs from bit width in the following way:
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-- Bit width gives a vector large enough to have maxval different states, but
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-- timer width gives a vector large enough to hold the quantity maxval.
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--
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-- The difference is critical when using timers, since they often count down from
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-- the initial value, and trigger timeout at a value of 1... So for maxval equal
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-- to a power of two, an extra bit must be reserved. This is done by adding one
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-- to the maxval input...
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------------------------------------------------------------------------------------
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function timer_width (maxval : integer) return integer is
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variable w : integer;
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begin
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if (maxval<2) then
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w := 1;
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else
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w := integer(ceil(log2(real(maxval+1))));
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end if;
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return w;
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end timer_width;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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function timer_width (maxval : real) return integer is
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variable w : integer;
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begin
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if (maxval<2.0) then
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w := 1;
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else
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w := integer(ceil(log2(maxval+1.0)));
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end if;
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return w;
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end timer_width;
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end function_pack;
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