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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>Data Memory</title>
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<link href="doxygen.css" rel="stylesheet" type="text/css">
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</head><body>
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<!-- Generated by Doxygen 1.2.16 -->
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<center>
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<a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="pages.html">Related Pages</a> </center>
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<hr><h1>Data Memory<br>
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<small>
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[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
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</h1><table border=0 cellpadding=0 cellspacing=0>
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</table>
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<dl compact><dt><b>
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Data Memory connectivity</b><dd>
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<br>
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<div align="center">
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<img src="pavr_hwres_dm_01.gif" alt="pavr_hwres_dm_01.gif">
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</div>
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<br>
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The Data Memory is a single port RAM. <br>
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That port provides both read and write DM accesses. <br>
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The DM is organized on bytes, and has the length set by a constant in the constants definition file (`pavr-constants.vhd'). <br>
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<br>
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</dl><dl compact><dt><b>
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Requests to DM</b><dd>
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Requests to access DM come only from the DACU: <br>
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<ul>
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<li>pavr_s5_dacu_dmrd_rq <br>
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<li>pavr_s5_dacu_dmwr_rq <br>
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<br>
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</ul>
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</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by
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<a href="http://www.doxygen.org/index.html">
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<img src="doxygen.png" alt="doxygen" align="middle" border=0
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width=110 height=53></a>1.2.16 </small></address>
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</body>
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</html>
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