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[/] [pavr/] [trunk/] [src/] [pavr_control.vhd] - Blame information for rev 6

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1 4 doru 
-- <File header>
2 
-- Project
3 
--    pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
4 
--    AVR core, but about 3x faster in terms of both clock frequency and MIPS.
5 
--    The increase in speed comes from a relatively deep pipeline. The original
6 
--    AVR core has only two pipeline stages (fetch and execute), while pAVR has
7 
--    6 pipeline stages:
8 
--       1. PM    (read Program Memory)
9 
--       2. INSTR (load Instruction)
10 
--       3. RFRD  (decode Instruction and read Register File)
11 
--       4. OPS   (load Operands)
12 
--       5. ALU   (execute ALU opcode or access Unified Memory)
13 
--       6. RFWR  (write Register File)
14 
-- Version
15 
--    0.32
16 
-- Date
17 
--    2002 August 07
18 
-- Author
19 
--    Doru Cuturela, doruu@yahoo.com
20 
-- License
21 
--    This program is free software; you can redistribute it and/or modify
22 
--    it under the terms of the GNU General Public License as published by
23 
--    the Free Software Foundation; either version 2 of the License, or
24 
--    (at your option) any later version.
25 
--    This program is distributed in the hope that it will be useful,
26 
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
27 
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28 
--    GNU General Public License for more details.
29 
--    You should have received a copy of the GNU General Public License
30 
--    along with this program; if not, write to the Free Software
31 
--    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
32 
-- </File header>
33 
 
34 
 
35 
 
36 
-- <File info>
37 
-- This file contains the control structure of the pAVR controller. That is, the
38 
--    pipeline.
39 
-- The pipeline stages are pretty much decoupled from each other. The pipeline is
40 
--    initialized in stage 3 (s3) with values from the instruction decoder.
41 
--    Basically, each pipeline stage receives values from the previous one, in a
42 
--    shift-like flow. The `terminal' registers contain data actually used, the
43 
--    previous ones are just used for synchronization. Exceptions from this
44 
--    `normal' flow are the stall and flush actions, which can basically
45 
--    independently stall or reset to zero (force a nop into) any stage. Other
46 
--    exceptions are when several registers in such a chain are actually used,
47 
--    not only the terminal one.
48 
--    The terminology used reflects the data flow. For example,
49 
--    `pavr_s4_s6_rfwr_addr1' is assigned in s3 (by the instruction decoder),
50 
--    shifts into `pavr_s5_s6_rfwr_addr1', that finally shifts into
51 
--    `pavr_s6_rfwr_addr1' (terminal register). Only this one carries information
52 
--    actually used by hardware resource managers. This particualr one signalizes
53 
--    an access request to the Register File write port manager.
54 
-- Process splitting strategy:
55 
--    - requests to hardware resources are managed by dedicated processes, one
56 
--       process per hardware resource.
57 
--       Main hardware resources:
58 
--          - Register File (RF)
59 
--          - Bypass Unit (BPU)
60 
--             - ByPass Register 0 (ByPass chain 0) (BPR0)
61 
--             - ByPass Register 1 (ByPass chain 1) (BPR1)
62 
--             - ByPass Register 2 (ByPass chain 2) (BPR2)
63 
--          - IO File (IOF)
64 
--          - Status Register (SREG)
65 
--          - Stack Pointer (SP)
66 
--          - Arithmetic and Logic Unit (ALU)
67 
--          - Data Access Control Unit (DACU)
68 
--          - Program Memory (PM)
69 
--          - Stall and Flush Unit (SFU)
70 
--    - an asynchronous main process (instruction decoder) computes values that
71 
--    initialize the pipeline in s3.
72 
--    - a main synchronous process assings new values to pipeline registers.
73 
--       - loading a register that belongs to the pipeline is conditioned by 2
74 
--          stage-specific signals (written here in descending priority order):
75 
--          - if stage_flush=1 then the register is reseted to zero.
76 
--          - if stage_stall=1 then the register is not modified.
77 
--          - if neither stall nor flush are requested, load the register with:
78 
--             - the values from the instruction decoder, if stage = 3 (s3)
79 
--             - some particular values if stage = s1 or s2 (values set by the PM
80 
--                manager)
81 
--             - the values from the previous stage, if stage != s1 or s2 or s3
82 
-- To do
83 
--    - Define multiplication in ALU.
84 
--       For now, the ALU returns 0 when provided a multiplication ALU opcode.
85 
--       However, the pAVR pipeline does its job. Multiplication instructions
86 
--       are decoded and executed OK.
87 
--    - Replace all those wires named `next...' with a (pretty wide) state
88 
--       decoder.
89 
--    - Branch prediction with hashed branch prediction table and 2 bit predictor.
90 
-- </File info>
91 
 
92 
 
93 
 
94 
-- <File body>
95 
library work;
96 
use work.std_util.all;
97 
use work.pavr_util.all;
98 
use work.pavr_constants.all;
99 
library ieee;
100 
use ieee.std_logic_1164.all;
101 
 
102 
 
103 
 
104 
 
105 
 
106 
 
107 
entity pavr is
108 
   port(
109 
      pavr_clk:     in std_logic;
110 
      pavr_res:     in std_logic;
111 
      pavr_syncres: in std_logic;
112 
 
113 
      -- Program Memory interface
114 
      pavr_pm_addr: out std_logic_vector(21 downto 0);
115 
      pavr_pm_do:   in  std_logic_vector(15 downto 0);
116 
      pavr_pm_wr:   out std_logic;
117 
 
118 
      -- IO interface
119 
      -- A single 8 bit port is implemented. It has, as alternate functions,
120 
      --    external interrupt 0 on pin 0, and timer 0 clock input on pin 1.
121 
      pavr_pa: inout std_logic_vector(7 downto 0);
122 
 
123 
      -- <DEBUG>
124 
      -- This is used for testing purposes only, for instruction counting.
125 
      pavr_inc_instr_cnt: out std_logic_vector(1 downto 0)
126 
      -- </DEBUG>
127 
   );
128 
end;
129 
 
130 
 
131 
 
132 
 
133 
 
134 
 
135 
architecture pavr_arch of pavr is
136 
 
137 
   -- Wires -------------------------------------------------------------------
138 
 
139 
   -- RF read port 1-related
140 
   signal pavr_s3_rfrd1_rq       : std_logic;
141 
   signal pavr_s5_dacu_rfrd1_rq  : std_logic;                     -- Note 1: outside pipeline
142 
 
143 
   signal pavr_s3_rfrd1_addr     : std_logic_vector(4 downto 0);
144 
 
145 
   -- RF read port 2-related
146 
   signal pavr_s3_rfrd2_rq    : std_logic;
147 
 
148 
   signal pavr_s3_rfrd2_addr  : std_logic_vector(4 downto 0);
149 
 
150 
   -- RF write port-related
151 
   signal next_pavr_s4_s6_aluoutlo8_rfwr_rq  : std_logic;
152 
   signal next_pavr_s4_s61_aluouthi8_rfwr_rq : std_logic;
153 
   signal next_pavr_s4_s6_iof_rfwr_rq        : std_logic;
154 
   signal next_pavr_s4_s6_dacu_rfwr_rq       : std_logic;
155 
   signal next_pavr_s4_s6_pm_rfwr_rq         : std_logic;
156 
   signal pavr_s5_dacu_rfwr_rq               : std_logic;         -- Note 1
157 
 
158 
   signal next_pavr_s4_s6_rfwr_addr1      : std_logic_vector(4 downto 0);
159 
   signal next_pavr_s4_s61_rfwr_addr2     : std_logic_vector(4 downto 0);
160 
   signal pavr_s5_dacu_rfwr_di            : std_logic_vector(7 downto 0);  -- Note 1
161 
 
162 
   -- Pointer registers-related
163 
   signal next_pavr_s4_s5_ldstincrampx_xwr_rq   : std_logic;
164 
   signal next_pavr_s4_s5_ldstdecrampx_xwr_rq   : std_logic;
165 
 
166 
   signal next_pavr_s4_s5_ldstincrampy_ywr_rq   : std_logic;
167 
   signal next_pavr_s4_s5_ldstdecrampy_ywr_rq   : std_logic;
168 
 
169 
   signal next_pavr_s4_s5_ldstincrampz_zwr_rq   : std_logic;
170 
   signal next_pavr_s4_s5_ldstdecrampz_zwr_rq   : std_logic;
171 
   signal next_pavr_s4_s5_elpmincrampz_zwr_rq   : std_logic;
172 
   signal next_pavr_s4_s5_lpminc_zwr_rq         : std_logic;
173 
 
174 
   -- BPU read
175 
   signal pavr_xbpu: std_logic_vector(15 downto 0);
176 
   signal pavr_ybpu: std_logic_vector(15 downto 0);
177 
   signal pavr_zbpu: std_logic_vector(15 downto 0);
178 
 
179 
   -- BPU write, BPR0-related
180 
   signal next_pavr_s4_s5_alu_bpr0wr_rq      : std_logic;
181 
   signal next_pavr_s4_s6_iof_bpr0wr_rq      : std_logic;
182 
   signal next_pavr_s4_s6_daculd_bpr0wr_rq   : std_logic;
183 
   signal pavr_s5_dacust_bpr0wr_rq           : std_logic;   -- Note 1
184 
   signal next_pavr_s4_s6_pmdo_bpr0wr_rq     : std_logic;
185 
 
186 
   signal next_pavr_bpr0         : std_logic_vector(7 downto 0);
187 
   signal next_pavr_bpr0_addr    : std_logic_vector(4 downto 0);
188 
   signal next_pavr_bpr0_active  : std_logic;
189 
 
190 
   -- BPU write, BPR1-related
191 
   signal next_pavr_s4_s5_dacux_bpr12wr_rq   : std_logic;
192 
   signal next_pavr_s4_s5_dacuy_bpr12wr_rq   : std_logic;
193 
   signal next_pavr_s4_s5_dacuz_bpr12wr_rq   : std_logic;
194 
   signal next_pavr_s4_s5_alu_bpr1wr_rq      : std_logic;
195 
 
196 
   signal next_pavr_bpr1         : std_logic_vector(7 downto 0);
197 
   signal next_pavr_bpr1_addr    : std_logic_vector(4 downto 0);
198 
   signal next_pavr_bpr1_active  : std_logic;
199 
 
200 
   -- BPU write, BPR2-related
201 
 
202 
   signal next_pavr_bpr2         : std_logic_vector(7 downto 0);
203 
   signal next_pavr_bpr2_addr    : std_logic_vector(4 downto 0);
204 
   signal next_pavr_bpr2_active  : std_logic;
205 
 
206 
   -- IOF port-related
207 
   signal next_pavr_s4_s5_iof_rq          : std_logic;
208 
   signal next_pavr_s4_s6_iof_rq          : std_logic;
209 
   signal pavr_s5_dacu_iof_rq             : std_logic;            -- Note 1
210 
 
211 
   signal next_pavr_s4_s5_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
212 
   signal next_pavr_s4_s6_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
213 
   signal next_pavr_s4_s5s6_iof_addr      : std_logic_vector(5 downto 0);
214 
   signal next_pavr_s4_s5s6_iof_bitaddr   : std_logic_vector(2 downto 0);
215 
   signal pavr_s5_dacu_iofwr_di           : std_logic_vector(7 downto 0);  -- Note 1
216 
 
217 
   -- SREG-related
218 
   signal next_pavr_s4_s5_alu_sregwr_rq      : std_logic;
219 
   signal next_pavr_s4_s5_clriflag_sregwr_rq : std_logic;
220 
   signal next_pavr_s4_s5_setiflag_sregwr_rq : std_logic;
221 
 
222 
   -- SP-related
223 
   signal next_pavr_s4_s5_inc_spwr_rq           : std_logic;
224 
   signal next_pavr_s4_s5_dec_spwr_rq           : std_logic;
225 
   signal next_pavr_s4_s5s51s52_calldec_spwr_rq : std_logic;
226 
   signal next_pavr_s4_s5s51_retinc_spwr_rq     : std_logic;
227 
 
228 
   -- ALU-related
229 
   signal next_pavr_s4_s5_alu_opcode         : std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
230 
   signal next_pavr_s4_s5_alu_op1_hi8_sel    : std_logic;
231 
   signal next_pavr_s4_s5_alu_op2_sel        : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0);
232 
   signal next_pavr_s4_s5_k8                 : std_logic_vector(7 downto 0);
233 
   signal pavr_s5_op1bpu                     : std_logic_vector(7 downto 0);        -- Note 1
234 
   signal pavr_s5_op2bpu                     : std_logic_vector(7 downto 0);        -- Note 1
235 
   signal pavr_s5_alu_op1                    : std_logic_vector(15 downto 0);       -- Note 1
236 
   signal pavr_s5_alu_op2                    : std_logic_vector( 7 downto 0);       -- Note 1
237 
   signal pavr_s5_alu_flagsin                : std_logic_vector(5 downto 0);        -- Note 1
238 
   signal pavr_s5_alu_flagsout               : std_logic_vector(5 downto 0);        -- Note 1
239 
   signal pavr_s5_alu_out                    : std_logic_vector(15 downto 0);       -- Note 1
240 
 
241 
   -- DACU setup-related
242 
   signal next_pavr_s4_dacu_q       : std_logic_vector(7 downto 0);
243 
   signal pavr_s4_iof_dacu_q        : std_logic_vector(7 downto 0);                       -- Note 1
244 
   signal pavr_s4_dm_dacu_q         : std_logic_vector(7 downto 0);                       -- Note 1
245 
   signal pavr_s5_dacudo_sel        : std_logic_vector(1 downto 0);                       -- Note 1
246 
   signal pavr_dacu_do              : std_logic_vector(7 downto 0);                       -- Note 1
247 
   signal pavr_s5_dacust_rf_addr    : std_logic_vector(4 downto 0);                       -- Note 1
248 
   signal pavr_s5_dacu_iof_addr     : std_logic_vector(5 downto 0);                       -- Note 1
249 
   signal pavr_s5_dacu_dm_addr      : std_logic_vector(23 downto 0);                      -- Note 1
250 
   signal pavr_s5_dacu_iof_opcode   : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);   -- Note 1
251 
 
252 
   -- DACU read-related
253 
   signal next_pavr_s4_s5_x_dacurd_rq        : std_logic;
254 
   signal next_pavr_s4_s5_y_dacurd_rq        : std_logic;
255 
   signal next_pavr_s4_s5_z_dacurd_rq        : std_logic;
256 
   signal next_pavr_s4_s5_sp_dacurd_rq       : std_logic;
257 
   signal next_pavr_s4_s5_k16_dacurd_rq      : std_logic;
258 
   signal next_pavr_s4_s5s51s52_pc_dacurd_rq : std_logic;
259 
 
260 
   -- DACU write-related
261 
   signal next_pavr_s4_s5_sp_dacuwr_rq       : std_logic;
262 
   signal next_pavr_s4_s5_k16_dacuwr_rq      : std_logic;
263 
   signal next_pavr_s4_s5_x_dacuwr_rq        : std_logic;
264 
   signal next_pavr_s4_s5_y_dacuwr_rq        : std_logic;
265 
   signal next_pavr_s4_s5_z_dacuwr_rq        : std_logic;
266 
   signal next_pavr_s4_s5s51s52_pc_dacuwr_rq : std_logic;
267 
 
268 
   -- DM-related
269 
   signal pavr_s5_dacu_dmrd_rq   : std_logic;                     -- Note 1
270 
   signal pavr_s5_dacu_dmwr_rq   : std_logic;                     -- Note 1
271 
 
272 
   signal pavr_s5_dacu_dmwr_di  : std_logic_vector(7 downto 0);   -- Note 1
273 
 
274 
   -- PM access-related
275 
   signal next_pavr_s4_s5_lpm_pm_rq    : std_logic;
276 
   signal next_pavr_s4_s5_elpm_pm_rq   : std_logic;
277 
   signal next_pavr_s4_z_pm_rq         : std_logic;
278 
   signal next_pavr_s4_zeind_pm_rq     : std_logic;
279 
   signal next_pavr_s4_k22abs_pm_rq    : std_logic;
280 
   signal next_pavr_s4_k12rel_pm_rq    : std_logic;
281 
   signal next_pavr_s4_k22int_pm_rq    : std_logic;
282 
   signal next_pavr_s4_s54_ret_pm_rq   : std_logic;
283 
   signal pavr_s6_branch_pm_rq         : std_logic;      -- Note 1
284 
   signal pavr_s6_skip_pm_rq           : std_logic;      -- Note 1
285 
   signal pavr_s61_skip_pm_rq          : std_logic;      -- Note 1
286 
 
287 
   signal next_pavr_s4_k6                 : std_logic_vector(5  downto 0);
288 
   signal next_pavr_s4_k12                : std_logic_vector(11 downto 0);
289 
   signal next_pavr_s4_k22int             : std_logic_vector(21 downto 0);
290 
   signal next_pavr_s4_s51s52s53_retpc_ld : std_logic;
291 
   signal next_pavr_s4_pcinc              : std_logic;
292 
 
293 
   -- PC handling-related
294 
   signal next_pavr_s1_pc                 : std_logic_vector(21 downto 0);    -- Note 1
295 
   signal next_pavr_s2_pc                 : std_logic_vector(21 downto 0);    -- Note 1
296 
   signal next_pavr_s3_pc                 : std_logic_vector(21 downto 0);    -- Note 1
297 
   signal pavr_pm_addr_int                : std_logic_vector(21 downto 0);    -- Note 1
298 
   signal next_pavr_s2_pmdo_valid         : std_logic;                        -- Note 1
299 
   signal next_pavr_s3_instr              : std_logic_vector(15 downto 0);    -- Note 1
300 
   signal pavr_grant_control_flow_access  : std_logic;                        -- Note 1
301 
 
302 
   -- SFU requests-related
303 
   signal pavr_s3_stall_rq                : std_logic;   -- *** Note 1
304 
   signal next_pavr_s4_stall_rq           : std_logic;
305 
   signal next_pavr_s4_s5_stall_rq        : std_logic;
306 
   signal next_pavr_s4_s6_stall_rq        : std_logic;
307 
   signal pavr_s3_flush_s2_rq             : std_logic;
308 
   signal next_pavr_s4_flush_s2_rq        : std_logic;
309 
   signal next_pavr_s4_ret_flush_s2_rq    : std_logic;
310 
   signal next_pavr_s6_skip_rq            : std_logic;   -- Note 1
311 
   signal next_pavr_s61_skip_rq           : std_logic;   -- Note 1
312 
   signal next_pavr_s6_branch_rq          : std_logic;   -- Note 1
313 
   signal next_pavr_s4_nop_rq             : std_logic;
314 
 
315 
   signal next_pavr_s4_s5_skip_cond_sel         : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0);
316 
   signal next_pavr_s4_s6_skip_cond_sel         : std_logic;
317 
   signal next_pavr_s4_s5_skip_en               : std_logic;
318 
   signal next_pavr_s4_s6_skip_en               : std_logic;
319 
   signal next_pavr_s4_s5_skip_bitrf_sel        : std_logic_vector(2 downto 0);
320 
   signal next_pavr_s4_s6_skip_bitiof_sel       : std_logic_vector(2 downto 0);
321 
   signal next_pavr_s4_s5_k7_branch_offset      : std_logic_vector(6 downto 0);
322 
   signal next_pavr_s4_s5_branch_cond_sel       : std_logic;
323 
   signal next_pavr_s4_s5_branch_en             : std_logic;
324 
   signal next_pavr_s4_s5_branch_bitsreg_sel    : std_logic_vector(2 downto 0);
325 
 
326 
   -- SFU outputs
327 
   signal pavr_stall_s1:      std_logic;     -- Note 1
328 
   signal pavr_stall_s2:      std_logic;     -- Note 1
329 
   signal pavr_stall_s3:      std_logic;     -- Note 1
330 
   signal pavr_stall_s4:      std_logic;     -- Note 1
331 
   signal pavr_stall_s5:      std_logic;     -- Note 1
332 
   signal pavr_stall_s6:      std_logic;     -- Note 1
333 
   signal pavr_flush_s1:      std_logic;     -- Note 1
334 
   signal pavr_flush_s2:      std_logic;     -- Note 1
335 
   signal pavr_flush_s3:      std_logic;     -- Note 1
336 
   signal pavr_flush_s4:      std_logic;     -- Note 1
337 
   signal pavr_flush_s5:      std_logic;     -- Note 1
338 
   signal pavr_flush_s6:      std_logic;     -- Note 1
339 
   signal pavr_stall_bpu:     std_logic;     -- Note 1
340 
   signal pavr_s61_hwrq_en:   std_logic;     -- Note 1   These signals signalize whether or not hardware resource requests can safely be acknowledged.
341 
   signal pavr_s6_hwrq_en:    std_logic;     -- Note 1
342 
   signal pavr_s5_hwrq_en:    std_logic;     -- Note 1
343 
   signal pavr_s4_hwrq_en:    std_logic;     -- Note 1
344 
   signal pavr_s3_hwrq_en:    std_logic;     -- Note 1
345 
   signal pavr_s2_hwrq_en:    std_logic;     -- Note 1
346 
   signal pavr_s1_hwrq_en:    std_logic;     -- Note 1
347 
 
348 
   -- Others
349 
   signal next_pavr_s4_instr32bits  : std_logic;
350 
   signal next_pavr_s4_disable_int  : std_logic;
351 
   signal pavr_disable_int          : std_logic;
352 
   signal pavr_int_rq               : std_logic;                        -- Note 1
353 
   signal pavr_int_vec              : std_logic_vector(21 downto 0);    -- Note 1
354 
 
355 
 
356 
 
357 
   -- Wires for RF, IOF and DM connectivity
358 
 
359 
   -- RF read port 1
360 
   signal pavr_rf_rd1_addr : std_logic_vector(4 downto 0);
361 
   signal pavr_rf_rd1_rd   : std_logic;
362 
   signal pavr_rf_rd1_do   : std_logic_vector(7 downto 0);
363 
 
364 
   -- RF read port 2
365 
   signal pavr_rf_rd2_addr : std_logic_vector(4 downto 0);
366 
   signal pavr_rf_rd2_rd   : std_logic;
367 
   signal pavr_rf_rd2_do   : std_logic_vector(7 downto 0);
368 
 
369 
   -- RF write port
370 
   signal pavr_rf_wr_addr  : std_logic_vector(4 downto 0);
371 
   signal pavr_rf_wr_wr    : std_logic;
372 
   signal pavr_rf_wr_di    : std_logic_vector(7 downto 0);
373 
 
374 
   -- X pointer port
375 
   signal pavr_rf_x     : std_logic_vector(15 downto 0);
376 
   signal pavr_rf_x_wr  : std_logic;
377 
   signal pavr_rf_x_di  : std_logic_vector(15 downto 0);
378 
 
379 
   -- Y pointer port
380 
   signal pavr_rf_y     : std_logic_vector(15 downto 0);
381 
   signal pavr_rf_y_wr  : std_logic;
382 
   signal pavr_rf_y_di  : std_logic_vector(15 downto 0);
383 
 
384 
   -- Z pointer port
385 
   signal pavr_rf_z     : std_logic_vector(15 downto 0);
386 
   signal pavr_rf_z_wr  : std_logic;
387 
   signal pavr_rf_z_di  : std_logic_vector(15 downto 0);
388 
 
389 
   -- IOF general read and write port
390 
   signal pavr_iof_opcode  : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
391 
   signal pavr_iof_addr    : std_logic_vector(5 downto 0);
392 
   signal pavr_iof_di      : std_logic_vector(7 downto 0);
393 
   signal pavr_iof_do      : std_logic_vector(7 downto 0);
394 
   signal pavr_iof_bitaddr : std_logic_vector(2 downto 0);
395 
   signal pavr_iof_bitout  : std_logic;
396 
 
397 
   -- SREG port
398 
   signal pavr_iof_sreg    : std_logic_vector(7 downto 0);
399 
   signal pavr_iof_sreg_wr : std_logic;
400 
   signal pavr_iof_sreg_di : std_logic_vector(7 downto 0);
401 
 
402 
   -- SP port
403 
   signal pavr_iof_spl     : std_logic_vector(7 downto 0);
404 
   signal pavr_iof_spl_wr  : std_logic;
405 
   signal pavr_iof_spl_di  : std_logic_vector(7 downto 0);
406 
 
407 
   signal pavr_iof_sph     : std_logic_vector(7 downto 0);
408 
   signal pavr_iof_sph_wr  : std_logic;
409 
   signal pavr_iof_sph_di  : std_logic_vector(7 downto 0);
410 
 
411 
   -- RAMPX port
412 
   signal pavr_iof_rampx      : std_logic_vector(7 downto 0);
413 
   signal pavr_iof_rampx_wr   : std_logic;
414 
   signal pavr_iof_rampx_di   : std_logic_vector(7 downto 0);
415 
 
416 
   -- RAMPY port
417 
   signal pavr_iof_rampy      : std_logic_vector(7 downto 0);
418 
   signal pavr_iof_rampy_wr   : std_logic;
419 
   signal pavr_iof_rampy_di   : std_logic_vector(7 downto 0);
420 
 
421 
   -- RAMPZ port
422 
   signal pavr_iof_rampz      : std_logic_vector(7 downto 0);
423 
   signal pavr_iof_rampz_wr   : std_logic;
424 
   signal pavr_iof_rampz_di   : std_logic_vector(7 downto 0);
425 
 
426 
   -- RAMPD port
427 
   signal pavr_iof_rampd      : std_logic_vector(7 downto 0);
428 
   signal pavr_iof_rampd_wr   : std_logic;
429 
   signal pavr_iof_rampd_di   : std_logic_vector(7 downto 0);
430 
 
431 
   -- EIND port
432 
   signal pavr_iof_eind       : std_logic_vector(7 downto 0);
433 
   signal pavr_iof_eind_wr    : std_logic;
434 
   signal pavr_iof_eind_di    : std_logic_vector(7 downto 0);
435 
 
436 
   -- DM port
437 
   signal pavr_dm_do    : std_logic_vector(7 downto 0);
438 
   signal pavr_dm_wr    : std_logic;
439 
   signal pavr_dm_addr  : std_logic_vector(pavr_dm_addr_w - 1 downto 0);
440 
   signal pavr_dm_di    : std_logic_vector(7 downto 0);
441 
 
442 
   -- Registers ---------------------------------------------------------------
443 
 
444 
   -- RF read port 1-related
445 
   -- No registers related to requests to RF read port 1.
446 
 
447 
   signal pavr_s5_op1 : std_logic_vector(7 downto 0);
448 
 
449 
   -- RF read port 2-related
450 
   -- No registers related to requests to RF read port 2.
451 
 
452 
   signal pavr_s5_op2 : std_logic_vector(7 downto 0);
453 
 
454 
   -- RF write port-related
455 
   signal pavr_s4_s6_aluoutlo8_rfwr_rq    : std_logic;
456 
   signal pavr_s5_s6_aluoutlo8_rfwr_rq    : std_logic;
457 
   signal    pavr_s6_aluoutlo8_rfwr_rq    : std_logic;
458 
   signal pavr_s4_s61_aluouthi8_rfwr_rq   : std_logic;
459 
   signal pavr_s5_s61_aluouthi8_rfwr_rq   : std_logic;
460 
   signal pavr_s6_s61_aluouthi8_rfwr_rq   : std_logic;
461 
   signal    pavr_s61_aluouthi8_rfwr_rq   : std_logic;
462 
   signal pavr_s4_s6_iof_rfwr_rq          : std_logic;
463 
   signal pavr_s5_s6_iof_rfwr_rq          : std_logic;
464 
   signal    pavr_s6_iof_rfwr_rq          : std_logic;
465 
   signal pavr_s4_s6_dacu_rfwr_rq         : std_logic;
466 
   signal pavr_s5_s6_dacu_rfwr_rq         : std_logic;
467 
   signal    pavr_s6_dacu_rfwr_rq         : std_logic;
468 
   signal pavr_s4_s6_pm_rfwr_rq           : std_logic;
469 
   signal pavr_s5_s6_pm_rfwr_rq           : std_logic;
470 
   signal    pavr_s6_pm_rfwr_rq           : std_logic;
471 
 
472 
   signal pavr_s4_s6_rfwr_addr1           : std_logic_vector(4 downto 0);
473 
   signal pavr_s5_s6_rfwr_addr1           : std_logic_vector(4 downto 0);
474 
   signal    pavr_s6_rfwr_addr1           : std_logic_vector(4 downto 0);
475 
   signal pavr_s4_s61_rfwr_addr2          : std_logic_vector(4 downto 0);
476 
   signal pavr_s5_s61_rfwr_addr2          : std_logic_vector(4 downto 0);
477 
   signal pavr_s6_s61_rfwr_addr2          : std_logic_vector(4 downto 0);
478 
   signal    pavr_s61_rfwr_addr2          : std_logic_vector(4 downto 0);
479 
 
480 
   -- Pointer registers-related
481 
   signal pavr_s4_s5_ldstincrampx_xwr_rq  : std_logic;
482 
   signal    pavr_s5_ldstincrampx_xwr_rq  : std_logic;
483 
   signal pavr_s4_s5_ldstdecrampx_xwr_rq  : std_logic;
484 
   signal    pavr_s5_ldstdecrampx_xwr_rq  : std_logic;
485 
 
486 
   signal pavr_s4_s5_ldstincrampy_ywr_rq  : std_logic;
487 
   signal    pavr_s5_ldstincrampy_ywr_rq  : std_logic;
488 
   signal pavr_s4_s5_ldstdecrampy_ywr_rq  : std_logic;
489 
   signal    pavr_s5_ldstdecrampy_ywr_rq  : std_logic;
490 
 
491 
   signal pavr_s4_s5_ldstincrampz_zwr_rq  : std_logic;
492 
   signal    pavr_s5_ldstincrampz_zwr_rq  : std_logic;
493 
   signal pavr_s4_s5_ldstdecrampz_zwr_rq  : std_logic;
494 
   signal    pavr_s5_ldstdecrampz_zwr_rq  : std_logic;
495 
   signal pavr_s4_s5_elpmincrampz_zwr_rq  : std_logic;
496 
   signal    pavr_s5_elpmincrampz_zwr_rq  : std_logic;
497 
   signal pavr_s4_s5_lpminc_zwr_rq        : std_logic;
498 
   signal    pavr_s5_lpminc_zwr_rq        : std_logic;
499 
 
500 
   -- BPU write, BPR0-related
501 
   signal pavr_s4_s5_alu_bpr0wr_rq     : std_logic;
502 
   signal    pavr_s5_alu_bpr0wr_rq     : std_logic;
503 
   signal pavr_s4_s6_iof_bpr0wr_rq     : std_logic;
504 
   signal pavr_s5_s6_iof_bpr0wr_rq     : std_logic;
505 
   signal    pavr_s6_iof_bpr0wr_rq     : std_logic;
506 
   signal pavr_s4_s6_daculd_bpr0wr_rq  : std_logic;
507 
   signal pavr_s5_s6_daculd_bpr0wr_rq  : std_logic;
508 
   signal    pavr_s6_daculd_bpr0wr_rq  : std_logic;
509 
   signal pavr_s4_s6_pmdo_bpr0wr_rq    : std_logic;
510 
   signal pavr_s5_s6_pmdo_bpr0wr_rq    : std_logic;
511 
   signal    pavr_s6_pmdo_bpr0wr_rq    : std_logic;
512 
 
513 
   signal pavr_bpr00        : std_logic_vector(7 downto 0);           -- Bypass chain 0 and associated registers. Note 1
514 
   signal pavr_bpr00_addr   : std_logic_vector(4 downto 0);
515 
   signal pavr_bpr00_active : std_logic;
516 
   signal pavr_bpr01        : std_logic_vector(7 downto 0);
517 
   signal pavr_bpr01_addr   : std_logic_vector(4 downto 0);
518 
   signal pavr_bpr01_active : std_logic;
519 
   signal pavr_bpr02        : std_logic_vector(7 downto 0);
520 
   signal pavr_bpr02_addr   : std_logic_vector(4 downto 0);
521 
   signal pavr_bpr02_active : std_logic;
522 
   signal pavr_bpr03        : std_logic_vector(7 downto 0);
523 
   signal pavr_bpr03_addr   : std_logic_vector(4 downto 0);
524 
   signal pavr_bpr03_active : std_logic;
525 
 
526 
   -- BPU write, BPR1-related
527 
   signal pavr_s4_s5_dacux_bpr12wr_rq  : std_logic;
528 
   signal    pavr_s5_dacux_bpr12wr_rq  : std_logic;
529 
   signal pavr_s4_s5_dacuy_bpr12wr_rq  : std_logic;
530 
   signal    pavr_s5_dacuy_bpr12wr_rq  : std_logic;
531 
   signal pavr_s4_s5_dacuz_bpr12wr_rq  : std_logic;
532 
   signal    pavr_s5_dacuz_bpr12wr_rq  : std_logic;
533 
   signal pavr_s4_s5_alu_bpr1wr_rq     : std_logic;
534 
   signal    pavr_s5_alu_bpr1wr_rq     : std_logic;
535 
 
536 
   signal pavr_bpr10          : std_logic_vector(7 downto 0);           -- Bypass chain 1 and associated registers. Note 1
537 
   signal pavr_bpr10_addr     : std_logic_vector(4 downto 0);
538 
   signal pavr_bpr10_active   : std_logic;
539 
   signal pavr_bpr11          : std_logic_vector(7 downto 0);
540 
   signal pavr_bpr11_addr     : std_logic_vector(4 downto 0);
541 
   signal pavr_bpr11_active   : std_logic;
542 
   signal pavr_bpr12          : std_logic_vector(7 downto 0);
543 
   signal pavr_bpr12_addr     : std_logic_vector(4 downto 0);
544 
   signal pavr_bpr12_active   : std_logic;
545 
   signal pavr_bpr13          : std_logic_vector(7 downto 0);
546 
   signal pavr_bpr13_addr     : std_logic_vector(4 downto 0);
547 
   signal pavr_bpr13_active   : std_logic;
548 
 
549 
   -- BPU write, BPR2-related
550 
 
551 
   signal pavr_bpr20          : std_logic_vector(7 downto 0);           -- Bypass chain 2 and associated registers. Note 1
552 
   signal pavr_bpr20_addr     : std_logic_vector(4 downto 0);
553 
   signal pavr_bpr20_active   : std_logic;
554 
   signal pavr_bpr21          : std_logic_vector(7 downto 0);
555 
   signal pavr_bpr21_addr     : std_logic_vector(4 downto 0);
556 
   signal pavr_bpr21_active   : std_logic;
557 
   signal pavr_bpr22          : std_logic_vector(7 downto 0);
558 
   signal pavr_bpr22_addr     : std_logic_vector(4 downto 0);
559 
   signal pavr_bpr22_active   : std_logic;
560 
   signal pavr_bpr23          : std_logic_vector(7 downto 0);
561 
   signal pavr_bpr23_addr     : std_logic_vector(4 downto 0);
562 
   signal pavr_bpr23_active   : std_logic;
563 
 
564 
   -- IOF port-related
565 
   signal pavr_s4_s5_iof_rq          : std_logic;
566 
   signal    pavr_s5_iof_rq          : std_logic;
567 
   signal pavr_s4_s6_iof_rq          : std_logic;
568 
   signal pavr_s5_s6_iof_rq          : std_logic;
569 
   signal    pavr_s6_iof_rq          : std_logic;
570 
 
571 
   signal pavr_s4_s5_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
572 
   signal    pavr_s5_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
573 
   signal pavr_s4_s6_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
574 
   signal pavr_s5_s6_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
575 
   signal    pavr_s6_iof_opcode      : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
576 
   signal pavr_s4_s5s6_iof_addr      : std_logic_vector(5 downto 0);
577 
   signal      pavr_s5_iof_addr      : std_logic_vector(5 downto 0);
578 
   signal      pavr_s6_iof_addr      : std_logic_vector(5 downto 0);
579 
   signal pavr_s4_s5s6_iof_bitaddr   : std_logic_vector(2 downto 0);
580 
   signal      pavr_s5_iof_bitaddr   : std_logic_vector(2 downto 0);
581 
   signal      pavr_s6_iof_bitaddr   : std_logic_vector(2 downto 0);
582 
 
583 
   -- SREG-related
584 
   signal pavr_s4_s5_alu_sregwr_rq        : std_logic;
585 
   signal    pavr_s5_alu_sregwr_rq        : std_logic;
586 
   signal pavr_s4_s5_clriflag_sregwr_rq   : std_logic;
587 
   signal    pavr_s5_clriflag_sregwr_rq   : std_logic;
588 
   signal pavr_s4_s5_setiflag_sregwr_rq   : std_logic;
589 
   signal    pavr_s5_setiflag_sregwr_rq   : std_logic;
590 
 
591 
   -- SP-related
592 
   signal pavr_s4_s5_inc_spwr_rq             : std_logic;
593 
   signal    pavr_s5_inc_spwr_rq             : std_logic;
594 
   signal pavr_s4_s5_dec_spwr_rq             : std_logic;
595 
   signal    pavr_s5_dec_spwr_rq             : std_logic;
596 
   signal pavr_s4_s5s51s52_calldec_spwr_rq   : std_logic;
597 
   signal    pavr_s5_calldec_spwr_rq         : std_logic;
598 
   signal    pavr_s51_calldec_spwr_rq        : std_logic;
599 
   signal    pavr_s52_calldec_spwr_rq        : std_logic;
600 
   signal pavr_s4_s5s51_retinc_spwr_rq       : std_logic;
601 
   signal    pavr_s5_retinc2_spwr_rq         : std_logic;
602 
   signal    pavr_s51_retinc_spwr_rq         : std_logic;
603 
 
604 
   -- ALU-related
605 
   signal pavr_s4_s5_alu_opcode        : std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
606 
   signal    pavr_s5_alu_opcode        : std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
607 
   signal pavr_s4_s5_alu_op1_hi8_sel   : std_logic;
608 
   signal    pavr_s5_alu_op1_hi8_sel   : std_logic;
609 
   signal pavr_s4_s5_alu_op2_sel       : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0);
610 
   signal    pavr_s5_alu_op2_sel       : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0);
611 
   signal pavr_s4_s5_op1_addr          : std_logic_vector(4 downto 0);
612 
   signal    pavr_s5_op1_addr          : std_logic_vector(4 downto 0);
613 
   signal pavr_s4_s5_op2_addr          : std_logic_vector(4 downto 0);
614 
   signal    pavr_s5_op2_addr          : std_logic_vector(4 downto 0);
615 
   signal pavr_s4_s5_k8                : std_logic_vector(7 downto 0);
616 
   signal    pavr_s5_k8                : std_logic_vector(7 downto 0);
617 
   signal pavr_s6_alu_out              : std_logic_vector(15 downto 0);
618 
   signal pavr_s61_alu_out_hi8         : std_logic_vector( 7 downto 0);
619 
 
620 
   -- DACU setup-related
621 
   signal pavr_s4_dacu_q      : std_logic_vector(7 downto 0);
622 
   signal pavr_s5_rf_dacu_q   : std_logic_vector(7 downto 0);
623 
   signal pavr_s5_iof_dacu_q  : std_logic_vector(7 downto 0);
624 
   signal pavr_s5_dm_dacu_q   : std_logic_vector(7 downto 0);
625 
   signal pavr_s6_dacudo_sel  : std_logic_vector(1 downto 0);
626 
   signal pavr_s5_k16         : std_logic_vector(15 downto 0); -- *** Attention: no `pavr_s4_s5_k16'. `pavr_s5_k16' is fed directly from stage s3.
627 
 
628 
   -- DACU read-related
629 
   signal pavr_s4_s5_x_dacurd_rq          : std_logic;
630 
   signal    pavr_s5_x_dacurd_rq          : std_logic;
631 
   signal pavr_s4_s5_y_dacurd_rq          : std_logic;
632 
   signal    pavr_s5_y_dacurd_rq          : std_logic;
633 
   signal pavr_s4_s5_z_dacurd_rq          : std_logic;
634 
   signal    pavr_s5_z_dacurd_rq          : std_logic;
635 
   signal pavr_s4_s5_sp_dacurd_rq         : std_logic;
636 
   signal    pavr_s5_sp_dacurd_rq         : std_logic;
637 
   signal pavr_s4_s5_k16_dacurd_rq        : std_logic;
638 
   signal    pavr_s5_k16_dacurd_rq        : std_logic;
639 
   signal pavr_s4_s5s51s52_pc_dacurd_rq   : std_logic;
640 
   signal    pavr_s5_pchi8_dacurd_rq      : std_logic;
641 
   signal    pavr_s51_pcmid8_dacurd_rq    : std_logic;
642 
   signal    pavr_s52_pclo8_dacurd_rq     : std_logic;
643 
 
644 
   -- DACU write-related
645 
   signal pavr_s4_s5_sp_dacuwr_rq         : std_logic;
646 
   signal    pavr_s5_sp_dacuwr_rq         : std_logic;
647 
   signal pavr_s4_s5_k16_dacuwr_rq        : std_logic;
648 
   signal    pavr_s5_k16_dacuwr_rq        : std_logic;
649 
   signal pavr_s4_s5_x_dacuwr_rq          : std_logic;
650 
   signal    pavr_s5_x_dacuwr_rq          : std_logic;
651 
   signal pavr_s4_s5_y_dacuwr_rq          : std_logic;
652 
   signal    pavr_s5_y_dacuwr_rq          : std_logic;
653 
   signal pavr_s4_s5_z_dacuwr_rq          : std_logic;
654 
   signal    pavr_s5_z_dacuwr_rq          : std_logic;
655 
   signal pavr_s4_s5s51s52_pc_dacuwr_rq   : std_logic;
656 
   signal    pavr_s5_pclo8_dacuwr_rq      : std_logic;
657 
   signal    pavr_s51_pcmid8_dacuwr_rq    : std_logic;
658 
   signal    pavr_s52_pchi8_dacuwr_rq     : std_logic;
659 
 
660 
   -- DM-related
661 
 
662 
   -- PM access-related
663 
   signal pavr_s4_s5_lpm_pm_rq   : std_logic;
664 
   signal    pavr_s5_lpm_pm_rq   : std_logic;
665 
   signal pavr_s4_s5_elpm_pm_rq  : std_logic;
666 
   signal    pavr_s5_elpm_pm_rq  : std_logic;
667 
   signal pavr_s4_z_pm_rq        : std_logic;
668 
   signal pavr_s4_zeind_pm_rq    : std_logic;
669 
   signal pavr_s4_k22abs_pm_rq   : std_logic;
670 
   signal pavr_s4_k12rel_pm_rq   : std_logic;
671 
   signal pavr_s4_k22int_pm_rq   : std_logic;
672 
   signal pavr_s4_s54_ret_pm_rq  : std_logic;
673 
   signal pavr_s5_s54_ret_pm_rq  : std_logic;
674 
   signal pavr_s51_s54_ret_pm_rq : std_logic;
675 
   signal pavr_s52_s54_ret_pm_rq : std_logic;
676 
   signal pavr_s53_s54_ret_pm_rq : std_logic;
677 
   signal     pavr_s54_ret_pm_rq : std_logic;
678 
 
679 
   signal pavr_s4_k6                   : std_logic_vector(5 downto 0);
680 
   signal pavr_s4_k12                  : std_logic_vector(11 downto 0);
681 
   signal pavr_s4_k22int               : std_logic_vector(21 downto 0);
682 
   signal pavr_s2_pc                   : std_logic_vector(21 downto 0);
683 
   signal pavr_s3_pc                   : std_logic_vector(21 downto 0);
684 
   signal pavr_s4_pc                   : std_logic_vector(21 downto 0);
685 
   signal pavr_s5_pc                   : std_logic_vector(21 downto 0);
686 
   signal pavr_s51_pc                  : std_logic_vector(21 downto 0);
687 
   signal pavr_s52_pc                  : std_logic_vector(21 downto 0);
688 
   signal pavr_s4_pcinc                : std_logic;
689 
   signal pavr_s4_s51s52s53_retpc_ld   : std_logic;
690 
   signal pavr_s5_s51s52s53_retpc_ld   : std_logic;
691 
   signal    pavr_s51_retpchi8_ld      : std_logic;
692 
   signal    pavr_s52_retpcmid8_ld     : std_logic;
693 
   signal    pavr_s53_retpclo8_ld      : std_logic;
694 
   signal pavr_s52_retpchi8            : std_logic_vector(7 downto 0);
695 
   signal pavr_s53_retpcmid8           : std_logic_vector(7 downto 0);
696 
   signal pavr_s54_retpclo8            : std_logic_vector(7 downto 0);
697 
   signal pavr_s1_pc                   : std_logic_vector(21 downto 0);
698 
   signal pavr_s2_pmdo_valid           : std_logic;
699 
 
700 
   signal pavr_s6_zlsb                 : std_logic;      -- Needed by LPM instructions to select low/high byte read.
701 
 
702 
   -- SFU requests-related
703 
   signal    pavr_s4_stall_rq        : std_logic;
704 
   signal pavr_s4_s5_stall_rq        : std_logic;
705 
   signal    pavr_s5_stall_rq        : std_logic;
706 
   signal pavr_s4_s6_stall_rq        : std_logic;
707 
   signal pavr_s5_s6_stall_rq        : std_logic;
708 
   signal    pavr_s6_stall_rq        : std_logic;
709 
   signal pavr_s4_flush_s2_rq        : std_logic;
710 
   signal pavr_s4_ret_flush_s2_rq    : std_logic;
711 
   signal pavr_s5_ret_flush_s2_rq    : std_logic;
712 
   signal pavr_s51_ret_flush_s2_rq   : std_logic;
713 
   signal pavr_s52_ret_flush_s2_rq   : std_logic;
714 
   signal pavr_s53_ret_flush_s2_rq   : std_logic;
715 
   signal pavr_s54_ret_flush_s2_rq   : std_logic;
716 
   signal pavr_s55_ret_flush_s2_rq   : std_logic;
717 
   signal pavr_s6_skip_rq            : std_logic;
718 
   signal pavr_s61_skip_rq           : std_logic;
719 
   signal pavr_s6_branch_rq          : std_logic;
720 
   signal pavr_s4_nop_rq             : std_logic;
721 
 
722 
   signal pavr_s4_s5_skip_cond_sel     : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0);
723 
   signal    pavr_s5_skip_cond_sel     : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0);
724 
   signal pavr_s4_s6_skip_cond_sel     : std_logic;
725 
   signal pavr_s5_s6_skip_cond_sel     : std_logic;
726 
   signal    pavr_s6_skip_cond_sel     : std_logic;
727 
   signal pavr_s4_s5_skip_en           : std_logic;
728 
   signal    pavr_s5_skip_en           : std_logic;
729 
   signal pavr_s4_s6_skip_en           : std_logic;
730 
   signal pavr_s5_s6_skip_en           : std_logic;
731 
   signal    pavr_s6_skip_en           : std_logic;
732 
   signal pavr_s4_s5_skip_bitrf_sel    : std_logic_vector(2 downto 0);
733 
   signal    pavr_s5_skip_bitrf_sel    : std_logic_vector(2 downto 0);
734 
   signal pavr_s4_s6_skip_bitiof_sel   : std_logic_vector(2 downto 0);
735 
   signal pavr_s5_s6_skip_bitiof_sel   : std_logic_vector(2 downto 0);
736 
   signal    pavr_s6_skip_bitiof_sel   : std_logic_vector(2 downto 0);
737 
 
738 
   signal pavr_s4_s5_k7_branch_offset     : std_logic_vector(6 downto 0);
739 
   signal    pavr_s5_k7_branch_offset     : std_logic_vector(6 downto 0);
740 
   signal pavr_s6_branch_pc               : std_logic_vector(21 downto 0);
741 
   signal pavr_s4_s5_branch_cond_sel      : std_logic;
742 
   signal    pavr_s5_branch_cond_sel      : std_logic;
743 
   signal pavr_s4_s5_branch_en            : std_logic;
744 
   signal    pavr_s5_branch_en            : std_logic;
745 
   signal pavr_s4_s5_branch_bitsreg_sel   : std_logic_vector(2 downto 0);
746 
   signal    pavr_s5_branch_bitsreg_sel   : std_logic_vector(2 downto 0);
747 
 
748 
   -- Others
749 
   signal pavr_nop_ack           : std_logic;                     -- Nop state machine's memory. The nop state machine is outside the pipeline.
750 
   signal pavr_s3_instr          : std_logic_vector(15 downto 0); -- Instruction register
751 
   signal pavr_s4_instr32bits    : std_logic;                     -- Signalizes that this instruction is 32 bits wide. Next word (16 bits) will be ignored by the instruction decoder (nop). It's a constant that will be extracted directly by s5.
752 
   signal pavr_s4_disable_int    : std_logic;
753 
   signal pavr_s5_disable_int    : std_logic;
754 
   signal pavr_s51_disable_int   : std_logic;
755 
   signal pavr_s52_disable_int   : std_logic;
756 
 
757 
   -- Shadow-related
758 
   -- Shadow registers hold temporary values already read from memories but not
759 
   --    yet used because of a stall. See comments at Shadow Manager process.
760 
   -- RF-related shadow registers
761 
   signal pavr_rf_rd1_do_shadow     : std_logic_vector(7 downto 0);
762 
   signal pavr_rf_rd2_do_shadow     : std_logic_vector(7 downto 0);
763 
   -- IOF-related shadow registers
764 
   signal pavr_iof_do_shadow        : std_logic_vector(7 downto 0);
765 
   -- DM-related shadow registers
766 
   signal pavr_dm_do_shadow         : std_logic_vector(7 downto 0);
767 
   -- DACU-related shadow registers
768 
   signal pavr_dacu_do_shadow       : std_logic_vector(7 downto 0);
769 
   -- PM-related shadow registers
770 
   signal pavr_pm_do_shadow         : std_logic_vector(15 downto 0);
771 
   signal pavr_s2_pmdo_valid_shadow : std_logic;
772 
 
773 
   signal pavr_rf_do_shadow_active                    : std_logic;
774 
   signal pavr_iof_do_shadow_active                   : std_logic;
775 
   signal pavr_dm_do_shadow_active                    : std_logic;
776 
   signal pavr_dacu_do_shadow_active                  : std_logic;
777 
   signal pavr_pm_do_shadow_active                    : std_logic;
778 
 
779 
 
780 
 
781 
 
782 
 
783 
 
784 
   -- Declare components ------------------------------------------------------
785 
 
786 
   -- Declare the Register File.
787 
   component pavr_rf
788 
   port(
789 
      pavr_rf_clk:     in std_logic;
790 
      pavr_rf_res:     in std_logic;
791 
      pavr_rf_syncres: in std_logic;
792 
 
793 
      -- Read port #1
794 
      pavr_rf_rd1_addr: in  std_logic_vector(4 downto 0);
795 
      pavr_rf_rd1_rd:   in  std_logic;
796 
      pavr_rf_rd1_do:   out std_logic_vector(7 downto 0);
797 
 
798 
      -- Read port #2
799 
      pavr_rf_rd2_addr: in  std_logic_vector(4 downto 0);
800 
      pavr_rf_rd2_rd:   in  std_logic;
801 
      pavr_rf_rd2_do:   out std_logic_vector(7 downto 0);
802 
 
803 
      -- Write port
804 
      pavr_rf_wr_addr: in std_logic_vector(4 downto 0);
805 
      pavr_rf_wr_wr:   in std_logic;
806 
      pavr_rf_wr_di:   in std_logic_vector(7 downto 0);
807 
 
808 
      -- Pointer registers
809 
      pavr_rf_x:    out std_logic_vector(15 downto 0);
810 
      pavr_rf_x_wr: in  std_logic;
811 
      pavr_rf_x_di: in  std_logic_vector(15 downto 0);
812 
 
813 
      pavr_rf_y:    out std_logic_vector(15 downto 0);
814 
      pavr_rf_y_wr: in  std_logic;
815 
      pavr_rf_y_di: in  std_logic_vector(15 downto 0);
816 
 
817 
      pavr_rf_z:    out std_logic_vector(15 downto 0);
818 
      pavr_rf_z_wr: in  std_logic;
819 
      pavr_rf_z_di: in  std_logic_vector(15 downto 0)
820 
   );
821 
   end component;
822 
   for all: pavr_rf use entity work.pavr_rf(pavr_rf_arch);
823 
 
824 
   -- Declare the IO File.
825 
   component pavr_iof
826 
   port(
827 
      pavr_iof_clk      : in std_logic;
828 
      pavr_iof_res      : in std_logic;
829 
      pavr_iof_syncres  : in std_logic;
830 
 
831 
      -- General IO file port
832 
      pavr_iof_opcode   : in  std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
833 
      pavr_iof_addr     : in  std_logic_vector(5 downto 0);
834 
      pavr_iof_di       : in  std_logic_vector(7 downto 0);
835 
      pavr_iof_do       : out std_logic_vector(7 downto 0);
836 
      pavr_iof_bitout   : out std_logic;
837 
      pavr_iof_bitaddr  : in  std_logic_vector(2 downto 0);
838 
 
839 
      -- AVR kernel register ports
840 
      -- Status register (SREG)
841 
      pavr_iof_sreg     : out std_logic_vector(7 downto 0);
842 
      pavr_iof_sreg_wr  : in  std_logic;
843 
      pavr_iof_sreg_di  : in  std_logic_vector(7 downto 0);
844 
 
845 
      -- Stack pointer (SP = SPH&SPL)
846 
      pavr_iof_sph      : out std_logic_vector(7 downto 0);
847 
      pavr_iof_sph_wr   : in  std_logic;
848 
      pavr_iof_sph_di   : in  std_logic_vector(7 downto 0);
849 
      pavr_iof_spl      : out std_logic_vector(7 downto 0);
850 
      pavr_iof_spl_wr   : in  std_logic;
851 
      pavr_iof_spl_di   : in  std_logic_vector(7 downto 0);
852 
 
853 
      -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
854 
      pavr_iof_rampx    : out std_logic_vector(7 downto 0);
855 
      pavr_iof_rampx_wr : in  std_logic;
856 
      pavr_iof_rampx_di : in  std_logic_vector(7 downto 0);
857 
 
858 
      pavr_iof_rampy    : out std_logic_vector(7 downto 0);
859 
      pavr_iof_rampy_wr : in  std_logic;
860 
      pavr_iof_rampy_di : in  std_logic_vector(7 downto 0);
861 
 
862 
      pavr_iof_rampz    : out std_logic_vector(7 downto 0);
863 
      pavr_iof_rampz_wr : in  std_logic;
864 
      pavr_iof_rampz_di : in  std_logic_vector(7 downto 0);
865 
 
866 
      -- Data Memory extension address register (RAMPD)
867 
      pavr_iof_rampd    : out std_logic_vector(7 downto 0);
868 
      pavr_iof_rampd_wr : in  std_logic;
869 
      pavr_iof_rampd_di : in  std_logic_vector(7 downto 0);
870 
 
871 
      -- Program Memory extension address register (EIND)
872 
      pavr_iof_eind     : out std_logic_vector(7 downto 0);
873 
      pavr_iof_eind_wr  : in  std_logic;
874 
      pavr_iof_eind_di  : in  std_logic_vector(7 downto 0);
875 
 
876 
      -- AVR non-kernel (feature) register ports
877 
      -- Port A
878 
      pavr_iof_pa : inout std_logic_vector(7 downto 0);
879 
 
880 
      -- Interrupt-related interface signals to control module (to the pipeline).
881 
      pavr_disable_int  : in  std_logic;
882 
      pavr_int_rq       : out std_logic;
883 
      pavr_int_vec      : out std_logic_vector(21 downto 0)
884 
   );
885 
   end component;
886 
   for all: pavr_iof use entity work.pavr_iof(pavr_iof_arch);
887 
 
888 
   -- Declare the Data Memory
889 
   component pavr_dm
890 
   port(
891 
      pavr_dm_clk:  in  std_logic;
892 
      pavr_dm_wr:   in  std_logic;
893 
      pavr_dm_addr: in  std_logic_vector(pavr_dm_addr_w - 1 downto 0);
894 
      pavr_dm_di:   in  std_logic_vector(7 downto 0);
895 
      pavr_dm_do:   out std_logic_vector(7 downto 0)
896 
   );
897 
   end component;
898 
   for all: pavr_dm use entity work.pavr_dm(pavr_dm_arch);
899 
 
900 
   -- Declare the ALU.
901 
   component pavr_alu
902 
   port(
903 
      pavr_alu_op1:      in  std_logic_vector(15 downto 0);
904 
      pavr_alu_op2:      in  std_logic_vector(7 downto 0);
905 
      pavr_alu_out:      out std_logic_vector(15 downto 0);
906 
      pavr_alu_opcode:   in  std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
907 
      pavr_alu_flagsin:  in  std_logic_vector(5 downto 0);
908 
      pavr_alu_flagsout: out std_logic_vector(5 downto 0)
909 
   );
910 
   end component;
911 
   for all: pavr_alu use entity work.pavr_alu(pavr_alu_arch);
912 
 
913 
 
914 
 
915 
begin
916 
 
917 
   -- Instantiate Components --------------------------------------------------
918 
 
919 
   -- Instantiate the Register File.
920 
   pavr_rf_instance1: pavr_rf
921 
   port map(
922 
      pavr_clk,
923 
      pavr_res,
924 
      pavr_syncres,
925 
 
926 
      -- Read port #1
927 
      pavr_rf_rd1_addr,
928 
      pavr_rf_rd1_rd,
929 
      pavr_rf_rd1_do,
930 
 
931 
      -- Read port #2
932 
      pavr_rf_rd2_addr,
933 
      pavr_rf_rd2_rd,
934 
      pavr_rf_rd2_do,
935 
 
936 
      -- Write port
937 
      pavr_rf_wr_addr,
938 
      pavr_rf_wr_wr,
939 
      pavr_rf_wr_di,
940 
 
941 
      -- Pointer registers
942 
      pavr_rf_x,
943 
      pavr_rf_x_wr,
944 
      pavr_rf_x_di,
945 
 
946 
      pavr_rf_y,
947 
      pavr_rf_y_wr,
948 
      pavr_rf_y_di,
949 
 
950 
      pavr_rf_z,
951 
      pavr_rf_z_wr,
952 
      pavr_rf_z_di
953 
   );
954 
 
955 
   -- Instantiate the IO File.
956 
   pavr_iof_instance1: pavr_iof
957 
   port map(
958 
      pavr_clk,
959 
      pavr_res,
960 
      pavr_syncres,
961 
 
962 
      -- General IO file port
963 
      pavr_iof_opcode,
964 
      pavr_iof_addr,
965 
      pavr_iof_di,
966 
      pavr_iof_do,
967 
      pavr_iof_bitout,
968 
      pavr_iof_bitaddr,
969 
 
970 
      -- AVR kernel register ports
971 
      -- Status register (SREG)
972 
      pavr_iof_sreg,
973 
      pavr_iof_sreg_wr,
974 
      pavr_iof_sreg_di,
975 
 
976 
      -- Stack pointer (SP = SPH&SPL)
977 
      pavr_iof_sph,
978 
      pavr_iof_sph_wr,
979 
      pavr_iof_sph_di,
980 
      pavr_iof_spl,
981 
      pavr_iof_spl_wr,
982 
      pavr_iof_spl_di,
983 
 
984 
      -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
985 
      pavr_iof_rampx,
986 
      pavr_iof_rampx_wr,
987 
      pavr_iof_rampx_di,
988 
 
989 
      pavr_iof_rampy,
990 
      pavr_iof_rampy_wr,
991 
      pavr_iof_rampy_di,
992 
 
993 
      pavr_iof_rampz,
994 
      pavr_iof_rampz_wr,
995 
      pavr_iof_rampz_di,
996 
 
997 
      -- Data Memory extension address register (RAMPD)
998 
      pavr_iof_rampd,
999 
      pavr_iof_rampd_wr,
1000 
      pavr_iof_rampd_di,
1001 
 
1002 
      -- Program Memory extension address register (EIND)
1003 
      pavr_iof_eind,
1004 
      pavr_iof_eind_wr,
1005 
      pavr_iof_eind_di,
1006 
 
1007 
      -- AVR non-kernel (feature) register ports
1008 
      -- Port A
1009 
      pavr_pa,
1010 
 
1011 
      -- Interrupt-related interface signals to control module (to the pipeline).
1012 
      pavr_disable_int,
1013 
      pavr_int_rq,
1014 
      pavr_int_vec
1015 
   );
1016 
 
1017 
   -- Instantiate the Data Memory.
1018 
   pavr_dm_instance1: pavr_dm
1019 
   port map(
1020 
      pavr_clk,
1021 
      pavr_dm_wr,
1022 
      pavr_dm_addr,
1023 
      pavr_dm_di,
1024 
      pavr_dm_do
1025 
   );
1026 
 
1027 
   -- Instantiate the ALU.
1028 
   pavr_alu_instance1: pavr_alu
1029 
   port map(
1030 
      pavr_s5_alu_op1,
1031 
      pavr_s5_alu_op2,
1032 
      pavr_s5_alu_out,
1033 
      pavr_s5_alu_opcode,
1034 
      pavr_s5_alu_flagsin,
1035 
      pavr_s5_alu_flagsout
1036 
   );
1037 
 
1038 
 
1039 
 
1040 
   -- Main synchronous process ------------------------------------------------
1041 
   -- Basically, assign registers (whether they are inside or outside the pipeline)
1042 
   --    with the values generated by the instruction decoder, from the previous
1043 
   --    stage or other sources outside the pipeline.
1044 
   control_sync:
1045 
   process(pavr_clk, pavr_res, pavr_syncres,
1046 
           pavr_s5_op1, pavr_s5_op2, pavr_s4_s6_rfwr_addr1, pavr_s5_s6_rfwr_addr1, pavr_s6_rfwr_addr1,
1047 
           pavr_s4_s61_rfwr_addr2, pavr_s5_s61_rfwr_addr2, pavr_s6_s61_rfwr_addr2, pavr_s61_rfwr_addr2,
1048 
           pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active, pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active, pavr_bpr02, pavr_bpr02_addr,
1049 
           pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active, pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active, pavr_bpr12, pavr_bpr12_addr,
1050 
           pavr_s4_s5_iof_opcode, pavr_s5_iof_opcode, pavr_s4_s6_iof_opcode, pavr_s5_s6_iof_opcode, pavr_s6_iof_opcode,
1051 
           pavr_s4_s5s6_iof_addr, pavr_s5_iof_addr, pavr_s6_iof_addr, pavr_s4_s5s6_iof_bitaddr, pavr_s5_iof_bitaddr, pavr_s6_iof_bitaddr,
1052 
           pavr_s4_s5_alu_opcode, pavr_s5_alu_opcode, pavr_s4_s5_alu_op2_sel, pavr_s5_alu_op2_sel, pavr_s4_s5_op1_addr, pavr_s5_op1_addr,
1053 
           pavr_s4_s5_op2_addr, pavr_s5_op2_addr, pavr_s4_s5_k8, pavr_s5_k8, pavr_s6_alu_out, pavr_s61_alu_out_hi8, pavr_s4_dacu_q,
1054 
           pavr_s5_rf_dacu_q, pavr_s5_iof_dacu_q, pavr_s5_dm_dacu_q, pavr_s6_dacudo_sel, pavr_s5_k16, pavr_s4_k6, pavr_s4_k12, pavr_s4_k22int,
1055 
           pavr_s1_pc, pavr_s2_pc, pavr_s3_pc, pavr_s4_pc, pavr_s5_pc, pavr_s51_pc, pavr_s52_pc, pavr_s52_retpchi8, pavr_s53_retpcmid8,
1056 
           pavr_s54_retpclo8, pavr_s4_s5_skip_cond_sel, pavr_s5_skip_cond_sel, pavr_s4_s6_skip_cond_sel, pavr_s5_s6_skip_cond_sel,
1057 
           pavr_s4_s5_skip_bitrf_sel, pavr_s5_skip_bitrf_sel, pavr_s4_s6_skip_bitiof_sel, pavr_s5_s6_skip_bitiof_sel,
1058 
           pavr_s6_skip_bitiof_sel, pavr_s4_s5_k7_branch_offset, pavr_s5_k7_branch_offset, pavr_s6_branch_pc, pavr_s4_s5_branch_bitsreg_sel,
1059 
           pavr_s5_branch_bitsreg_sel, pavr_s3_instr, pavr_flush_s3, pavr_flush_s4, pavr_flush_s5,
1060 
           pavr_flush_s6, pavr_stall_s3, next_pavr_s4_s6_aluoutlo8_rfwr_rq,
1061 
           next_pavr_s4_s61_aluouthi8_rfwr_rq, next_pavr_s4_s6_iof_rfwr_rq, next_pavr_s4_s6_dacu_rfwr_rq, next_pavr_s4_s6_pm_rfwr_rq,
1062 
           next_pavr_s4_s6_rfwr_addr1, next_pavr_s4_s61_rfwr_addr2, next_pavr_s4_s5_ldstincrampx_xwr_rq, next_pavr_s4_s5_ldstdecrampx_xwr_rq,
1063 
           next_pavr_s4_s5_ldstincrampy_ywr_rq, next_pavr_s4_s5_ldstdecrampy_ywr_rq, next_pavr_s4_s5_ldstincrampz_zwr_rq, next_pavr_s4_s5_ldstdecrampz_zwr_rq,
1064 
           next_pavr_s4_s5_lpminc_zwr_rq, next_pavr_s4_s5_alu_bpr0wr_rq, next_pavr_s4_s6_daculd_bpr0wr_rq, next_pavr_s4_s5_alu_bpr1wr_rq,
1065 
           next_pavr_s4_s5_iof_rq, next_pavr_s4_s6_iof_rq, next_pavr_s4_s5_iof_opcode, next_pavr_s4_s6_iof_opcode, next_pavr_s4_s5s6_iof_addr,
1066 
           next_pavr_s4_s5s6_iof_bitaddr, next_pavr_s4_s5_alu_sregwr_rq, next_pavr_s4_s5_clriflag_sregwr_rq, next_pavr_s4_s5_setiflag_sregwr_rq,
1067 
           next_pavr_s4_s5_inc_spwr_rq, next_pavr_s4_s5_dec_spwr_rq, next_pavr_s4_s5s51s52_calldec_spwr_rq, next_pavr_s4_s5s51_retinc_spwr_rq,
1068 
           next_pavr_s4_s5_alu_opcode, next_pavr_s4_s5_alu_op1_hi8_sel, next_pavr_s4_s5_alu_op2_sel, pavr_s3_rfrd1_addr, pavr_s3_rfrd2_addr,
1069 
           next_pavr_s4_s5_k8, next_pavr_s4_dacu_q, next_pavr_s4_s5_x_dacurd_rq, next_pavr_s4_s5_y_dacurd_rq, next_pavr_s4_s5_z_dacurd_rq,
1070 
           next_pavr_s4_s5_sp_dacurd_rq, next_pavr_s4_s5_k16_dacurd_rq, next_pavr_s4_s5s51s52_pc_dacurd_rq, next_pavr_s4_s5_sp_dacuwr_rq,
1071 
           next_pavr_s4_s5_x_dacuwr_rq, next_pavr_s4_s5_y_dacuwr_rq, next_pavr_s4_s5_z_dacuwr_rq, next_pavr_s4_s5s51s52_pc_dacuwr_rq,
1072 
           next_pavr_s4_s5_lpm_pm_rq, next_pavr_s4_s5_elpm_pm_rq, next_pavr_s4_z_pm_rq, next_pavr_s4_zeind_pm_rq, next_pavr_s4_k22abs_pm_rq,
1073 
           next_pavr_s4_k12rel_pm_rq, next_pavr_s4_k22int_pm_rq, next_pavr_s4_s54_ret_pm_rq, next_pavr_s4_k6, next_pavr_s4_k12,
1074 
           next_pavr_s4_k22int, next_pavr_s4_s51s52s53_retpc_ld, next_pavr_s4_s5_stall_rq, next_pavr_s4_s6_stall_rq, next_pavr_s4_flush_s2_rq,
1075 
           next_pavr_s4_ret_flush_s2_rq, next_pavr_s4_nop_rq, next_pavr_s4_s5_skip_cond_sel, next_pavr_s4_s6_skip_cond_sel,
1076 
           next_pavr_s4_s5_skip_en, next_pavr_s4_s6_skip_en, next_pavr_s4_s5_skip_bitrf_sel, next_pavr_s4_s6_skip_bitiof_sel,
1077 
           next_pavr_s4_s5_k7_branch_offset, next_pavr_s4_s5_branch_cond_sel, next_pavr_s4_s5_branch_en, next_pavr_s4_s5_branch_bitsreg_sel,
1078 
           next_pavr_s4_instr32bits, next_pavr_s4_disable_int, pavr_stall_s4, pavr_rf_rd1_do, pavr_rf_rd2_do, pavr_s4_s6_aluoutlo8_rfwr_rq,
1079 
           pavr_s4_s61_aluouthi8_rfwr_rq, pavr_s4_s6_iof_rfwr_rq, pavr_s4_s6_dacu_rfwr_rq, pavr_s4_s6_pm_rfwr_rq, pavr_s4_s5_ldstincrampx_xwr_rq,
1080 
           pavr_s4_s5_ldstdecrampx_xwr_rq, pavr_s4_s5_ldstincrampy_ywr_rq, pavr_s4_s5_ldstdecrampy_ywr_rq, pavr_s4_s5_ldstincrampz_zwr_rq,
1081 
           pavr_s4_s5_ldstdecrampz_zwr_rq, pavr_s4_s5_lpminc_zwr_rq, pavr_s4_s5_alu_bpr0wr_rq, pavr_s4_s6_daculd_bpr0wr_rq, pavr_s4_s5_alu_bpr1wr_rq,
1082 
           pavr_s4_s5_iof_rq, pavr_s4_s6_iof_rq, pavr_s4_s5_alu_sregwr_rq, pavr_s4_s5_clriflag_sregwr_rq, pavr_s4_s5_setiflag_sregwr_rq,
1083 
           pavr_s4_s5_inc_spwr_rq, pavr_s4_s5_dec_spwr_rq, pavr_s4_s5s51s52_calldec_spwr_rq, pavr_s4_s5s51_retinc_spwr_rq,
1084 
           pavr_s4_s5_alu_op1_hi8_sel, pavr_s4_iof_dacu_q, pavr_s4_dm_dacu_q, pavr_s4_instr32bits, pavr_s4_s5_x_dacurd_rq,
1085 
           pavr_s4_s5_y_dacurd_rq, pavr_s4_s5_z_dacurd_rq, pavr_s4_s5_sp_dacurd_rq, pavr_s4_s5_k16_dacurd_rq, pavr_s4_s5s51s52_pc_dacurd_rq,
1086 
           pavr_s4_s5_sp_dacuwr_rq, pavr_s4_s5_x_dacuwr_rq, pavr_s4_s5_y_dacuwr_rq, pavr_s4_s5_z_dacuwr_rq, pavr_s4_s5s51s52_pc_dacuwr_rq,
1087 
           pavr_s4_s5_lpm_pm_rq, pavr_s4_s5_elpm_pm_rq, pavr_s4_s54_ret_pm_rq, pavr_s4_s51s52s53_retpc_ld, pavr_s4_s5_stall_rq,
1088 
           pavr_s4_s6_stall_rq, pavr_s4_ret_flush_s2_rq, pavr_s4_s5_skip_en, pavr_s4_s6_skip_en, pavr_s4_s5_branch_cond_sel,
1089 
           pavr_s4_s5_branch_en, pavr_s4_disable_int, pavr_stall_s5, pavr_s5_s6_aluoutlo8_rfwr_rq, pavr_s5_s61_aluouthi8_rfwr_rq,
1090 
           pavr_s5_s6_iof_rfwr_rq, pavr_s5_s6_dacu_rfwr_rq, pavr_s5_s6_pm_rfwr_rq, pavr_s5_s6_daculd_bpr0wr_rq, pavr_s5_s6_iof_rq,
1091 
           pavr_s5_calldec_spwr_rq, pavr_s5_retinc2_spwr_rq, pavr_s5_alu_out, pavr_s5_pchi8_dacurd_rq, pavr_s5_pclo8_dacuwr_rq,
1092 
           pavr_s5_s54_ret_pm_rq, pavr_s5_s51s52s53_retpc_ld, pavr_s5_s6_stall_rq, pavr_s5_ret_flush_s2_rq, next_pavr_s6_skip_rq,
1093 
           next_pavr_s6_branch_rq, pavr_s5_s6_skip_en, pavr_s5_disable_int, pavr_stall_s6, next_pavr_s61_skip_rq, pavr_s51_ret_flush_s2_rq,
1094 
           pavr_s51_pcmid8_dacuwr_rq, pavr_s51_calldec_spwr_rq, pavr_s51_disable_int, pavr_s51_retpchi8_ld, pavr_s51_pcmid8_dacurd_rq,
1095 
           pavr_s51_s54_ret_pm_rq, pavr_s52_ret_flush_s2_rq, pavr_s52_retpcmid8_ld, pavr_s52_s54_ret_pm_rq, pavr_s53_ret_flush_s2_rq,
1096 
           pavr_s53_s54_ret_pm_rq, pavr_s54_ret_flush_s2_rq, pavr_s4_nop_rq, pavr_nop_ack, pavr_s51_retpchi8_ld, pavr_dacu_do,
1097 
           pavr_s52_retpcmid8_ld, pavr_s53_retpclo8_ld, next_pavr_s1_pc, next_pavr_bpr0, next_pavr_bpr0_addr, next_pavr_bpr0_active,
1098 
           next_pavr_bpr1, next_pavr_bpr1_addr, next_pavr_bpr1_active, pavr_s5_dacudo_sel, next_pavr_s4_s5_k16_dacuwr_rq,
1099 
           pavr_s4_s5_k16_dacuwr_rq, next_pavr_s2_pmdo_valid, pavr_s6_s61_aluouthi8_rfwr_rq, pavr_stall_bpu,
1100 
           pavr_rf_do_shadow_active, pavr_rf_rd1_do_shadow, pavr_rf_rd2_do_shadow, next_pavr_s4_s6_iof_bpr0wr_rq,
1101 
           pavr_s4_s6_iof_bpr0wr_rq, pavr_s5_s6_iof_bpr0wr_rq, pavr_dacu_do_shadow_active, pavr_dacu_do_shadow,
1102 
           pavr_bpr13, pavr_bpr13_addr, pavr_bpr02_active, pavr_bpr03, pavr_bpr03_addr, pavr_bpr12_active,
1103 
           pavr_bpr20, pavr_bpr20_addr, pavr_bpr21, pavr_bpr21_addr, pavr_bpr22, pavr_bpr22_addr, pavr_bpr23,
1104 
           pavr_bpr23_addr, next_pavr_bpr2, next_pavr_bpr2_addr, next_pavr_bpr2_active, pavr_bpr20_active,
1105 
           pavr_bpr21_active, pavr_bpr22_active, pavr_zbpu, pavr_s4_pcinc, next_pavr_s4_pcinc,
1106 
           next_pavr_s4_s6_pmdo_bpr0wr_rq, pavr_s4_s6_pmdo_bpr0wr_rq, pavr_s5_s6_pmdo_bpr0wr_rq,
1107 
           next_pavr_s4_s5_elpmincrampz_zwr_rq, next_pavr_s4_s5_dacux_bpr12wr_rq, next_pavr_s4_s5_dacuy_bpr12wr_rq,
1108 
           next_pavr_s4_s5_dacuz_bpr12wr_rq, pavr_s4_s5_elpmincrampz_zwr_rq, pavr_s4_s5_dacux_bpr12wr_rq,
1109 
           pavr_s4_s5_dacuy_bpr12wr_rq, pavr_s4_s5_dacuz_bpr12wr_rq, next_pavr_s4_stall_rq, next_pavr_s3_instr,
1110 
           next_pavr_s3_pc, next_pavr_s2_pc)
1111 
   begin
1112 
      if pavr_res='1' then
1113 
         -- Asynchronous reset
1114 
 
1115 
         -- RF read port 1-related
1116 
 
1117 
         pavr_s5_op1 <= int_to_std_logic_vector(0, pavr_s5_op1'length);
1118 
 
1119 
         -- RF read port 2-related
1120 
 
1121 
         pavr_s5_op2 <= int_to_std_logic_vector(0, pavr_s5_op2'length);
1122 
 
1123 
         -- RF write port-related
1124 
         pavr_s4_s6_aluoutlo8_rfwr_rq  <= '0';
1125 
         pavr_s5_s6_aluoutlo8_rfwr_rq  <= '0';
1126 
            pavr_s6_aluoutlo8_rfwr_rq  <= '0';
1127 
         pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
1128 
         pavr_s5_s61_aluouthi8_rfwr_rq <= '0';
1129 
         pavr_s6_s61_aluouthi8_rfwr_rq <= '0';
1130 
            pavr_s61_aluouthi8_rfwr_rq <= '0';
1131 
         pavr_s4_s6_iof_rfwr_rq        <= '0';
1132 
         pavr_s5_s6_iof_rfwr_rq        <= '0';
1133 
            pavr_s6_iof_rfwr_rq        <= '0';
1134 
         pavr_s4_s6_dacu_rfwr_rq       <= '0';
1135 
         pavr_s5_s6_dacu_rfwr_rq       <= '0';
1136 
            pavr_s6_dacu_rfwr_rq       <= '0';
1137 
         pavr_s4_s6_pm_rfwr_rq         <= '0';
1138 
         pavr_s5_s6_pm_rfwr_rq         <= '0';
1139 
            pavr_s6_pm_rfwr_rq         <= '0';
1140 
 
1141 
         pavr_s4_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s4_s6_rfwr_addr1'length);
1142 
         pavr_s5_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s5_s6_rfwr_addr1'length);
1143 
            pavr_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s6_rfwr_addr1'length);
1144 
         pavr_s4_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s4_s61_rfwr_addr2'length);
1145 
         pavr_s5_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s5_s61_rfwr_addr2'length);
1146 
         pavr_s6_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s6_s61_rfwr_addr2'length);
1147 
            pavr_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s61_rfwr_addr2'length);
1148 
 
1149 
         -- Pointer registers-related
1150 
         pavr_s4_s5_ldstincrampx_xwr_rq   <= '0';
1151 
            pavr_s5_ldstincrampx_xwr_rq   <= '0';
1152 
         pavr_s4_s5_ldstdecrampx_xwr_rq   <= '0';
1153 
            pavr_s5_ldstdecrampx_xwr_rq   <= '0';
1154 
 
1155 
         pavr_s4_s5_ldstincrampy_ywr_rq   <= '0';
1156 
            pavr_s5_ldstincrampy_ywr_rq   <= '0';
1157 
         pavr_s4_s5_ldstdecrampy_ywr_rq   <= '0';
1158 
            pavr_s5_ldstdecrampy_ywr_rq   <= '0';
1159 
 
1160 
         pavr_s4_s5_ldstincrampz_zwr_rq   <= '0';
1161 
            pavr_s5_ldstincrampz_zwr_rq   <= '0';
1162 
         pavr_s4_s5_ldstdecrampz_zwr_rq   <= '0';
1163 
            pavr_s5_ldstdecrampz_zwr_rq   <= '0';
1164 
         pavr_s4_s5_elpmincrampz_zwr_rq   <= '0';
1165 
            pavr_s5_elpmincrampz_zwr_rq   <= '0';
1166 
         pavr_s4_s5_lpminc_zwr_rq         <= '0';
1167 
            pavr_s5_lpminc_zwr_rq         <= '0';
1168 
 
1169 
         -- BPU write, BPR0-related
1170 
         pavr_s4_s5_alu_bpr0wr_rq      <= '0';
1171 
            pavr_s5_alu_bpr0wr_rq      <= '0';
1172 
         pavr_s4_s6_iof_bpr0wr_rq      <= '0';
1173 
         pavr_s5_s6_iof_bpr0wr_rq      <= '0';
1174 
            pavr_s6_iof_bpr0wr_rq      <= '0';
1175 
         pavr_s4_s6_daculd_bpr0wr_rq   <= '0';
1176 
         pavr_s5_s6_daculd_bpr0wr_rq   <= '0';
1177 
            pavr_s6_daculd_bpr0wr_rq   <= '0';
1178 
         pavr_s4_s6_pmdo_bpr0wr_rq     <= '0';
1179 
         pavr_s5_s6_pmdo_bpr0wr_rq     <= '0';
1180 
            pavr_s6_pmdo_bpr0wr_rq     <= '0';
1181 
 
1182 
         pavr_bpr00        <= int_to_std_logic_vector(0, pavr_bpr00'length);
1183 
         pavr_bpr00_addr   <= int_to_std_logic_vector(0, pavr_bpr00_addr'length);
1184 
         pavr_bpr00_active <= '0';
1185 
         pavr_bpr01        <= int_to_std_logic_vector(0, pavr_bpr01'length);
1186 
         pavr_bpr01_addr   <= int_to_std_logic_vector(0, pavr_bpr01_addr'length);
1187 
         pavr_bpr01_active <= '0';
1188 
         pavr_bpr02        <= int_to_std_logic_vector(0, pavr_bpr02'length);
1189 
         pavr_bpr02_addr   <= int_to_std_logic_vector(0, pavr_bpr02_addr'length);
1190 
         pavr_bpr02_active <= '0';
1191 
         pavr_bpr03        <= int_to_std_logic_vector(0, pavr_bpr03'length);
1192 
         pavr_bpr03_addr   <= int_to_std_logic_vector(0, pavr_bpr03_addr'length);
1193 
         pavr_bpr03_active <= '0';
1194 
 
1195 
         -- BPU write, BPR1-related
1196 
         pavr_s4_s5_dacux_bpr12wr_rq   <= '0';
1197 
            pavr_s5_dacux_bpr12wr_rq   <= '0';
1198 
         pavr_s4_s5_dacuy_bpr12wr_rq   <= '0';
1199 
            pavr_s5_dacuy_bpr12wr_rq   <= '0';
1200 
         pavr_s4_s5_dacuz_bpr12wr_rq   <= '0';
1201 
            pavr_s5_dacuz_bpr12wr_rq   <= '0';
1202 
         pavr_s4_s5_alu_bpr1wr_rq      <= '0';
1203 
            pavr_s5_alu_bpr1wr_rq      <= '0';
1204 
 
1205 
         pavr_bpr10           <= int_to_std_logic_vector(0, pavr_bpr10'length);
1206 
         pavr_bpr10_addr      <= int_to_std_logic_vector(0, pavr_bpr10_addr'length);
1207 
         pavr_bpr10_active    <= '0';
1208 
         pavr_bpr11           <= int_to_std_logic_vector(0, pavr_bpr11'length);
1209 
         pavr_bpr11_addr      <= int_to_std_logic_vector(0, pavr_bpr11_addr'length);
1210 
         pavr_bpr11_active    <= '0';
1211 
         pavr_bpr12           <= int_to_std_logic_vector(0, pavr_bpr12'length);
1212 
         pavr_bpr12_addr      <= int_to_std_logic_vector(0, pavr_bpr12_addr'length);
1213 
         pavr_bpr12_active    <= '0';
1214 
         pavr_bpr13           <= int_to_std_logic_vector(0, pavr_bpr13'length);
1215 
         pavr_bpr13_addr      <= int_to_std_logic_vector(0, pavr_bpr13_addr'length);
1216 
         pavr_bpr13_active    <= '0';
1217 
 
1218 
         -- BPU write, BPR2-related
1219 
 
1220 
         pavr_bpr20           <= int_to_std_logic_vector(0, pavr_bpr20'length);
1221 
         pavr_bpr20_addr      <= int_to_std_logic_vector(0, pavr_bpr20_addr'length);
1222 
         pavr_bpr20_active    <= '0';
1223 
         pavr_bpr21           <= int_to_std_logic_vector(0, pavr_bpr21'length);
1224 
         pavr_bpr21_addr      <= int_to_std_logic_vector(0, pavr_bpr21_addr'length);
1225 
         pavr_bpr21_active    <= '0';
1226 
         pavr_bpr22           <= int_to_std_logic_vector(0, pavr_bpr22'length);
1227 
         pavr_bpr22_addr      <= int_to_std_logic_vector(0, pavr_bpr22_addr'length);
1228 
         pavr_bpr22_active    <= '0';
1229 
         pavr_bpr23           <= int_to_std_logic_vector(0, pavr_bpr23'length);
1230 
         pavr_bpr23_addr      <= int_to_std_logic_vector(0, pavr_bpr23_addr'length);
1231 
         pavr_bpr23_active    <= '0';
1232 
 
1233 
         -- IOF port-related
1234 
         pavr_s4_s5_iof_rq          <= '0';
1235 
            pavr_s5_iof_rq          <= '0';
1236 
         pavr_s4_s6_iof_rq          <= '0';
1237 
         pavr_s5_s6_iof_rq          <= '0';
1238 
            pavr_s6_iof_rq          <= '0';
1239 
 
1240 
         pavr_s4_s5_iof_opcode      <= int_to_std_logic_vector(0, pavr_s4_s5_iof_opcode'length);
1241 
            pavr_s5_iof_opcode      <= int_to_std_logic_vector(0, pavr_s5_iof_opcode'length);
1242 
         pavr_s4_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s4_s6_iof_opcode'length);
1243 
         pavr_s5_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s5_s6_iof_opcode'length);
1244 
            pavr_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s6_iof_opcode'length);
1245 
         pavr_s4_s5s6_iof_addr      <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_addr'length);
1246 
              pavr_s5_iof_addr      <= int_to_std_logic_vector(0, pavr_s5_iof_addr'length);
1247 
              pavr_s6_iof_addr      <= int_to_std_logic_vector(0, pavr_s6_iof_addr'length);
1248 
         pavr_s4_s5s6_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_bitaddr'length);
1249 
              pavr_s5_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s5_iof_bitaddr'length);
1250 
              pavr_s6_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s6_iof_bitaddr'length);
1251 
 
1252 
         -- SREG-related
1253 
         pavr_s4_s5_alu_sregwr_rq         <= '0';
1254 
            pavr_s5_alu_sregwr_rq         <= '0';
1255 
         pavr_s4_s5_clriflag_sregwr_rq    <= '0';
1256 
            pavr_s5_clriflag_sregwr_rq    <= '0';
1257 
         pavr_s4_s5_setiflag_sregwr_rq    <= '0';
1258 
            pavr_s5_setiflag_sregwr_rq    <= '0';
1259 
 
1260 
         -- SP-related
1261 
         pavr_s4_s5_inc_spwr_rq              <= '0';
1262 
            pavr_s5_inc_spwr_rq              <= '0';
1263 
         pavr_s4_s5_dec_spwr_rq              <= '0';
1264 
            pavr_s5_dec_spwr_rq              <= '0';
1265 
         pavr_s4_s5s51s52_calldec_spwr_rq    <= '0';
1266 
            pavr_s5_calldec_spwr_rq          <= '0';
1267 
            pavr_s51_calldec_spwr_rq         <= '0';
1268 
            pavr_s52_calldec_spwr_rq         <= '0';
1269 
         pavr_s4_s5s51_retinc_spwr_rq        <= '0';
1270 
            pavr_s5_retinc2_spwr_rq          <= '0';
1271 
            pavr_s51_retinc_spwr_rq          <= '0';
1272 
 
1273 
         -- ALU-related
1274 
         pavr_s4_s5_alu_opcode         <= int_to_std_logic_vector(0, pavr_s4_s5_alu_opcode'length);
1275 
            pavr_s5_alu_opcode         <= int_to_std_logic_vector(0, pavr_s5_alu_opcode'length);
1276 
         pavr_s4_s5_alu_op1_hi8_sel    <= '0';
1277 
            pavr_s5_alu_op1_hi8_sel    <= '0';
1278 
         pavr_s4_s5_alu_op2_sel        <= int_to_std_logic_vector(0, pavr_s4_s5_alu_op2_sel'length);
1279 
            pavr_s5_alu_op2_sel        <= int_to_std_logic_vector(0, pavr_s5_alu_op2_sel'length);
1280 
         pavr_s4_s5_op1_addr           <= int_to_std_logic_vector(0, pavr_s4_s5_op1_addr'length);
1281 
            pavr_s5_op1_addr           <= int_to_std_logic_vector(0, pavr_s5_op1_addr'length);
1282 
         pavr_s4_s5_op2_addr           <= int_to_std_logic_vector(0, pavr_s4_s5_op2_addr'length);
1283 
            pavr_s5_op2_addr           <= int_to_std_logic_vector(0, pavr_s5_op2_addr'length);
1284 
         pavr_s4_s5_k8                 <= int_to_std_logic_vector(0, pavr_s4_s5_k8'length);
1285 
            pavr_s5_k8                 <= int_to_std_logic_vector(0, pavr_s5_k8'length);
1286 
         pavr_s6_alu_out               <= int_to_std_logic_vector(0, pavr_s6_alu_out'length);
1287 
         pavr_s61_alu_out_hi8          <= int_to_std_logic_vector(0, pavr_s61_alu_out_hi8'length);
1288 
 
1289 
         -- DACU setup-related
1290 
         pavr_s4_dacu_q       <= int_to_std_logic_vector(0, pavr_s4_dacu_q'length);
1291 
         pavr_s5_rf_dacu_q    <= int_to_std_logic_vector(0, pavr_s5_rf_dacu_q'length);
1292 
         pavr_s5_iof_dacu_q   <= int_to_std_logic_vector(0, pavr_s5_iof_dacu_q'length);
1293 
         pavr_s5_dm_dacu_q    <= int_to_std_logic_vector(0, pavr_s5_dm_dacu_q'length);
1294 
         pavr_s6_dacudo_sel   <= int_to_std_logic_vector(0, pavr_s6_dacudo_sel'length);
1295 
         pavr_s5_k16          <= int_to_std_logic_vector(0, pavr_s5_k16'length);
1296 
 
1297 
         -- DACU read-related
1298 
         pavr_s4_s5_x_dacurd_rq        <= '0';
1299 
            pavr_s5_x_dacurd_rq        <= '0';
1300 
         pavr_s4_s5_y_dacurd_rq        <= '0';
1301 
            pavr_s5_y_dacurd_rq        <= '0';
1302 
         pavr_s4_s5_z_dacurd_rq        <= '0';
1303 
            pavr_s5_z_dacurd_rq        <= '0';
1304 
         pavr_s4_s5_sp_dacurd_rq       <= '0';
1305 
            pavr_s5_sp_dacurd_rq       <= '0';
1306 
         pavr_s4_s5_k16_dacurd_rq      <= '0';
1307 
            pavr_s5_k16_dacurd_rq      <= '0';
1308 
         pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
1309 
            pavr_s5_pchi8_dacurd_rq    <= '0';
1310 
            pavr_s51_pcmid8_dacurd_rq  <= '0';
1311 
            pavr_s52_pclo8_dacurd_rq   <= '0';
1312 
 
1313 
         -- DACU write-related
1314 
         pavr_s4_s5_sp_dacuwr_rq          <= '0';
1315 
            pavr_s5_sp_dacuwr_rq          <= '0';
1316 
         pavr_s4_s5_k16_dacuwr_rq         <= '0';
1317 
            pavr_s5_k16_dacuwr_rq         <= '0';
1318 
         pavr_s4_s5_x_dacuwr_rq           <= '0';
1319 
            pavr_s5_x_dacuwr_rq           <= '0';
1320 
         pavr_s4_s5_y_dacuwr_rq           <= '0';
1321 
            pavr_s5_y_dacuwr_rq           <= '0';
1322 
         pavr_s4_s5_z_dacuwr_rq           <= '0';
1323 
            pavr_s5_z_dacuwr_rq           <= '0';
1324 
         pavr_s4_s5s51s52_pc_dacuwr_rq    <= '0';
1325 
            pavr_s5_pclo8_dacuwr_rq       <= '0';
1326 
            pavr_s51_pcmid8_dacuwr_rq     <= '0';
1327 
            pavr_s52_pchi8_dacuwr_rq      <= '0';
1328 
 
1329 
         -- DM-related
1330 
 
1331 
         -- PM access-related
1332 
         pavr_s4_s5_lpm_pm_rq    <= '0';
1333 
            pavr_s5_lpm_pm_rq    <= '0';
1334 
         pavr_s4_s5_elpm_pm_rq   <= '0';
1335 
            pavr_s5_elpm_pm_rq   <= '0';
1336 
         pavr_s4_z_pm_rq         <= '0';
1337 
         pavr_s4_zeind_pm_rq     <= '0';
1338 
         pavr_s4_k22abs_pm_rq    <= '0';
1339 
         pavr_s4_k12rel_pm_rq    <= '0';
1340 
         pavr_s4_k22int_pm_rq    <= '0';
1341 
         pavr_s4_s54_ret_pm_rq   <= '0';
1342 
         pavr_s5_s54_ret_pm_rq   <= '0';
1343 
         pavr_s51_s54_ret_pm_rq  <= '0';
1344 
         pavr_s52_s54_ret_pm_rq  <= '0';
1345 
         pavr_s53_s54_ret_pm_rq  <= '0';
1346 
             pavr_s54_ret_pm_rq  <= '0';
1347 
 
1348 
         pavr_s4_k6                 <= int_to_std_logic_vector(0, pavr_s4_k6'length);
1349 
         pavr_s4_k12                <= int_to_std_logic_vector(0, pavr_s4_k12'length);
1350 
         pavr_s4_k22int             <= int_to_std_logic_vector(0, pavr_s4_k22int'length);
1351 
         pavr_s2_pc                 <= int_to_std_logic_vector(0, pavr_s2_pc'length);
1352 
         pavr_s3_pc                 <= int_to_std_logic_vector(0, pavr_s3_pc'length);
1353 
         pavr_s4_pc                 <= int_to_std_logic_vector(0, pavr_s4_pc'length);
1354 
         pavr_s5_pc                 <= int_to_std_logic_vector(0, pavr_s5_pc'length);
1355 
         pavr_s51_pc                <= int_to_std_logic_vector(0, pavr_s51_pc'length);
1356 
         pavr_s52_pc                <= int_to_std_logic_vector(0, pavr_s52_pc'length);
1357 
         pavr_s4_pcinc              <= '0';
1358 
         pavr_s4_s51s52s53_retpc_ld <= '0';
1359 
         pavr_s5_s51s52s53_retpc_ld <= '0';
1360 
            pavr_s51_retpchi8_ld    <= '0';
1361 
            pavr_s52_retpcmid8_ld   <= '0';
1362 
            pavr_s53_retpclo8_ld    <= '0';
1363 
         pavr_s52_retpchi8          <= int_to_std_logic_vector(0, pavr_s52_retpchi8'length);
1364 
         pavr_s53_retpcmid8         <= int_to_std_logic_vector(0, pavr_s53_retpcmid8'length);
1365 
         pavr_s54_retpclo8          <= int_to_std_logic_vector(0, pavr_s54_retpclo8'length);
1366 
         pavr_s1_pc                 <= int_to_std_logic_vector(0, pavr_s1_pc'length);              -- Note 1
1367 
         pavr_s2_pmdo_valid         <= '0';
1368 
 
1369 
         pavr_s6_zlsb               <= '0';
1370 
 
1371 
         -- SFU requests-related
1372 
            pavr_s4_stall_rq        <= '0';
1373 
         pavr_s4_s5_stall_rq        <= '0';
1374 
            pavr_s5_stall_rq        <= '0';
1375 
         pavr_s4_s6_stall_rq        <= '0';
1376 
         pavr_s5_s6_stall_rq        <= '0';
1377 
            pavr_s6_stall_rq        <= '0';
1378 
         pavr_s4_flush_s2_rq        <= '0';
1379 
         pavr_s4_ret_flush_s2_rq    <= '0';
1380 
         pavr_s5_ret_flush_s2_rq    <= '0';
1381 
         pavr_s51_ret_flush_s2_rq   <= '0';
1382 
         pavr_s52_ret_flush_s2_rq   <= '0';
1383 
         pavr_s53_ret_flush_s2_rq   <= '0';
1384 
         pavr_s54_ret_flush_s2_rq   <= '0';
1385 
         pavr_s55_ret_flush_s2_rq   <= '0';
1386 
         pavr_s6_skip_rq            <= '0';
1387 
         pavr_s61_skip_rq           <= '0';
1388 
         pavr_s6_branch_rq          <= '0';
1389 
         pavr_s4_nop_rq             <= '0';
1390 
 
1391 
         pavr_s4_s5_skip_cond_sel      <= int_to_std_logic_vector(0, pavr_s4_s5_skip_cond_sel'length);
1392 
            pavr_s5_skip_cond_sel      <= int_to_std_logic_vector(0, pavr_s5_skip_cond_sel'length);
1393 
         pavr_s4_s6_skip_cond_sel      <= '0';
1394 
         pavr_s5_s6_skip_cond_sel      <= '0';
1395 
            pavr_s6_skip_cond_sel      <= '0';
1396 
         pavr_s4_s5_skip_en            <= '0';
1397 
            pavr_s5_skip_en            <= '0';
1398 
         pavr_s4_s6_skip_en            <= '0';
1399 
         pavr_s5_s6_skip_en            <= '0';
1400 
            pavr_s6_skip_en            <= '0';
1401 
         pavr_s4_s5_skip_bitrf_sel     <= int_to_std_logic_vector(0, pavr_s4_s5_skip_bitrf_sel'length);
1402 
            pavr_s5_skip_bitrf_sel     <= int_to_std_logic_vector(0, pavr_s5_skip_bitrf_sel'length);
1403 
         pavr_s4_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s4_s6_skip_bitiof_sel'length);
1404 
         pavr_s5_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s5_s6_skip_bitiof_sel'length);
1405 
            pavr_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s6_skip_bitiof_sel'length);
1406 
 
1407 
         pavr_s4_s5_k7_branch_offset   <= int_to_std_logic_vector(0, pavr_s4_s5_k7_branch_offset'length);
1408 
            pavr_s5_k7_branch_offset   <= int_to_std_logic_vector(0, pavr_s5_k7_branch_offset'length);
1409 
         pavr_s6_branch_pc             <= int_to_std_logic_vector(0, pavr_s6_branch_pc'length);
1410 
         pavr_s4_s5_branch_cond_sel    <= '0';
1411 
            pavr_s5_branch_cond_sel    <= '0';
1412 
         pavr_s4_s5_branch_en          <= '0';
1413 
            pavr_s5_branch_en          <= '0';
1414 
         pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s4_s5_branch_bitsreg_sel'length);
1415 
            pavr_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s5_branch_bitsreg_sel'length);
1416 
 
1417 
         -- Others
1418 
         pavr_nop_ack         <= '0';
1419 
         pavr_s3_instr        <= int_to_std_logic_vector(0, pavr_s3_instr'length);
1420 
         pavr_s4_instr32bits  <= '0';
1421 
         pavr_s4_disable_int  <= '0';
1422 
         pavr_s5_disable_int  <= '0';
1423 
         pavr_s51_disable_int <= '0';
1424 
         pavr_s52_disable_int <= '0';
1425 
 
1426 
      elsif pavr_clk'event and pavr_clk='1' then
1427 
         -- Load registers ----------------------------------------------------
1428 
 
1429 
         -- Stage s1 ----------------------------------------------------------
1430 
         pavr_s2_pmdo_valid   <= next_pavr_s2_pmdo_valid;
1431 
         pavr_s2_pc           <= next_pavr_s2_pc;
1432 
 
1433 
         -- Stage s2 ----------------------------------------------------------
1434 
         pavr_s3_instr  <= next_pavr_s3_instr;
1435 
         pavr_s3_pc     <= next_pavr_s3_pc;
1436 
 
1437 
         -- Stage s3 ----------------------------------------------------------
1438 
         if pavr_flush_s3='1' then
1439 
            -- RF read port 1-related
1440 
 
1441 
            -- RF read port 2-related
1442 
 
1443 
            -- RF write port-related
1444 
            pavr_s4_s6_aluoutlo8_rfwr_rq  <= '0';
1445 
            pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
1446 
            pavr_s4_s6_iof_rfwr_rq        <= '0';
1447 
            pavr_s4_s6_dacu_rfwr_rq       <= '0';
1448 
            pavr_s4_s6_pm_rfwr_rq         <= '0';
1449 
 
1450 
            pavr_s4_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s4_s6_rfwr_addr1'length);
1451 
            pavr_s4_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s4_s61_rfwr_addr2'length);
1452 
 
1453 
            -- Pointer registers-related
1454 
            pavr_s4_s5_ldstincrampx_xwr_rq   <= '0';
1455 
            pavr_s4_s5_ldstdecrampx_xwr_rq   <= '0';
1456 
 
1457 
            pavr_s4_s5_ldstincrampy_ywr_rq   <= '0';
1458 
            pavr_s4_s5_ldstdecrampy_ywr_rq   <= '0';
1459 
 
1460 
            pavr_s4_s5_ldstincrampz_zwr_rq   <= '0';
1461 
            pavr_s4_s5_ldstdecrampz_zwr_rq   <= '0';
1462 
            pavr_s4_s5_elpmincrampz_zwr_rq   <= '0';
1463 
            pavr_s4_s5_lpminc_zwr_rq         <= '0';
1464 
 
1465 
            -- BPU write, BPR0-related
1466 
            pavr_s4_s5_alu_bpr0wr_rq      <= '0';
1467 
            pavr_s4_s6_iof_bpr0wr_rq      <= '0';
1468 
            pavr_s4_s6_daculd_bpr0wr_rq   <= '0';
1469 
            pavr_s4_s6_pmdo_bpr0wr_rq     <= '0';
1470 
 
1471 
            -- BPU write, BPR1-related
1472 
            pavr_s4_s5_dacux_bpr12wr_rq   <= '0';
1473 
            pavr_s4_s5_dacuy_bpr12wr_rq   <= '0';
1474 
            pavr_s4_s5_dacuz_bpr12wr_rq   <= '0';
1475 
            pavr_s4_s5_alu_bpr1wr_rq      <= '0';
1476 
 
1477 
            -- IOF port-related
1478 
            pavr_s4_s5_iof_rq          <= '0';
1479 
            pavr_s4_s6_iof_rq          <= '0';
1480 
 
1481 
            pavr_s4_s5_iof_opcode      <= int_to_std_logic_vector(0, pavr_s4_s5_iof_opcode'length);
1482 
            pavr_s4_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s4_s6_iof_opcode'length);
1483 
            pavr_s4_s5s6_iof_addr      <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_addr'length);
1484 
            pavr_s4_s5s6_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_bitaddr'length);
1485 
 
1486 
            -- SREG-related
1487 
            pavr_s4_s5_alu_sregwr_rq         <= '0';
1488 
            pavr_s4_s5_clriflag_sregwr_rq    <= '0';
1489 
            pavr_s4_s5_setiflag_sregwr_rq    <= '0';
1490 
 
1491 
            -- SP-related
1492 
            pavr_s4_s5_inc_spwr_rq              <= '0';
1493 
            pavr_s4_s5_dec_spwr_rq              <= '0';
1494 
            pavr_s4_s5s51s52_calldec_spwr_rq    <= '0';
1495 
            pavr_s4_s5s51_retinc_spwr_rq        <= '0';
1496 
 
1497 
            -- ALU-related
1498 
            pavr_s4_s5_alu_opcode         <= int_to_std_logic_vector(0, pavr_s4_s5_alu_opcode'length);
1499 
            pavr_s4_s5_alu_op1_hi8_sel    <= '0';
1500 
            pavr_s4_s5_alu_op2_sel        <= int_to_std_logic_vector(0, pavr_s4_s5_alu_op2_sel'length);
1501 
            pavr_s4_s5_op1_addr           <= int_to_std_logic_vector(0, pavr_s4_s5_op1_addr'length);
1502 
            pavr_s4_s5_op2_addr           <= int_to_std_logic_vector(0, pavr_s4_s5_op2_addr'length);
1503 
            pavr_s4_s5_k8                 <= int_to_std_logic_vector(0, pavr_s4_s5_k8'length);
1504 
 
1505 
            -- DACU setup-related
1506 
            pavr_s4_dacu_q    <= int_to_std_logic_vector(0, pavr_s4_dacu_q'length);
1507 
 
1508 
            -- DACU read-related
1509 
            pavr_s4_s5_x_dacurd_rq        <= '0';
1510 
            pavr_s4_s5_y_dacurd_rq        <= '0';
1511 
            pavr_s4_s5_z_dacurd_rq        <= '0';
1512 
            pavr_s4_s5_sp_dacurd_rq       <= '0';
1513 
            pavr_s4_s5_k16_dacurd_rq      <= '0';
1514 
            pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
1515 
 
1516 
            -- DACU write-related
1517 
            pavr_s4_s5_sp_dacuwr_rq          <= '0';
1518 
            pavr_s4_s5_k16_dacuwr_rq         <= '0';
1519 
            pavr_s4_s5_x_dacuwr_rq           <= '0';
1520 
            pavr_s4_s5_y_dacuwr_rq           <= '0';
1521 
            pavr_s4_s5_z_dacuwr_rq           <= '0';
1522 
            pavr_s4_s5s51s52_pc_dacuwr_rq    <= '0';
1523 
 
1524 
            -- DM-related
1525 
 
1526 
            -- PM access-related
1527 
            pavr_s4_s5_lpm_pm_rq    <= '0';
1528 
            pavr_s4_s5_elpm_pm_rq   <= '0';
1529 
            pavr_s4_z_pm_rq         <= '0';
1530 
            pavr_s4_zeind_pm_rq     <= '0';
1531 
            pavr_s4_k22abs_pm_rq    <= '0';
1532 
            pavr_s4_k12rel_pm_rq    <= '0';
1533 
            pavr_s4_k22int_pm_rq    <= '0';
1534 
            pavr_s4_s54_ret_pm_rq   <= '0';
1535 
 
1536 
            pavr_s4_k6                 <= int_to_std_logic_vector(0, pavr_s4_k6'length);
1537 
            pavr_s4_k12                <= int_to_std_logic_vector(0, pavr_s4_k12'length);
1538 
            pavr_s4_k22int             <= int_to_std_logic_vector(0, pavr_s4_k22int'length);
1539 
            --pavr_s4_pc                 <= int_to_std_logic_vector(0, pavr_s4_pc'length);  -- *** Comment this. The flush lines shouldn't interfere with PC temporary storage. Otherwise, 32 bit intructions are messed up.
1540 
            pavr_s4_pcinc              <= '0';
1541 
            pavr_s4_s51s52s53_retpc_ld <= '0';
1542 
 
1543 
            -- SFU requests-related
1544 
            pavr_s4_stall_rq           <= '0';
1545 
            pavr_s4_s5_stall_rq        <= '0';
1546 
            pavr_s4_s6_stall_rq        <= '0';
1547 
            pavr_s4_flush_s2_rq        <= '0';
1548 
            pavr_s4_ret_flush_s2_rq    <= '0';
1549 
            pavr_s4_nop_rq             <= '0';
1550 
 
1551 
            pavr_s4_s5_skip_cond_sel      <= int_to_std_logic_vector(0, pavr_s4_s5_skip_cond_sel'length);
1552 
            pavr_s4_s6_skip_cond_sel      <= '0';
1553 
            pavr_s4_s5_skip_en            <= '0';
1554 
            pavr_s4_s6_skip_en            <= '0';
1555 
            pavr_s4_s5_skip_bitrf_sel     <= int_to_std_logic_vector(0, pavr_s4_s5_skip_bitrf_sel'length);
1556 
            pavr_s4_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s4_s6_skip_bitiof_sel'length);
1557 
 
1558 
            pavr_s4_s5_k7_branch_offset   <= int_to_std_logic_vector(0, pavr_s4_s5_k7_branch_offset'length);
1559 
            pavr_s4_s5_branch_cond_sel    <= '0';
1560 
            pavr_s4_s5_branch_en          <= '0';
1561 
            pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s4_s5_branch_bitsreg_sel'length);
1562 
 
1563 
            -- Others
1564 
            pavr_s4_instr32bits  <= '0';
1565 
            pavr_s4_disable_int  <= '0';
1566 
         elsif pavr_stall_s3='0' then
1567 
            -- RF read port 1-related
1568 
 
1569 
            -- RF read port 2-related
1570 
 
1571 
            -- RF write port-related
1572 
            pavr_s4_s6_aluoutlo8_rfwr_rq  <= next_pavr_s4_s6_aluoutlo8_rfwr_rq;
1573 
            pavr_s4_s61_aluouthi8_rfwr_rq <= next_pavr_s4_s61_aluouthi8_rfwr_rq;
1574 
            pavr_s4_s6_iof_rfwr_rq        <= next_pavr_s4_s6_iof_rfwr_rq;
1575 
            pavr_s4_s6_dacu_rfwr_rq       <= next_pavr_s4_s6_dacu_rfwr_rq;
1576 
            pavr_s4_s6_pm_rfwr_rq         <= next_pavr_s4_s6_pm_rfwr_rq;
1577 
 
1578 
            pavr_s4_s6_rfwr_addr1         <= next_pavr_s4_s6_rfwr_addr1;
1579 
            pavr_s4_s61_rfwr_addr2        <= next_pavr_s4_s61_rfwr_addr2;
1580 
 
1581 
            -- Pointer registers-related
1582 
            pavr_s4_s5_ldstincrampx_xwr_rq   <= next_pavr_s4_s5_ldstincrampx_xwr_rq;
1583 
            pavr_s4_s5_ldstdecrampx_xwr_rq   <= next_pavr_s4_s5_ldstdecrampx_xwr_rq;
1584 
 
1585 
            pavr_s4_s5_ldstincrampy_ywr_rq   <= next_pavr_s4_s5_ldstincrampy_ywr_rq;
1586 
            pavr_s4_s5_ldstdecrampy_ywr_rq   <= next_pavr_s4_s5_ldstdecrampy_ywr_rq;
1587 
 
1588 
            pavr_s4_s5_ldstincrampz_zwr_rq   <= next_pavr_s4_s5_ldstincrampz_zwr_rq;
1589 
            pavr_s4_s5_ldstdecrampz_zwr_rq   <= next_pavr_s4_s5_ldstdecrampz_zwr_rq;
1590 
            pavr_s4_s5_elpmincrampz_zwr_rq   <= next_pavr_s4_s5_elpmincrampz_zwr_rq;
1591 
            pavr_s4_s5_lpminc_zwr_rq         <= next_pavr_s4_s5_lpminc_zwr_rq;
1592 
 
1593 
            -- BPU write, BPR0-related
1594 
            pavr_s4_s5_alu_bpr0wr_rq      <= next_pavr_s4_s5_alu_bpr0wr_rq;
1595 
            pavr_s4_s6_iof_bpr0wr_rq      <= next_pavr_s4_s6_iof_bpr0wr_rq;
1596 
            pavr_s4_s6_daculd_bpr0wr_rq   <= next_pavr_s4_s6_daculd_bpr0wr_rq;
1597 
            pavr_s4_s6_pmdo_bpr0wr_rq     <= next_pavr_s4_s6_pmdo_bpr0wr_rq;
1598 
 
1599 
            -- BPU write, BPR1-related
1600 
            pavr_s4_s5_dacux_bpr12wr_rq   <= next_pavr_s4_s5_dacux_bpr12wr_rq;
1601 
            pavr_s4_s5_dacuy_bpr12wr_rq   <= next_pavr_s4_s5_dacuy_bpr12wr_rq;
1602 
            pavr_s4_s5_dacuz_bpr12wr_rq   <= next_pavr_s4_s5_dacuz_bpr12wr_rq;
1603 
            pavr_s4_s5_alu_bpr1wr_rq      <= next_pavr_s4_s5_alu_bpr1wr_rq;
1604 
 
1605 
            -- IOF port-related
1606 
            pavr_s4_s5_iof_rq          <= next_pavr_s4_s5_iof_rq;
1607 
            pavr_s4_s6_iof_rq          <= next_pavr_s4_s6_iof_rq;
1608 
 
1609 
            pavr_s4_s5_iof_opcode      <= next_pavr_s4_s5_iof_opcode;
1610 
            pavr_s4_s6_iof_opcode      <= next_pavr_s4_s6_iof_opcode;
1611 
            pavr_s4_s5s6_iof_addr      <= next_pavr_s4_s5s6_iof_addr;
1612 
            pavr_s4_s5s6_iof_bitaddr   <= next_pavr_s4_s5s6_iof_bitaddr;
1613 
 
1614 
            -- SREG-related
1615 
            pavr_s4_s5_alu_sregwr_rq         <= next_pavr_s4_s5_alu_sregwr_rq;
1616 
            pavr_s4_s5_clriflag_sregwr_rq    <= next_pavr_s4_s5_clriflag_sregwr_rq;
1617 
            pavr_s4_s5_setiflag_sregwr_rq    <= next_pavr_s4_s5_setiflag_sregwr_rq;
1618 
 
1619 
            -- SP-related
1620 
            pavr_s4_s5_inc_spwr_rq              <= next_pavr_s4_s5_inc_spwr_rq;
1621 
            pavr_s4_s5_dec_spwr_rq              <= next_pavr_s4_s5_dec_spwr_rq;
1622 
            pavr_s4_s5s51s52_calldec_spwr_rq    <= next_pavr_s4_s5s51s52_calldec_spwr_rq;
1623 
            pavr_s4_s5s51_retinc_spwr_rq        <= next_pavr_s4_s5s51_retinc_spwr_rq;
1624 
 
1625 
            -- ALU-related
1626 
            pavr_s4_s5_alu_opcode         <= next_pavr_s4_s5_alu_opcode;
1627 
            pavr_s4_s5_alu_op1_hi8_sel    <= next_pavr_s4_s5_alu_op1_hi8_sel;
1628 
            pavr_s4_s5_alu_op2_sel        <= next_pavr_s4_s5_alu_op2_sel;
1629 
            pavr_s4_s5_op1_addr           <= pavr_s3_rfrd1_addr;              -- *** Attention here; unusual notation.
1630 
            pavr_s4_s5_op2_addr           <= pavr_s3_rfrd2_addr;              --
1631 
            pavr_s4_s5_k8                 <= next_pavr_s4_s5_k8;
1632 
 
1633 
            -- DACU setup-related
1634 
            pavr_s4_dacu_q    <= next_pavr_s4_dacu_q;
1635 
 
1636 
            -- DACU read-related
1637 
            pavr_s4_s5_x_dacurd_rq        <= next_pavr_s4_s5_x_dacurd_rq;
1638 
            pavr_s4_s5_y_dacurd_rq        <= next_pavr_s4_s5_y_dacurd_rq;
1639 
            pavr_s4_s5_z_dacurd_rq        <= next_pavr_s4_s5_z_dacurd_rq;
1640 
            pavr_s4_s5_sp_dacurd_rq       <= next_pavr_s4_s5_sp_dacurd_rq;
1641 
            pavr_s4_s5_k16_dacurd_rq      <= next_pavr_s4_s5_k16_dacurd_rq;
1642 
            pavr_s4_s5s51s52_pc_dacurd_rq <= next_pavr_s4_s5s51s52_pc_dacurd_rq;
1643 
 
1644 
            -- DACU write-related
1645 
            pavr_s4_s5_sp_dacuwr_rq          <= next_pavr_s4_s5_sp_dacuwr_rq;
1646 
            pavr_s4_s5_k16_dacuwr_rq         <= next_pavr_s4_s5_k16_dacuwr_rq;
1647 
            pavr_s4_s5_x_dacuwr_rq           <= next_pavr_s4_s5_x_dacuwr_rq;
1648 
            pavr_s4_s5_y_dacuwr_rq           <= next_pavr_s4_s5_y_dacuwr_rq;
1649 
            pavr_s4_s5_z_dacuwr_rq           <= next_pavr_s4_s5_z_dacuwr_rq;
1650 
            pavr_s4_s5s51s52_pc_dacuwr_rq    <= next_pavr_s4_s5s51s52_pc_dacuwr_rq;
1651 
 
1652 
            -- DM-related
1653 
 
1654 
            -- PM access-related
1655 
            pavr_s4_s5_lpm_pm_rq    <= next_pavr_s4_s5_lpm_pm_rq;
1656 
            pavr_s4_s5_elpm_pm_rq   <= next_pavr_s4_s5_elpm_pm_rq;
1657 
            pavr_s4_z_pm_rq         <= next_pavr_s4_z_pm_rq;
1658 
            pavr_s4_zeind_pm_rq     <= next_pavr_s4_zeind_pm_rq;
1659 
            pavr_s4_k22abs_pm_rq    <= next_pavr_s4_k22abs_pm_rq;
1660 
            pavr_s4_k12rel_pm_rq    <= next_pavr_s4_k12rel_pm_rq;
1661 
            pavr_s4_k22int_pm_rq    <= next_pavr_s4_k22int_pm_rq;
1662 
            pavr_s4_s54_ret_pm_rq   <= next_pavr_s4_s54_ret_pm_rq;
1663 
 
1664 
            pavr_s4_k6                 <= next_pavr_s4_k6;
1665 
            pavr_s4_k12                <= next_pavr_s4_k12;
1666 
            pavr_s4_k22int             <= next_pavr_s4_k22int;
1667 
            pavr_s4_pc                 <= pavr_s3_pc;
1668 
            pavr_s4_pcinc              <= next_pavr_s4_pcinc;
1669 
            pavr_s4_s51s52s53_retpc_ld <= next_pavr_s4_s51s52s53_retpc_ld;
1670 
 
1671 
            -- SFU requests-related
1672 
            pavr_s4_stall_rq           <= next_pavr_s4_stall_rq;
1673 
            pavr_s4_s5_stall_rq        <= next_pavr_s4_s5_stall_rq;
1674 
            pavr_s4_s6_stall_rq        <= next_pavr_s4_s6_stall_rq;
1675 
            pavr_s4_flush_s2_rq        <= next_pavr_s4_flush_s2_rq;
1676 
            pavr_s4_ret_flush_s2_rq    <= next_pavr_s4_ret_flush_s2_rq;
1677 
            pavr_s4_nop_rq             <= next_pavr_s4_nop_rq;
1678 
 
1679 
            pavr_s4_s5_skip_cond_sel      <= next_pavr_s4_s5_skip_cond_sel;
1680 
            pavr_s4_s6_skip_cond_sel      <= next_pavr_s4_s6_skip_cond_sel;
1681 
            pavr_s4_s5_skip_en            <= next_pavr_s4_s5_skip_en;
1682 
            pavr_s4_s6_skip_en            <= next_pavr_s4_s6_skip_en;
1683 
            pavr_s4_s5_skip_bitrf_sel     <= next_pavr_s4_s5_skip_bitrf_sel;
1684 
            pavr_s4_s6_skip_bitiof_sel    <= next_pavr_s4_s6_skip_bitiof_sel;
1685 
            pavr_s4_s5_k7_branch_offset   <= next_pavr_s4_s5_k7_branch_offset;
1686 
            pavr_s4_s5_branch_cond_sel    <= next_pavr_s4_s5_branch_cond_sel;
1687 
            pavr_s4_s5_branch_en          <= next_pavr_s4_s5_branch_en;
1688 
            pavr_s4_s5_branch_bitsreg_sel <= next_pavr_s4_s5_branch_bitsreg_sel;
1689 
 
1690 
            -- Others
1691 
            pavr_s4_instr32bits  <= next_pavr_s4_instr32bits;
1692 
            pavr_s4_disable_int  <= next_pavr_s4_disable_int;
1693 
         end if;
1694 
 
1695 
         -- Stage s4 ----------------------------------------------------------
1696 
         if pavr_flush_s4='1' then
1697 
            -- RF read port 1-related
1698 
 
1699 
            pavr_s5_op1 <= int_to_std_logic_vector(0, pavr_s5_op1'length);
1700 
 
1701 
            -- RF read port 2-related
1702 
 
1703 
            pavr_s5_op2 <= int_to_std_logic_vector(0, pavr_s5_op2'length);
1704 
 
1705 
            -- RF write port-related
1706 
            pavr_s5_s6_aluoutlo8_rfwr_rq  <= '0';
1707 
            pavr_s5_s61_aluouthi8_rfwr_rq <= '0';
1708 
            pavr_s5_s6_iof_rfwr_rq        <= '0';
1709 
            pavr_s5_s6_dacu_rfwr_rq       <= '0';
1710 
            pavr_s5_s6_pm_rfwr_rq         <= '0';
1711 
 
1712 
            pavr_s5_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s5_s6_rfwr_addr1'length);
1713 
            pavr_s5_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s5_s61_rfwr_addr2'length);
1714 
 
1715 
            -- Pointer registers-related
1716 
            pavr_s5_ldstincrampx_xwr_rq   <= '0';
1717 
            pavr_s5_ldstdecrampx_xwr_rq   <= '0';
1718 
 
1719 
            pavr_s5_ldstincrampy_ywr_rq   <= '0';
1720 
            pavr_s5_ldstdecrampy_ywr_rq   <= '0';
1721 
 
1722 
            pavr_s5_ldstincrampz_zwr_rq   <= '0';
1723 
            pavr_s5_ldstdecrampz_zwr_rq   <= '0';
1724 
            pavr_s5_elpmincrampz_zwr_rq   <= '0';
1725 
            pavr_s5_lpminc_zwr_rq         <= '0';
1726 
 
1727 
            -- BPU write, BPR0-related
1728 
            pavr_s5_alu_bpr0wr_rq         <= '0';
1729 
            pavr_s5_s6_iof_bpr0wr_rq      <= '0';
1730 
            pavr_s5_s6_daculd_bpr0wr_rq   <= '0';
1731 
            pavr_s5_s6_pmdo_bpr0wr_rq     <= '0';
1732 
 
1733 
            -- BPU write, BPR1-related
1734 
            pavr_s5_dacux_bpr12wr_rq   <= '0';
1735 
            pavr_s5_dacuy_bpr12wr_rq   <= '0';
1736 
            pavr_s5_dacuz_bpr12wr_rq   <= '0';
1737 
            pavr_s5_alu_bpr1wr_rq      <= '0';
1738 
 
1739 
            -- IOF port-related
1740 
            pavr_s5_iof_rq          <= '0';
1741 
            pavr_s5_s6_iof_rq       <= '0';
1742 
 
1743 
            pavr_s5_iof_opcode      <= int_to_std_logic_vector(0, pavr_s5_iof_opcode'length);
1744 
            pavr_s5_s6_iof_opcode   <= int_to_std_logic_vector(0, pavr_s5_s6_iof_opcode'length);
1745 
            pavr_s5_iof_addr        <= int_to_std_logic_vector(0, pavr_s5_iof_addr'length);
1746 
            pavr_s5_iof_bitaddr     <= int_to_std_logic_vector(0, pavr_s5_iof_bitaddr'length);
1747 
 
1748 
            -- SREG-related
1749 
            pavr_s5_alu_sregwr_rq         <= '0';
1750 
            pavr_s5_clriflag_sregwr_rq    <= '0';
1751 
            pavr_s5_setiflag_sregwr_rq    <= '0';
1752 
 
1753 
            -- SP-related
1754 
            pavr_s5_inc_spwr_rq        <= '0';
1755 
            pavr_s5_dec_spwr_rq        <= '0';
1756 
            pavr_s5_calldec_spwr_rq    <= '0';
1757 
            pavr_s5_retinc2_spwr_rq    <= '0';
1758 
 
1759 
            -- ALU-related
1760 
            pavr_s5_alu_opcode         <= int_to_std_logic_vector(0, pavr_s5_alu_opcode'length);
1761 
            pavr_s5_alu_op1_hi8_sel    <= '0';
1762 
            pavr_s5_alu_op2_sel        <= int_to_std_logic_vector(0, pavr_s5_alu_op2_sel'length);
1763 
            pavr_s5_op1_addr           <= int_to_std_logic_vector(0, pavr_s5_op1_addr'length);
1764 
            pavr_s5_op2_addr           <= int_to_std_logic_vector(0, pavr_s5_op2_addr'length);
1765 
            pavr_s5_k8                 <= int_to_std_logic_vector(0, pavr_s5_k8'length);
1766 
 
1767 
            -- DACU setup-related
1768 
            pavr_s5_rf_dacu_q    <= int_to_std_logic_vector(0, pavr_s5_rf_dacu_q'length);
1769 
            pavr_s5_iof_dacu_q   <= int_to_std_logic_vector(0, pavr_s5_iof_dacu_q'length);
1770 
            pavr_s5_dm_dacu_q    <= int_to_std_logic_vector(0, pavr_s5_dm_dacu_q'length);
1771 
            pavr_s5_k16          <= int_to_std_logic_vector(0, pavr_s5_k16'length);
1772 
 
1773 
            -- DACU read-related
1774 
            pavr_s5_x_dacurd_rq        <= '0';
1775 
            pavr_s5_y_dacurd_rq        <= '0';
1776 
            pavr_s5_z_dacurd_rq        <= '0';
1777 
            pavr_s5_sp_dacurd_rq       <= '0';
1778 
            pavr_s5_k16_dacurd_rq      <= '0';
1779 
            pavr_s5_pchi8_dacurd_rq    <= '0';
1780 
 
1781 
            -- DACU write-related
1782 
            pavr_s5_sp_dacuwr_rq       <= '0';
1783 
            pavr_s5_k16_dacuwr_rq      <= '0';
1784 
            pavr_s5_x_dacuwr_rq        <= '0';
1785 
            pavr_s5_y_dacuwr_rq        <= '0';
1786 
            pavr_s5_z_dacuwr_rq        <= '0';
1787 
            pavr_s5_pclo8_dacuwr_rq    <= '0';
1788 
 
1789 
            -- DM-related
1790 
 
1791 
            -- PM access-related
1792 
            pavr_s5_lpm_pm_rq       <= '0';
1793 
            pavr_s5_elpm_pm_rq      <= '0';
1794 
            pavr_s5_s54_ret_pm_rq   <= '0';
1795 
 
1796 
            --pavr_s5_pc              <= int_to_std_logic_vector(0, pavr_s5_pc'length);  -- *** Comment this. The flush lines shouldn't interfere with PC temporary storage. Otherwise, 32 bit intructions are messed up.
1797 
            pavr_s5_s51s52s53_retpc_ld <= '0';
1798 
 
1799 
            -- SFU requests-related
1800 
            pavr_s5_stall_rq           <= '0';
1801 
            pavr_s5_s6_stall_rq        <= '0';
1802 
            pavr_s5_ret_flush_s2_rq    <= '0';
1803 
 
1804 
            pavr_s5_skip_cond_sel      <= int_to_std_logic_vector(0, pavr_s5_skip_cond_sel'length);
1805 
            pavr_s5_s6_skip_cond_sel   <= '0';
1806 
            pavr_s5_skip_en            <= '0';
1807 
            pavr_s5_s6_skip_en         <= '0';
1808 
            pavr_s5_skip_bitrf_sel     <= int_to_std_logic_vector(0, pavr_s5_skip_bitrf_sel'length);
1809 
            pavr_s5_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s5_s6_skip_bitiof_sel'length);
1810 
            pavr_s5_k7_branch_offset   <= int_to_std_logic_vector(0, pavr_s5_k7_branch_offset'length);
1811 
            pavr_s5_branch_cond_sel    <= '0';
1812 
            pavr_s5_branch_en          <= '0';
1813 
            pavr_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s5_branch_bitsreg_sel'length);
1814 
 
1815 
            -- Others
1816 
            pavr_s5_disable_int  <= '0';
1817 
         elsif pavr_stall_s4='0' then
1818 
            -- RF read port 1-related
1819 
 
1820 
            if pavr_rf_do_shadow_active='0' then
1821 
               pavr_s5_op1 <= pavr_rf_rd1_do;
1822 
            else
1823 
               pavr_s5_op1 <= pavr_rf_rd1_do_shadow;
1824 
            end if;
1825 
 
1826 
            -- RF read port 2-related
1827 
 
1828 
            if pavr_rf_do_shadow_active='0' then
1829 
               pavr_s5_op2 <= pavr_rf_rd2_do;
1830 
            else
1831 
               pavr_s5_op2 <= pavr_rf_rd2_do_shadow;
1832 
            end if;
1833 
 
1834 
            -- RF write port-related
1835 
            pavr_s5_s6_aluoutlo8_rfwr_rq  <= pavr_s4_s6_aluoutlo8_rfwr_rq;
1836 
            pavr_s5_s61_aluouthi8_rfwr_rq <= pavr_s4_s61_aluouthi8_rfwr_rq;
1837 
            pavr_s5_s6_iof_rfwr_rq        <= pavr_s4_s6_iof_rfwr_rq;
1838 
            pavr_s5_s6_dacu_rfwr_rq       <= pavr_s4_s6_dacu_rfwr_rq;
1839 
            pavr_s5_s6_pm_rfwr_rq         <= pavr_s4_s6_pm_rfwr_rq;
1840 
 
1841 
            pavr_s5_s6_rfwr_addr1         <= pavr_s4_s6_rfwr_addr1;
1842 
            pavr_s5_s61_rfwr_addr2        <= pavr_s4_s61_rfwr_addr2;
1843 
 
1844 
            -- Pointer registers-related
1845 
            pavr_s5_ldstincrampx_xwr_rq   <= pavr_s4_s5_ldstincrampx_xwr_rq;
1846 
            pavr_s5_ldstdecrampx_xwr_rq   <= pavr_s4_s5_ldstdecrampx_xwr_rq;
1847 
 
1848 
            pavr_s5_ldstincrampy_ywr_rq   <= pavr_s4_s5_ldstincrampy_ywr_rq;
1849 
            pavr_s5_ldstdecrampy_ywr_rq   <= pavr_s4_s5_ldstdecrampy_ywr_rq;
1850 
 
1851 
            pavr_s5_ldstincrampz_zwr_rq   <= pavr_s4_s5_ldstincrampz_zwr_rq;
1852 
            pavr_s5_ldstdecrampz_zwr_rq   <= pavr_s4_s5_ldstdecrampz_zwr_rq;
1853 
            pavr_s5_elpmincrampz_zwr_rq   <= pavr_s4_s5_elpmincrampz_zwr_rq;
1854 
            pavr_s5_lpminc_zwr_rq         <= pavr_s4_s5_lpminc_zwr_rq;
1855 
 
1856 
            -- BPU write, BPR0-related
1857 
            pavr_s5_alu_bpr0wr_rq         <= pavr_s4_s5_alu_bpr0wr_rq;
1858 
            pavr_s5_s6_iof_bpr0wr_rq      <= pavr_s4_s6_iof_bpr0wr_rq;
1859 
            pavr_s5_s6_daculd_bpr0wr_rq   <= pavr_s4_s6_daculd_bpr0wr_rq;
1860 
            pavr_s5_s6_pmdo_bpr0wr_rq     <= pavr_s4_s6_pmdo_bpr0wr_rq;
1861 
 
1862 
            -- BPU write, BPR1-related
1863 
            pavr_s5_dacux_bpr12wr_rq   <= pavr_s4_s5_dacux_bpr12wr_rq;
1864 
            pavr_s5_dacuy_bpr12wr_rq   <= pavr_s4_s5_dacuy_bpr12wr_rq;
1865 
            pavr_s5_dacuz_bpr12wr_rq   <= pavr_s4_s5_dacuz_bpr12wr_rq;
1866 
            pavr_s5_alu_bpr1wr_rq      <= pavr_s4_s5_alu_bpr1wr_rq;
1867 
 
1868 
            -- IOF port-related
1869 
            pavr_s5_iof_rq          <= pavr_s4_s5_iof_rq;
1870 
            pavr_s5_s6_iof_rq       <= pavr_s4_s6_iof_rq;
1871 
 
1872 
            pavr_s5_iof_opcode      <= pavr_s4_s5_iof_opcode;
1873 
            pavr_s5_s6_iof_opcode   <= pavr_s4_s6_iof_opcode;
1874 
            pavr_s5_iof_addr        <= pavr_s4_s5s6_iof_addr;
1875 
            pavr_s5_iof_bitaddr     <= pavr_s4_s5s6_iof_bitaddr;
1876 
 
1877 
            -- SREG-related
1878 
            pavr_s5_alu_sregwr_rq         <= pavr_s4_s5_alu_sregwr_rq;
1879 
            pavr_s5_clriflag_sregwr_rq    <= pavr_s4_s5_clriflag_sregwr_rq;
1880 
            pavr_s5_setiflag_sregwr_rq    <= pavr_s4_s5_setiflag_sregwr_rq;
1881 
 
1882 
            -- SP-related
1883 
            pavr_s5_inc_spwr_rq        <= pavr_s4_s5_inc_spwr_rq;
1884 
            pavr_s5_dec_spwr_rq        <= pavr_s4_s5_dec_spwr_rq;
1885 
            pavr_s5_calldec_spwr_rq    <= pavr_s4_s5s51s52_calldec_spwr_rq;
1886 
            pavr_s5_retinc2_spwr_rq    <= pavr_s4_s5s51_retinc_spwr_rq;
1887 
 
1888 
            -- ALU-related
1889 
            pavr_s5_alu_opcode         <= pavr_s4_s5_alu_opcode;
1890 
            pavr_s5_alu_op1_hi8_sel    <= pavr_s4_s5_alu_op1_hi8_sel;
1891 
            pavr_s5_alu_op2_sel        <= pavr_s4_s5_alu_op2_sel;
1892 
            pavr_s5_op1_addr           <= pavr_s4_s5_op1_addr;
1893 
            pavr_s5_op2_addr           <= pavr_s4_s5_op2_addr;
1894 
            pavr_s5_k8                 <= pavr_s4_s5_k8;
1895 
 
1896 
            -- DACU setup-related
1897 
            pavr_s5_rf_dacu_q    <= pavr_s4_dacu_q;
1898 
            pavr_s5_iof_dacu_q   <= pavr_s4_iof_dacu_q;
1899 
            pavr_s5_dm_dacu_q    <= pavr_s4_dm_dacu_q;
1900 
            if pavr_s4_instr32bits='1' then
1901 
               pavr_s5_k16       <= pavr_s3_instr;
1902 
            end if;
1903 
 
1904 
            -- DACU read-related
1905 
            pavr_s5_x_dacurd_rq        <= pavr_s4_s5_x_dacurd_rq;
1906 
            pavr_s5_y_dacurd_rq        <= pavr_s4_s5_y_dacurd_rq;
1907 
            pavr_s5_z_dacurd_rq        <= pavr_s4_s5_z_dacurd_rq;
1908 
            pavr_s5_sp_dacurd_rq       <= pavr_s4_s5_sp_dacurd_rq;
1909 
            pavr_s5_k16_dacurd_rq      <= pavr_s4_s5_k16_dacurd_rq;
1910 
            pavr_s5_pchi8_dacurd_rq    <= pavr_s4_s5s51s52_pc_dacurd_rq;
1911 
 
1912 
            -- DACU write-related
1913 
            pavr_s5_sp_dacuwr_rq       <= pavr_s4_s5_sp_dacuwr_rq;
1914 
            pavr_s5_k16_dacuwr_rq      <= pavr_s4_s5_k16_dacuwr_rq;
1915 
            pavr_s5_x_dacuwr_rq        <= pavr_s4_s5_x_dacuwr_rq;
1916 
            pavr_s5_y_dacuwr_rq        <= pavr_s4_s5_y_dacuwr_rq;
1917 
            pavr_s5_z_dacuwr_rq        <= pavr_s4_s5_z_dacuwr_rq;
1918 
            pavr_s5_pclo8_dacuwr_rq    <= pavr_s4_s5s51s52_pc_dacuwr_rq;
1919 
 
1920 
            -- DM-related
1921 
 
1922 
            -- PM access-related
1923 
            pavr_s5_lpm_pm_rq          <= pavr_s4_s5_lpm_pm_rq;
1924 
            pavr_s5_elpm_pm_rq         <= pavr_s4_s5_elpm_pm_rq;
1925 
            pavr_s5_s54_ret_pm_rq      <= pavr_s4_s54_ret_pm_rq;
1926 
 
1927 
            if pavr_s4_pcinc='1' then
1928 
               pavr_s5_pc  <= pavr_s4_pc + 1;
1929 
            else
1930 
               pavr_s5_pc  <= pavr_s4_pc;
1931 
            end if;
1932 
            pavr_s5_s51s52s53_retpc_ld <= pavr_s4_s51s52s53_retpc_ld;
1933 
 
1934 
            -- SFU requests-related
1935 
            pavr_s5_stall_rq           <= pavr_s4_s5_stall_rq;
1936 
            pavr_s5_s6_stall_rq        <= pavr_s4_s6_stall_rq;
1937 
            pavr_s5_ret_flush_s2_rq    <= pavr_s4_ret_flush_s2_rq;
1938 
 
1939 
            pavr_s5_skip_cond_sel      <= pavr_s4_s5_skip_cond_sel;
1940 
            pavr_s5_s6_skip_cond_sel   <= pavr_s4_s6_skip_cond_sel;
1941 
            pavr_s5_skip_en            <= pavr_s4_s5_skip_en;
1942 
            pavr_s5_s6_skip_en         <= pavr_s4_s6_skip_en;
1943 
            pavr_s5_skip_bitrf_sel     <= pavr_s4_s5_skip_bitrf_sel;
1944 
            pavr_s5_s6_skip_bitiof_sel <= pavr_s4_s6_skip_bitiof_sel;
1945 
            pavr_s5_k7_branch_offset   <= pavr_s4_s5_k7_branch_offset;
1946 
            pavr_s5_branch_cond_sel    <= pavr_s4_s5_branch_cond_sel;
1947 
            pavr_s5_branch_en          <= pavr_s4_s5_branch_en;
1948 
            pavr_s5_branch_bitsreg_sel <= pavr_s4_s5_branch_bitsreg_sel;
1949 
 
1950 
            -- Others
1951 
            pavr_s5_disable_int  <= pavr_s4_disable_int;
1952 
         end if;
1953 
 
1954 
         -- Stage s5 ----------------------------------------------------------
1955 
         if pavr_flush_s5='1' then
1956 
            -- RF read port 1-related
1957 
 
1958 
            -- RF read port 2-related
1959 
 
1960 
            -- RF write port-related
1961 
            pavr_s6_aluoutlo8_rfwr_rq        <= '0';
1962 
            pavr_s6_s61_aluouthi8_rfwr_rq    <= '0';
1963 
            pavr_s6_iof_rfwr_rq              <= '0';
1964 
            pavr_s6_dacu_rfwr_rq             <= '0';
1965 
            pavr_s6_pm_rfwr_rq               <= '0';
1966 
 
1967 
            pavr_s6_rfwr_addr1               <= int_to_std_logic_vector(0, pavr_s6_rfwr_addr1'length);
1968 
            pavr_s6_s61_rfwr_addr2           <= int_to_std_logic_vector(0, pavr_s6_s61_rfwr_addr2'length);
1969 
 
1970 
            -- Pointer registers-related
1971 
 
1972 
            -- BPU write, BPR0-related
1973 
            pavr_s6_iof_bpr0wr_rq      <= '0';
1974 
            pavr_s6_daculd_bpr0wr_rq   <= '0';
1975 
            pavr_s6_pmdo_bpr0wr_rq     <= '0';
1976 
 
1977 
            -- BPU write, BPR1-related
1978 
 
1979 
            -- IOF port-related
1980 
            pavr_s6_iof_rq       <= '0';
1981 
 
1982 
            pavr_s6_iof_opcode   <= int_to_std_logic_vector(0, pavr_s6_iof_opcode'length);
1983 
            pavr_s6_iof_addr     <= int_to_std_logic_vector(0, pavr_s6_iof_addr'length);
1984 
            pavr_s6_iof_bitaddr  <= int_to_std_logic_vector(0, pavr_s6_iof_bitaddr'length);
1985 
 
1986 
            -- SREG-related
1987 
 
1988 
            -- SP-related
1989 
            pavr_s51_calldec_spwr_rq   <= '0';
1990 
            pavr_s51_retinc_spwr_rq    <= '0';
1991 
 
1992 
            -- ALU-related
1993 
            pavr_s6_alu_out   <= int_to_std_logic_vector(0, pavr_s6_alu_out'length);
1994 
 
1995 
            -- DACU setup-related
1996 
 
1997 
            -- DACU read-related
1998 
            pavr_s51_pcmid8_dacurd_rq  <= '0';
1999 
 
2000 
            -- DACU write-related
2001 
            pavr_s51_pcmid8_dacuwr_rq  <= '0';
2002 
 
2003 
            -- DM-related
2004 
 
2005 
            -- PM access-related
2006 
            pavr_s51_s54_ret_pm_rq  <= '0';
2007 
 
2008 
            --pavr_s51_pc             <= int_to_std_logic_vector(0, pavr_s51_pc'length); -- *** Comment this. The flush lines shouldn't interfere with PC temporary storage. Otherwise, 32 bit intructions are messed up.
2009 
            pavr_s51_retpchi8_ld    <= '0';
2010 
            pavr_s6_zlsb            <= '0';
2011 
 
2012 
            -- SFU requests-related
2013 
            pavr_s6_stall_rq           <= '0';
2014 
            pavr_s51_ret_flush_s2_rq   <= '0';
2015 
            pavr_s6_skip_rq            <= '0';
2016 
            pavr_s6_branch_rq          <= '0';
2017 
 
2018 
            pavr_s6_skip_cond_sel      <= '0';
2019 
            pavr_s6_skip_en            <= '0';
2020 
            pavr_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s6_skip_bitiof_sel'length);
2021 
            pavr_s6_branch_pc          <= int_to_std_logic_vector(0, pavr_s6_branch_pc'length);
2022 
 
2023 
            -- Others
2024 
            pavr_s51_disable_int <= '0';
2025 
         elsif pavr_stall_s5='0' then
2026 
            -- RF read port 1-related
2027 
 
2028 
            -- RF read port 2-related
2029 
 
2030 
            -- RF write port-related
2031 
            pavr_s6_aluoutlo8_rfwr_rq        <= pavr_s5_s6_aluoutlo8_rfwr_rq;
2032 
            pavr_s6_s61_aluouthi8_rfwr_rq    <= pavr_s5_s61_aluouthi8_rfwr_rq;
2033 
            pavr_s6_iof_rfwr_rq              <= pavr_s5_s6_iof_rfwr_rq;
2034 
            pavr_s6_dacu_rfwr_rq             <= pavr_s5_s6_dacu_rfwr_rq;
2035 
            pavr_s6_pm_rfwr_rq               <= pavr_s5_s6_pm_rfwr_rq;
2036 
 
2037 
            pavr_s6_rfwr_addr1               <= pavr_s5_s6_rfwr_addr1;
2038 
            pavr_s6_s61_rfwr_addr2           <= pavr_s5_s61_rfwr_addr2;
2039 
 
2040 
            -- Pointer registers-related
2041 
 
2042 
            -- BPU write, BPR0-related
2043 
            pavr_s6_iof_bpr0wr_rq      <= pavr_s5_s6_iof_bpr0wr_rq;
2044 
            pavr_s6_daculd_bpr0wr_rq   <= pavr_s5_s6_daculd_bpr0wr_rq;
2045 
            pavr_s6_pmdo_bpr0wr_rq     <= pavr_s5_s6_pmdo_bpr0wr_rq;
2046 
 
2047 
            -- BPU write, BPR1-related
2048 
 
2049 
            -- IOF port-related
2050 
            pavr_s6_iof_rq       <= pavr_s5_s6_iof_rq;
2051 
 
2052 
            pavr_s6_iof_opcode   <= pavr_s5_s6_iof_opcode;
2053 
            pavr_s6_iof_addr     <= pavr_s5_iof_addr;
2054 
            pavr_s6_iof_bitaddr  <= pavr_s5_iof_bitaddr;
2055 
 
2056 
            -- SREG-related
2057 
 
2058 
            -- SP-related
2059 
            pavr_s51_calldec_spwr_rq   <= pavr_s5_calldec_spwr_rq;
2060 
            pavr_s51_retinc_spwr_rq    <= pavr_s5_retinc2_spwr_rq;
2061 
 
2062 
            -- ALU-related
2063 
            pavr_s6_alu_out   <= pavr_s5_alu_out;
2064 
 
2065 
            -- DACU setup-related
2066 
            pavr_s51_pcmid8_dacurd_rq  <= pavr_s5_pchi8_dacurd_rq;
2067 
 
2068 
            -- DACU read-related
2069 
 
2070 
            -- DACU write-related
2071 
            pavr_s51_pcmid8_dacuwr_rq  <= pavr_s5_pclo8_dacuwr_rq;
2072 
 
2073 
            -- DM-related
2074 
 
2075 
            -- PM access-related
2076 
            pavr_s51_s54_ret_pm_rq  <= pavr_s5_s54_ret_pm_rq;
2077 
 
2078 
            pavr_s51_pc             <= pavr_s5_pc;
2079 
            pavr_s51_retpchi8_ld    <= pavr_s5_s51s52s53_retpc_ld;
2080 
            pavr_s6_zlsb            <= pavr_zbpu(0);
2081 
 
2082 
            -- SFU requests-related
2083 
            pavr_s6_stall_rq           <= pavr_s5_s6_stall_rq;
2084 
            pavr_s51_ret_flush_s2_rq   <= pavr_s5_ret_flush_s2_rq;
2085 
            pavr_s6_skip_rq            <= next_pavr_s6_skip_rq;
2086 
            pavr_s6_branch_rq          <= next_pavr_s6_branch_rq;
2087 
 
2088 
            pavr_s6_skip_cond_sel      <= pavr_s5_s6_skip_cond_sel;
2089 
            pavr_s6_skip_en            <= pavr_s5_s6_skip_en;
2090 
            pavr_s6_skip_bitiof_sel    <= pavr_s5_s6_skip_bitiof_sel;
2091 
            pavr_s6_branch_pc          <= sign_extend(pavr_s5_k7_branch_offset, 22) + pavr_s5_pc;
2092 
 
2093 
            -- Others
2094 
            pavr_s51_disable_int <= pavr_s5_disable_int;
2095 
         end if;
2096 
 
2097 
         -- Stage s6 ----------------------------------------------------------
2098 
         if pavr_flush_s6='1' then
2099 
            -- RF read port 1-related
2100 
 
2101 
            -- RF read port 2-related
2102 
 
2103 
            -- RF write port-related
2104 
 
2105 
            pavr_s61_rfwr_addr2  <= int_to_std_logic_vector(0, pavr_s61_rfwr_addr2'length);
2106 
            pavr_s61_aluouthi8_rfwr_rq <= '0';
2107 
 
2108 
            -- Pointer registers-related
2109 
 
2110 
            -- BPU write, BPR0-related
2111 
 
2112 
            -- BPU write, BPR1-related
2113 
 
2114 
            -- IOF port-related
2115 
 
2116 
            -- SREG-related
2117 
 
2118 
            -- SP-related
2119 
 
2120 
            -- ALU-related
2121 
            pavr_s61_alu_out_hi8    <= int_to_std_logic_vector(0, pavr_s61_alu_out_hi8'length);
2122 
 
2123 
            -- DACU setup-related
2124 
 
2125 
            -- DACU read-related
2126 
 
2127 
            -- DACU write-related
2128 
 
2129 
            -- DM-related
2130 
 
2131 
            -- PM access-related
2132 
 
2133 
            -- SFU requests-related
2134 
            pavr_s61_skip_rq <= '0';
2135 
 
2136 
            -- Others
2137 
         elsif pavr_stall_s6='0' then
2138 
            -- RF read port 1-related
2139 
 
2140 
            -- RF read port 2-related
2141 
 
2142 
            -- RF write port-related
2143 
 
2144 
            pavr_s61_rfwr_addr2        <= pavr_s6_s61_rfwr_addr2;
2145 
            pavr_s61_aluouthi8_rfwr_rq <= pavr_s6_s61_aluouthi8_rfwr_rq;
2146 
 
2147 
            -- Pointer registers-related
2148 
 
2149 
            -- BPU write, BPR0-related
2150 
 
2151 
            -- BPU write, BPR1-related
2152 
 
2153 
            -- IOF port-related
2154 
 
2155 
            -- SREG-related
2156 
 
2157 
            -- SP-related
2158 
 
2159 
            -- ALU-related
2160 
            pavr_s61_alu_out_hi8    <= pavr_s6_alu_out(15 downto 8);
2161 
 
2162 
            -- DACU setup-related
2163 
 
2164 
            -- DACU read-related
2165 
 
2166 
            -- DACU write-related
2167 
 
2168 
            -- DM-related
2169 
 
2170 
            -- PM access-related
2171 
 
2172 
            -- SFU requests-related
2173 
            pavr_s61_skip_rq <= next_pavr_s61_skip_rq;
2174 
 
2175 
            -- Others
2176 
         end if;
2177 
 
2178 
         -- Stage s51 ---------------------------------------------------------
2179 
         pavr_s52_ret_flush_s2_rq   <= pavr_s51_ret_flush_s2_rq;
2180 
         pavr_s52_pc                <= pavr_s51_pc;
2181 
         pavr_s52_pchi8_dacuwr_rq   <= pavr_s51_pcmid8_dacuwr_rq;
2182 
         pavr_s52_calldec_spwr_rq   <= pavr_s51_calldec_spwr_rq;
2183 
         pavr_s52_disable_int       <= pavr_s51_disable_int;
2184 
         pavr_s52_retpcmid8_ld      <= pavr_s51_retpchi8_ld;
2185 
         pavr_s52_pclo8_dacurd_rq   <= pavr_s51_pcmid8_dacurd_rq;
2186 
         pavr_s52_s54_ret_pm_rq     <= pavr_s51_s54_ret_pm_rq;
2187 
 
2188 
         -- Stage s52 ---------------------------------------------------------
2189 
         pavr_s53_ret_flush_s2_rq   <= pavr_s52_ret_flush_s2_rq;
2190 
         pavr_s53_retpclo8_ld       <= pavr_s52_retpcmid8_ld;
2191 
         pavr_s53_s54_ret_pm_rq     <= pavr_s52_s54_ret_pm_rq;
2192 
 
2193 
         -- Stage s53 ---------------------------------------------------------
2194 
         pavr_s54_ret_flush_s2_rq   <= pavr_s53_ret_flush_s2_rq;
2195 
         pavr_s54_ret_pm_rq         <= pavr_s53_s54_ret_pm_rq;
2196 
 
2197 
         -- Stage s54 ---------------------------------------------------------
2198 
         pavr_s55_ret_flush_s2_rq   <= pavr_s54_ret_flush_s2_rq;
2199 
 
2200 
         -- Others ------------------------------------------------------------
2201 
         if pavr_s4_nop_rq='1' and pavr_nop_ack='0' then
2202 
            pavr_nop_ack <= '1';
2203 
         else
2204 
            pavr_nop_ack <= '0';
2205 
         end if;
2206 
 
2207 
         if pavr_s51_retpchi8_ld='1' then
2208 
            if pavr_dacu_do_shadow_active='0' then
2209 
               pavr_s52_retpchi8  <= pavr_dacu_do;
2210 
            else
2211 
               pavr_s52_retpchi8  <= pavr_dacu_do_shadow;
2212 
            end if;
2213 
         end if;
2214 
         if pavr_s52_retpcmid8_ld='1' then
2215 
            if pavr_dacu_do_shadow_active='0' then
2216 
               pavr_s53_retpcmid8 <= pavr_dacu_do;
2217 
            else
2218 
               pavr_s53_retpcmid8 <= pavr_dacu_do_shadow;
2219 
            end if;
2220 
         end if;
2221 
         if pavr_s53_retpclo8_ld='1' then
2222 
            if pavr_dacu_do_shadow_active='0' then
2223 
               pavr_s54_retpclo8  <= pavr_dacu_do;
2224 
            else
2225 
               pavr_s54_retpclo8  <= pavr_dacu_do_shadow;
2226 
            end if;
2227 
         end if;
2228 
 
2229 
         pavr_s1_pc <= next_pavr_s1_pc;
2230 
 
2231 
         if pavr_stall_bpu='0' then
2232 
            pavr_bpr00        <= next_pavr_bpr0;
2233 
            pavr_bpr00_addr   <= next_pavr_bpr0_addr;
2234 
            pavr_bpr00_active <= next_pavr_bpr0_active;
2235 
            pavr_bpr01        <= pavr_bpr00;
2236 
            pavr_bpr01_addr   <= pavr_bpr00_addr;
2237 
            pavr_bpr01_active <= pavr_bpr00_active;
2238 
            pavr_bpr02        <= pavr_bpr01;
2239 
            pavr_bpr02_addr   <= pavr_bpr01_addr;
2240 
            pavr_bpr02_active <= pavr_bpr01_active;
2241 
            pavr_bpr03        <= pavr_bpr02;
2242 
            pavr_bpr03_addr   <= pavr_bpr02_addr;
2243 
            pavr_bpr03_active <= pavr_bpr02_active;
2244 
 
2245 
            pavr_bpr10           <= next_pavr_bpr1;
2246 
            pavr_bpr10_addr      <= next_pavr_bpr1_addr;
2247 
            pavr_bpr10_active    <= next_pavr_bpr1_active;
2248 
            pavr_bpr11           <= pavr_bpr10;
2249 
            pavr_bpr11_addr      <= pavr_bpr10_addr;
2250 
            pavr_bpr11_active    <= pavr_bpr10_active;
2251 
            pavr_bpr12           <= pavr_bpr11;
2252 
            pavr_bpr12_addr      <= pavr_bpr11_addr;
2253 
            pavr_bpr12_active    <= pavr_bpr11_active;
2254 
            pavr_bpr13           <= pavr_bpr12;
2255 
            pavr_bpr13_addr      <= pavr_bpr12_addr;
2256 
            pavr_bpr13_active    <= pavr_bpr12_active;
2257 
 
2258 
            pavr_bpr20           <= next_pavr_bpr2;
2259 
            pavr_bpr20_addr      <= next_pavr_bpr2_addr;
2260 
            pavr_bpr20_active    <= next_pavr_bpr2_active;
2261 
            pavr_bpr21           <= pavr_bpr20;
2262 
            pavr_bpr21_addr      <= pavr_bpr20_addr;
2263 
            pavr_bpr21_active    <= pavr_bpr20_active;
2264 
            pavr_bpr22           <= pavr_bpr21;
2265 
            pavr_bpr22_addr      <= pavr_bpr21_addr;
2266 
            pavr_bpr22_active    <= pavr_bpr21_active;
2267 
            pavr_bpr23           <= pavr_bpr22;
2268 
            pavr_bpr23_addr      <= pavr_bpr22_addr;
2269 
            pavr_bpr23_active    <= pavr_bpr22_active;
2270 
         end if;
2271 
 
2272 
         pavr_s6_dacudo_sel <= pavr_s5_dacudo_sel;
2273 
 
2274 
         if pavr_syncres='1' then
2275 
            -- Synchronous reset ----------------------------------------------
2276 
 
2277 
            -- RF read port 1-related
2278 
 
2279 
            pavr_s5_op1 <= int_to_std_logic_vector(0, pavr_s5_op1'length);
2280 
 
2281 
            -- RF read port 2-related
2282 
 
2283 
            pavr_s5_op2 <= int_to_std_logic_vector(0, pavr_s5_op2'length);
2284 
 
2285 
            -- RF write port-related
2286 
            pavr_s4_s6_aluoutlo8_rfwr_rq  <= '0';
2287 
            pavr_s5_s6_aluoutlo8_rfwr_rq  <= '0';
2288 
               pavr_s6_aluoutlo8_rfwr_rq  <= '0';
2289 
            pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
2290 
            pavr_s5_s61_aluouthi8_rfwr_rq <= '0';
2291 
            pavr_s6_s61_aluouthi8_rfwr_rq <= '0';
2292 
               pavr_s61_aluouthi8_rfwr_rq <= '0';
2293 
            pavr_s4_s6_iof_rfwr_rq        <= '0';
2294 
            pavr_s5_s6_iof_rfwr_rq        <= '0';
2295 
               pavr_s6_iof_rfwr_rq        <= '0';
2296 
            pavr_s4_s6_dacu_rfwr_rq       <= '0';
2297 
            pavr_s5_s6_dacu_rfwr_rq       <= '0';
2298 
               pavr_s6_dacu_rfwr_rq       <= '0';
2299 
            pavr_s4_s6_pm_rfwr_rq         <= '0';
2300 
            pavr_s5_s6_pm_rfwr_rq         <= '0';
2301 
               pavr_s6_pm_rfwr_rq         <= '0';
2302 
 
2303 
            pavr_s4_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s4_s6_rfwr_addr1'length);
2304 
            pavr_s5_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s5_s6_rfwr_addr1'length);
2305 
               pavr_s6_rfwr_addr1         <= int_to_std_logic_vector(0, pavr_s6_rfwr_addr1'length);
2306 
            pavr_s4_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s4_s61_rfwr_addr2'length);
2307 
            pavr_s5_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s5_s61_rfwr_addr2'length);
2308 
            pavr_s6_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s6_s61_rfwr_addr2'length);
2309 
               pavr_s61_rfwr_addr2        <= int_to_std_logic_vector(0, pavr_s61_rfwr_addr2'length);
2310 
 
2311 
            -- Pointer registers-related
2312 
            pavr_s4_s5_ldstincrampx_xwr_rq   <= '0';
2313 
               pavr_s5_ldstincrampx_xwr_rq   <= '0';
2314 
            pavr_s4_s5_ldstdecrampx_xwr_rq   <= '0';
2315 
               pavr_s5_ldstdecrampx_xwr_rq   <= '0';
2316 
 
2317 
            pavr_s4_s5_ldstincrampy_ywr_rq   <= '0';
2318 
               pavr_s5_ldstincrampy_ywr_rq   <= '0';
2319 
            pavr_s4_s5_ldstdecrampy_ywr_rq   <= '0';
2320 
               pavr_s5_ldstdecrampy_ywr_rq   <= '0';
2321 
 
2322 
            pavr_s4_s5_ldstincrampz_zwr_rq   <= '0';
2323 
               pavr_s5_ldstincrampz_zwr_rq   <= '0';
2324 
            pavr_s4_s5_ldstdecrampz_zwr_rq   <= '0';
2325 
               pavr_s5_ldstdecrampz_zwr_rq   <= '0';
2326 
            pavr_s4_s5_elpmincrampz_zwr_rq   <= '0';
2327 
               pavr_s5_elpmincrampz_zwr_rq   <= '0';
2328 
            pavr_s4_s5_lpminc_zwr_rq         <= '0';
2329 
               pavr_s5_lpminc_zwr_rq         <= '0';
2330 
 
2331 
            -- BPU write, BPR0-related
2332 
            pavr_s4_s5_alu_bpr0wr_rq      <= '0';
2333 
               pavr_s5_alu_bpr0wr_rq      <= '0';
2334 
            pavr_s4_s6_iof_bpr0wr_rq      <= '0';
2335 
            pavr_s5_s6_iof_bpr0wr_rq      <= '0';
2336 
               pavr_s6_iof_bpr0wr_rq      <= '0';
2337 
            pavr_s4_s6_daculd_bpr0wr_rq   <= '0';
2338 
            pavr_s5_s6_daculd_bpr0wr_rq   <= '0';
2339 
               pavr_s6_daculd_bpr0wr_rq   <= '0';
2340 
            pavr_s4_s6_pmdo_bpr0wr_rq     <= '0';
2341 
            pavr_s5_s6_pmdo_bpr0wr_rq     <= '0';
2342 
               pavr_s6_pmdo_bpr0wr_rq     <= '0';
2343 
 
2344 
            pavr_bpr00           <= int_to_std_logic_vector(0, pavr_bpr00'length);
2345 
            pavr_bpr00_addr      <= int_to_std_logic_vector(0, pavr_bpr00_addr'length);
2346 
            pavr_bpr00_active    <= '0';
2347 
            pavr_bpr01           <= int_to_std_logic_vector(0, pavr_bpr01'length);
2348 
            pavr_bpr01_addr      <= int_to_std_logic_vector(0, pavr_bpr01_addr'length);
2349 
            pavr_bpr01_active    <= '0';
2350 
            pavr_bpr02           <= int_to_std_logic_vector(0, pavr_bpr02'length);
2351 
            pavr_bpr02_addr      <= int_to_std_logic_vector(0, pavr_bpr02_addr'length);
2352 
            pavr_bpr02_active    <= '0';
2353 
            pavr_bpr03           <= int_to_std_logic_vector(0, pavr_bpr03'length);
2354 
            pavr_bpr03_addr      <= int_to_std_logic_vector(0, pavr_bpr03_addr'length);
2355 
            pavr_bpr03_active    <= '0';
2356 
 
2357 
            -- BPU write, BPR1-related
2358 
            pavr_s4_s5_dacux_bpr12wr_rq   <= '0';
2359 
               pavr_s5_dacux_bpr12wr_rq   <= '0';
2360 
            pavr_s4_s5_dacuy_bpr12wr_rq   <= '0';
2361 
               pavr_s5_dacuy_bpr12wr_rq   <= '0';
2362 
            pavr_s4_s5_dacuz_bpr12wr_rq   <= '0';
2363 
               pavr_s5_dacuz_bpr12wr_rq   <= '0';
2364 
            pavr_s4_s5_alu_bpr1wr_rq      <= '0';
2365 
               pavr_s5_alu_bpr1wr_rq      <= '0';
2366 
 
2367 
            pavr_bpr10           <= int_to_std_logic_vector(0, pavr_bpr10'length);
2368 
            pavr_bpr10_addr      <= int_to_std_logic_vector(0, pavr_bpr10_addr'length);
2369 
            pavr_bpr10_active    <= '0';
2370 
            pavr_bpr11           <= int_to_std_logic_vector(0, pavr_bpr11'length);
2371 
            pavr_bpr11_addr      <= int_to_std_logic_vector(0, pavr_bpr11_addr'length);
2372 
            pavr_bpr11_active    <= '0';
2373 
            pavr_bpr12           <= int_to_std_logic_vector(0, pavr_bpr12'length);
2374 
            pavr_bpr12_addr      <= int_to_std_logic_vector(0, pavr_bpr12_addr'length);
2375 
            pavr_bpr12_active    <= '0';
2376 
            pavr_bpr13           <= int_to_std_logic_vector(0, pavr_bpr13'length);
2377 
            pavr_bpr13_addr      <= int_to_std_logic_vector(0, pavr_bpr13_addr'length);
2378 
            pavr_bpr13_active    <= '0';
2379 
 
2380 
            -- BPU write, BPR2-related
2381 
 
2382 
            pavr_bpr20           <= int_to_std_logic_vector(0, pavr_bpr20'length);
2383 
            pavr_bpr20_addr      <= int_to_std_logic_vector(0, pavr_bpr20_addr'length);
2384 
            pavr_bpr20_active    <= '0';
2385 
            pavr_bpr21           <= int_to_std_logic_vector(0, pavr_bpr21'length);
2386 
            pavr_bpr21_addr      <= int_to_std_logic_vector(0, pavr_bpr21_addr'length);
2387 
            pavr_bpr21_active    <= '0';
2388 
            pavr_bpr22           <= int_to_std_logic_vector(0, pavr_bpr22'length);
2389 
            pavr_bpr22_addr      <= int_to_std_logic_vector(0, pavr_bpr22_addr'length);
2390 
            pavr_bpr22_active    <= '0';
2391 
            pavr_bpr23           <= int_to_std_logic_vector(0, pavr_bpr23'length);
2392 
            pavr_bpr23_addr      <= int_to_std_logic_vector(0, pavr_bpr23_addr'length);
2393 
            pavr_bpr23_active    <= '0';
2394 
 
2395 
            -- IOF port-related
2396 
            pavr_s4_s5_iof_rq          <= '0';
2397 
               pavr_s5_iof_rq          <= '0';
2398 
            pavr_s4_s6_iof_rq          <= '0';
2399 
            pavr_s5_s6_iof_rq          <= '0';
2400 
               pavr_s6_iof_rq          <= '0';
2401 
 
2402 
            pavr_s4_s5_iof_opcode      <= int_to_std_logic_vector(0, pavr_s4_s5_iof_opcode'length);
2403 
               pavr_s5_iof_opcode      <= int_to_std_logic_vector(0, pavr_s5_iof_opcode'length);
2404 
            pavr_s4_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s4_s6_iof_opcode'length);
2405 
            pavr_s5_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s5_s6_iof_opcode'length);
2406 
               pavr_s6_iof_opcode      <= int_to_std_logic_vector(0, pavr_s6_iof_opcode'length);
2407 
            pavr_s4_s5s6_iof_addr      <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_addr'length);
2408 
                 pavr_s5_iof_addr      <= int_to_std_logic_vector(0, pavr_s5_iof_addr'length);
2409 
                 pavr_s6_iof_addr      <= int_to_std_logic_vector(0, pavr_s6_iof_addr'length);
2410 
            pavr_s4_s5s6_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_bitaddr'length);
2411 
                 pavr_s5_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s5_iof_bitaddr'length);
2412 
                 pavr_s6_iof_bitaddr   <= int_to_std_logic_vector(0, pavr_s6_iof_bitaddr'length);
2413 
 
2414 
            -- SREG-related
2415 
            pavr_s4_s5_alu_sregwr_rq         <= '0';
2416 
               pavr_s5_alu_sregwr_rq         <= '0';
2417 
            pavr_s4_s5_clriflag_sregwr_rq    <= '0';
2418 
               pavr_s5_clriflag_sregwr_rq    <= '0';
2419 
            pavr_s4_s5_setiflag_sregwr_rq    <= '0';
2420 
               pavr_s5_setiflag_sregwr_rq    <= '0';
2421 
 
2422 
            -- SP-related
2423 
            pavr_s4_s5_inc_spwr_rq              <= '0';
2424 
               pavr_s5_inc_spwr_rq              <= '0';
2425 
            pavr_s4_s5_dec_spwr_rq              <= '0';
2426 
               pavr_s5_dec_spwr_rq              <= '0';
2427 
            pavr_s4_s5s51s52_calldec_spwr_rq    <= '0';
2428 
               pavr_s5_calldec_spwr_rq          <= '0';
2429 
               pavr_s51_calldec_spwr_rq         <= '0';
2430 
               pavr_s52_calldec_spwr_rq         <= '0';
2431 
            pavr_s4_s5s51_retinc_spwr_rq        <= '0';
2432 
               pavr_s5_retinc2_spwr_rq          <= '0';
2433 
               pavr_s51_retinc_spwr_rq          <= '0';
2434 
 
2435 
            -- ALU-related
2436 
            pavr_s4_s5_alu_opcode         <= int_to_std_logic_vector(0, pavr_s4_s5_alu_opcode'length);
2437 
               pavr_s5_alu_opcode         <= int_to_std_logic_vector(0, pavr_s5_alu_opcode'length);
2438 
            pavr_s4_s5_alu_op1_hi8_sel    <= '0';
2439 
               pavr_s5_alu_op1_hi8_sel    <= '0';
2440 
            pavr_s4_s5_alu_op2_sel        <= int_to_std_logic_vector(0, pavr_s4_s5_alu_op2_sel'length);
2441 
               pavr_s5_alu_op2_sel        <= int_to_std_logic_vector(0, pavr_s5_alu_op2_sel'length);
2442 
            pavr_s4_s5_op1_addr           <= int_to_std_logic_vector(0, pavr_s4_s5_op1_addr'length);
2443 
               pavr_s5_op1_addr           <= int_to_std_logic_vector(0, pavr_s5_op1_addr'length);
2444 
            pavr_s4_s5_op2_addr           <= int_to_std_logic_vector(0, pavr_s4_s5_op2_addr'length);
2445 
               pavr_s5_op2_addr           <= int_to_std_logic_vector(0, pavr_s5_op2_addr'length);
2446 
            pavr_s4_s5_k8                 <= int_to_std_logic_vector(0, pavr_s4_s5_k8'length);
2447 
               pavr_s5_k8                 <= int_to_std_logic_vector(0, pavr_s5_k8'length);
2448 
            pavr_s6_alu_out               <= int_to_std_logic_vector(0, pavr_s6_alu_out'length);
2449 
            pavr_s61_alu_out_hi8          <= int_to_std_logic_vector(0, pavr_s61_alu_out_hi8'length);
2450 
 
2451 
            -- DACU setup-related
2452 
            pavr_s4_dacu_q       <= int_to_std_logic_vector(0, pavr_s4_dacu_q'length);
2453 
            pavr_s5_rf_dacu_q    <= int_to_std_logic_vector(0, pavr_s5_rf_dacu_q'length);
2454 
            pavr_s5_iof_dacu_q   <= int_to_std_logic_vector(0, pavr_s5_iof_dacu_q'length);
2455 
            pavr_s5_dm_dacu_q    <= int_to_std_logic_vector(0, pavr_s5_dm_dacu_q'length);
2456 
            pavr_s6_dacudo_sel   <= int_to_std_logic_vector(0, pavr_s6_dacudo_sel'length);
2457 
            pavr_s5_k16          <= int_to_std_logic_vector(0, pavr_s5_k16'length);
2458 
 
2459 
            -- DACU read-related
2460 
            pavr_s4_s5_x_dacurd_rq        <= '0';
2461 
               pavr_s5_x_dacurd_rq        <= '0';
2462 
            pavr_s4_s5_y_dacurd_rq        <= '0';
2463 
               pavr_s5_y_dacurd_rq        <= '0';
2464 
            pavr_s4_s5_z_dacurd_rq        <= '0';
2465 
               pavr_s5_z_dacurd_rq        <= '0';
2466 
            pavr_s4_s5_sp_dacurd_rq       <= '0';
2467 
               pavr_s5_sp_dacurd_rq       <= '0';
2468 
            pavr_s4_s5_k16_dacurd_rq      <= '0';
2469 
               pavr_s5_k16_dacurd_rq      <= '0';
2470 
            pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
2471 
               pavr_s5_pchi8_dacurd_rq    <= '0';
2472 
               pavr_s51_pcmid8_dacurd_rq  <= '0';
2473 
               pavr_s52_pclo8_dacurd_rq   <= '0';
2474 
 
2475 
            -- DACU write-related
2476 
            pavr_s4_s5_sp_dacuwr_rq          <= '0';
2477 
               pavr_s5_sp_dacuwr_rq          <= '0';
2478 
            pavr_s4_s5_x_dacuwr_rq           <= '0';
2479 
               pavr_s5_x_dacuwr_rq           <= '0';
2480 
            pavr_s4_s5_y_dacuwr_rq           <= '0';
2481 
               pavr_s5_y_dacuwr_rq           <= '0';
2482 
            pavr_s4_s5_z_dacuwr_rq           <= '0';
2483 
               pavr_s5_z_dacuwr_rq           <= '0';
2484 
            pavr_s4_s5s51s52_pc_dacuwr_rq    <= '0';
2485 
               pavr_s5_pclo8_dacuwr_rq       <= '0';
2486 
               pavr_s51_pcmid8_dacuwr_rq     <= '0';
2487 
               pavr_s52_pchi8_dacuwr_rq      <= '0';
2488 
 
2489 
            -- DM-related
2490 
 
2491 
            -- PM access-related
2492 
            pavr_s4_s5_lpm_pm_rq    <= '0';
2493 
               pavr_s5_lpm_pm_rq    <= '0';
2494 
            pavr_s4_s5_elpm_pm_rq   <= '0';
2495 
               pavr_s5_elpm_pm_rq   <= '0';
2496 
            pavr_s4_z_pm_rq         <= '0';
2497 
            pavr_s4_zeind_pm_rq     <= '0';
2498 
            pavr_s4_k22abs_pm_rq    <= '0';
2499 
            pavr_s4_k12rel_pm_rq    <= '0';
2500 
            pavr_s4_k22int_pm_rq    <= '0';
2501 
            pavr_s4_s54_ret_pm_rq   <= '0';
2502 
            pavr_s5_s54_ret_pm_rq   <= '0';
2503 
            pavr_s51_s54_ret_pm_rq  <= '0';
2504 
            pavr_s52_s54_ret_pm_rq  <= '0';
2505 
            pavr_s53_s54_ret_pm_rq  <= '0';
2506 
                pavr_s54_ret_pm_rq  <= '0';
2507 
 
2508 
            pavr_s4_k6                 <= int_to_std_logic_vector(0, pavr_s4_k6'length);
2509 
            pavr_s4_k12                <= int_to_std_logic_vector(0, pavr_s4_k12'length);
2510 
            pavr_s4_k22int             <= int_to_std_logic_vector(0, pavr_s4_k22int'length);
2511 
            pavr_s2_pc                 <= int_to_std_logic_vector(0, pavr_s2_pc'length);
2512 
            pavr_s3_pc                 <= int_to_std_logic_vector(0, pavr_s3_pc'length);
2513 
            pavr_s4_pc                 <= int_to_std_logic_vector(0, pavr_s4_pc'length);
2514 
            pavr_s5_pc                 <= int_to_std_logic_vector(0, pavr_s5_pc'length);
2515 
            pavr_s51_pc                <= int_to_std_logic_vector(0, pavr_s51_pc'length);
2516 
            pavr_s52_pc                <= int_to_std_logic_vector(0, pavr_s52_pc'length);
2517 
            pavr_s4_pcinc              <= '0';
2518 
            pavr_s4_s51s52s53_retpc_ld <= '0';
2519 
            pavr_s5_s51s52s53_retpc_ld <= '0';
2520 
               pavr_s51_retpchi8_ld    <= '0';
2521 
               pavr_s52_retpcmid8_ld   <= '0';
2522 
               pavr_s53_retpclo8_ld    <= '0';
2523 
            pavr_s52_retpchi8          <= int_to_std_logic_vector(0, pavr_s52_retpchi8'length);
2524 
            pavr_s53_retpcmid8         <= int_to_std_logic_vector(0, pavr_s53_retpcmid8'length);
2525 
            pavr_s54_retpclo8          <= int_to_std_logic_vector(0, pavr_s54_retpclo8'length);
2526 
            pavr_s1_pc                 <= int_to_std_logic_vector(0, pavr_s1_pc'length);              -- Note 1
2527 
            pavr_s2_pmdo_valid         <= '0';
2528 
 
2529 
            pavr_s6_zlsb               <= '0';
2530 
 
2531 
            -- SFU requests-related
2532 
               pavr_s4_stall_rq        <= '0';
2533 
            pavr_s4_s5_stall_rq        <= '0';
2534 
               pavr_s5_stall_rq        <= '0';
2535 
            pavr_s4_s6_stall_rq        <= '0';
2536 
            pavr_s5_s6_stall_rq        <= '0';
2537 
               pavr_s6_stall_rq        <= '0';
2538 
            pavr_s4_flush_s2_rq        <= '0';
2539 
            pavr_s4_ret_flush_s2_rq    <= '0';
2540 
            pavr_s5_ret_flush_s2_rq    <= '0';
2541 
            pavr_s51_ret_flush_s2_rq   <= '0';
2542 
            pavr_s52_ret_flush_s2_rq   <= '0';
2543 
            pavr_s53_ret_flush_s2_rq   <= '0';
2544 
            pavr_s54_ret_flush_s2_rq   <= '0';
2545 
            pavr_s55_ret_flush_s2_rq   <= '0';
2546 
            pavr_s6_skip_rq            <= '0';
2547 
            pavr_s61_skip_rq           <= '0';
2548 
            pavr_s6_branch_rq          <= '0';
2549 
            pavr_s4_nop_rq             <= '0';
2550 
 
2551 
            pavr_s4_s5_skip_cond_sel      <= int_to_std_logic_vector(0, pavr_s4_s5_skip_cond_sel'length);
2552 
               pavr_s5_skip_cond_sel      <= int_to_std_logic_vector(0, pavr_s5_skip_cond_sel'length);
2553 
            pavr_s4_s6_skip_cond_sel      <= '0';
2554 
            pavr_s5_s6_skip_cond_sel      <= '0';
2555 
               pavr_s6_skip_cond_sel      <= '0';
2556 
            pavr_s4_s5_skip_en            <= '0';
2557 
               pavr_s5_skip_en            <= '0';
2558 
            pavr_s4_s6_skip_en            <= '0';
2559 
            pavr_s5_s6_skip_en            <= '0';
2560 
               pavr_s6_skip_en            <= '0';
2561 
            pavr_s4_s5_skip_bitrf_sel     <= int_to_std_logic_vector(0, pavr_s4_s5_skip_bitrf_sel'length);
2562 
               pavr_s5_skip_bitrf_sel     <= int_to_std_logic_vector(0, pavr_s5_skip_bitrf_sel'length);
2563 
            pavr_s4_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s4_s6_skip_bitiof_sel'length);
2564 
            pavr_s5_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s5_s6_skip_bitiof_sel'length);
2565 
               pavr_s6_skip_bitiof_sel    <= int_to_std_logic_vector(0, pavr_s6_skip_bitiof_sel'length);
2566 
 
2567 
            pavr_s4_s5_k7_branch_offset   <= int_to_std_logic_vector(0, pavr_s4_s5_k7_branch_offset'length);
2568 
               pavr_s5_k7_branch_offset   <= int_to_std_logic_vector(0, pavr_s5_k7_branch_offset'length);
2569 
            pavr_s6_branch_pc             <= int_to_std_logic_vector(0, pavr_s6_branch_pc'length);
2570 
            pavr_s4_s5_branch_cond_sel    <= '0';
2571 
               pavr_s5_branch_cond_sel    <= '0';
2572 
            pavr_s4_s5_branch_en          <= '0';
2573 
               pavr_s5_branch_en          <= '0';
2574 
            pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s4_s5_branch_bitsreg_sel'length);
2575 
               pavr_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s5_branch_bitsreg_sel'length);
2576 
 
2577 
            -- Others
2578 
            pavr_nop_ack         <= '0';
2579 
            pavr_s3_instr        <= int_to_std_logic_vector(0, pavr_s3_instr'length);
2580 
            pavr_s4_instr32bits  <= '0';
2581 
            pavr_s4_disable_int  <= '0';
2582 
            pavr_s5_disable_int  <= '0';
2583 
            pavr_s51_disable_int <= '0';
2584 
            pavr_s52_disable_int <= '0';
2585 
 
2586 
         end if;
2587 
      end if;
2588 
   end process control_sync;
2589 
 
2590 
 
2591 
 
2592 
 
2593 
 
2594 
 
2595 
 
2596 
 
2597 
   -- Intruction decoder ------------------------------------------------------
2598 
   instr_decoder:
2599 
   process(pavr_s3_rfrd1_addr,
2600 
           pavr_s3_rfrd2_addr,
2601 
           next_pavr_s4_s6_rfwr_addr1,
2602 
           next_pavr_s4_s61_rfwr_addr2,
2603 
           next_pavr_s4_s5_iof_opcode,
2604 
           next_pavr_s4_s6_iof_opcode,
2605 
           next_pavr_s4_s5s6_iof_addr,
2606 
           next_pavr_s4_s5s6_iof_bitaddr,
2607 
           next_pavr_s4_s5_alu_opcode,
2608 
           next_pavr_s4_s5_alu_op2_sel,
2609 
           next_pavr_s4_s5_k8,
2610 
           next_pavr_s4_dacu_q,
2611 
           next_pavr_s4_k6,
2612 
           next_pavr_s4_k12,
2613 
           next_pavr_s4_k22int,
2614 
           next_pavr_s4_s5_skip_cond_sel,
2615 
           next_pavr_s4_s5_skip_bitrf_sel,
2616 
           next_pavr_s4_s6_skip_bitiof_sel,
2617 
           next_pavr_s4_s5_k7_branch_offset,
2618 
           next_pavr_s4_s5_branch_bitsreg_sel,
2619 
           pavr_int_rq,
2620 
           pavr_stall_s3,
2621 
           pavr_flush_s3,
2622 
           pavr_s4_instr32bits,
2623 
           pavr_s3_instr,
2624 
           next_pavr_s4_dacu_q,
2625 
           pavr_int_vec
2626 
          )
2627 
      variable tmp2_1, tmp2_2, tmp2_3, tmp2_4, tmp2_5, tmp2_6, tmp2_7, tmp2_8, tmp2_9, tmp2_a, tmp2_b, tmp2_c: std_logic_vector(1 downto 0);
2628 
      variable tmp3_1, tmp3_2: std_logic_vector(2 downto 0);
2629 
      variable tmp4_1, tmp4_2, tmp4_3, tmp4_4, tmp4_5 : std_logic_vector(3 downto 0);
2630 
   begin
2631 
      -- Default wires to benign values.
2632 
 
2633 
      -- RF read port 1-related
2634 
      pavr_s3_rfrd1_rq    <= '0';
2635 
      pavr_s3_rfrd1_addr  <= int_to_std_logic_vector(0, pavr_s3_rfrd1_addr'length);
2636 
 
2637 
      -- RF read port 2-related
2638 
      pavr_s3_rfrd2_rq    <= '0';
2639 
      pavr_s3_rfrd2_addr  <= int_to_std_logic_vector(0, pavr_s3_rfrd2_addr'length);
2640 
 
2641 
      -- RF write port-related
2642 
      next_pavr_s4_s6_aluoutlo8_rfwr_rq   <= '0';
2643 
      next_pavr_s4_s61_aluouthi8_rfwr_rq  <= '0';
2644 
      next_pavr_s4_s6_iof_rfwr_rq         <= '0';
2645 
      next_pavr_s4_s6_dacu_rfwr_rq        <= '0';
2646 
      next_pavr_s4_s6_pm_rfwr_rq          <= '0';
2647 
 
2648 
      next_pavr_s4_s6_rfwr_addr1          <= int_to_std_logic_vector(0, next_pavr_s4_s6_rfwr_addr1'length);
2649 
      next_pavr_s4_s61_rfwr_addr2         <= int_to_std_logic_vector(0, next_pavr_s4_s61_rfwr_addr2'length);
2650 
 
2651 
      -- Pointer registers-related
2652 
      next_pavr_s4_s5_ldstincrampx_xwr_rq    <= '0';
2653 
      next_pavr_s4_s5_ldstdecrampx_xwr_rq    <= '0';
2654 
 
2655 
      next_pavr_s4_s5_ldstincrampy_ywr_rq    <= '0';
2656 
      next_pavr_s4_s5_ldstdecrampy_ywr_rq    <= '0';
2657 
 
2658 
      next_pavr_s4_s5_ldstincrampz_zwr_rq    <= '0';
2659 
      next_pavr_s4_s5_ldstdecrampz_zwr_rq    <= '0';
2660 
      next_pavr_s4_s5_elpmincrampz_zwr_rq    <= '0';
2661 
      next_pavr_s4_s5_lpminc_zwr_rq          <= '0';
2662 
 
2663 
      -- BPU write, BPR0-related
2664 
      next_pavr_s4_s5_alu_bpr0wr_rq    <= '0';
2665 
      next_pavr_s4_s6_iof_bpr0wr_rq    <= '0';
2666 
      next_pavr_s4_s6_daculd_bpr0wr_rq <= '0';
2667 
      next_pavr_s4_s6_pmdo_bpr0wr_rq   <= '0';
2668 
 
2669 
      -- BPU write, BPR1-related
2670 
      next_pavr_s4_s5_dacux_bpr12wr_rq <= '0';
2671 
      next_pavr_s4_s5_dacuy_bpr12wr_rq <= '0';
2672 
      next_pavr_s4_s5_dacuz_bpr12wr_rq <= '0';
2673 
      next_pavr_s4_s5_alu_bpr1wr_rq    <= '0';
2674 
 
2675 
      -- IOF port-related
2676 
      next_pavr_s4_s5_iof_rq           <= '0';
2677 
      next_pavr_s4_s6_iof_rq           <= '0';
2678 
 
2679 
      next_pavr_s4_s5_iof_opcode       <= int_to_std_logic_vector(0, next_pavr_s4_s5_iof_opcode'length);
2680 
      next_pavr_s4_s6_iof_opcode       <= int_to_std_logic_vector(0, next_pavr_s4_s6_iof_opcode'length);
2681 
      next_pavr_s4_s5s6_iof_addr       <= int_to_std_logic_vector(0, next_pavr_s4_s5s6_iof_addr'length);
2682 
      next_pavr_s4_s5s6_iof_bitaddr    <= int_to_std_logic_vector(0, next_pavr_s4_s5s6_iof_bitaddr'length);
2683 
 
2684 
      -- SREG-related
2685 
      next_pavr_s4_s5_alu_sregwr_rq       <= '0';
2686 
      next_pavr_s4_s5_clriflag_sregwr_rq  <= '0';
2687 
      next_pavr_s4_s5_setiflag_sregwr_rq  <= '0';
2688 
 
2689 
      -- SP-related
2690 
      next_pavr_s4_s5_inc_spwr_rq            <= '0';
2691 
      next_pavr_s4_s5_dec_spwr_rq            <= '0';
2692 
      next_pavr_s4_s5s51s52_calldec_spwr_rq  <= '0';
2693 
      next_pavr_s4_s5s51_retinc_spwr_rq      <= '0';
2694 
 
2695 
      -- ALU-related
2696 
      next_pavr_s4_s5_alu_opcode       <= int_to_std_logic_vector(0, next_pavr_s4_s5_alu_opcode'length);
2697 
      next_pavr_s4_s5_alu_op1_hi8_sel  <= '0';
2698 
      next_pavr_s4_s5_alu_op2_sel      <= int_to_std_logic_vector(0, next_pavr_s4_s5_alu_op2_sel'length);
2699 
      next_pavr_s4_s5_k8               <= int_to_std_logic_vector(0, next_pavr_s4_s5_k8'length);
2700 
 
2701 
      -- DACU setup-related
2702 
      next_pavr_s4_dacu_q  <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
2703 
 
2704 
      -- DACU read-related
2705 
      next_pavr_s4_s5_x_dacurd_rq         <= '0';
2706 
      next_pavr_s4_s5_y_dacurd_rq         <= '0';
2707 
      next_pavr_s4_s5_z_dacurd_rq         <= '0';
2708 
      next_pavr_s4_s5_sp_dacurd_rq        <= '0';
2709 
      next_pavr_s4_s5_k16_dacurd_rq       <= '0';
2710 
      next_pavr_s4_s5s51s52_pc_dacurd_rq  <= '0';
2711 
 
2712 
      -- DACU write-related
2713 
      next_pavr_s4_s5_sp_dacuwr_rq        <= '0';
2714 
      next_pavr_s4_s5_k16_dacuwr_rq       <= '0';
2715 
      next_pavr_s4_s5_x_dacuwr_rq         <= '0';
2716 
      next_pavr_s4_s5_y_dacuwr_rq         <= '0';
2717 
      next_pavr_s4_s5_z_dacuwr_rq         <= '0';
2718 
      next_pavr_s4_s5s51s52_pc_dacuwr_rq  <= '0';
2719 
 
2720 
      -- DM-related
2721 
 
2722 
      -- PM access-related
2723 
      next_pavr_s4_s5_lpm_pm_rq     <= '0';
2724 
      next_pavr_s4_s5_elpm_pm_rq    <= '0';
2725 
      next_pavr_s4_z_pm_rq          <= '0';
2726 
      next_pavr_s4_zeind_pm_rq      <= '0';
2727 
      next_pavr_s4_k22abs_pm_rq     <= '0';
2728 
      next_pavr_s4_k12rel_pm_rq     <= '0';
2729 
      next_pavr_s4_k22int_pm_rq     <= '0';
2730 
      next_pavr_s4_s54_ret_pm_rq    <= '0';
2731 
 
2732 
      next_pavr_s4_k6                  <= int_to_std_logic_vector(0, next_pavr_s4_k6'length);
2733 
      next_pavr_s4_k12                 <= int_to_std_logic_vector(0, next_pavr_s4_k12'length);
2734 
      next_pavr_s4_k22int              <= int_to_std_logic_vector(0, next_pavr_s4_k22int'length);
2735 
      next_pavr_s4_s51s52s53_retpc_ld  <= '0';
2736 
      next_pavr_s4_pcinc               <= '0';
2737 
 
2738 
      -- SFU requests-related
2739 
      pavr_s3_stall_rq                 <= '0';
2740 
      next_pavr_s4_stall_rq            <= '0';
2741 
      next_pavr_s4_s5_stall_rq         <= '0';
2742 
      next_pavr_s4_s6_stall_rq         <= '0';
2743 
      pavr_s3_flush_s2_rq              <= '0';
2744 
      next_pavr_s4_flush_s2_rq         <= '0';
2745 
      next_pavr_s4_ret_flush_s2_rq     <= '0';
2746 
      next_pavr_s4_nop_rq              <= '0';
2747 
 
2748 
      next_pavr_s4_s5_skip_cond_sel       <= int_to_std_logic_vector(0, next_pavr_s4_s5_skip_cond_sel'length);
2749 
      next_pavr_s4_s6_skip_cond_sel       <= '0';
2750 
      next_pavr_s4_s5_skip_en             <= '0';
2751 
      next_pavr_s4_s6_skip_en             <= '0';
2752 
      next_pavr_s4_s5_skip_bitrf_sel      <= int_to_std_logic_vector(0, next_pavr_s4_s5_skip_bitrf_sel'length);
2753 
      next_pavr_s4_s6_skip_bitiof_sel     <= int_to_std_logic_vector(0, next_pavr_s4_s6_skip_bitiof_sel'length);
2754 
 
2755 
      next_pavr_s4_s5_k7_branch_offset    <= int_to_std_logic_vector(0, next_pavr_s4_s5_k7_branch_offset'length);
2756 
      next_pavr_s4_s5_branch_cond_sel     <= '0';
2757 
      next_pavr_s4_s5_branch_en           <= '0';
2758 
      next_pavr_s4_s5_branch_bitsreg_sel  <= int_to_std_logic_vector(0, next_pavr_s4_s5_branch_bitsreg_sel'length);
2759 
 
2760 
      -- Others
2761 
      next_pavr_s4_disable_int   <= '0';
2762 
      next_pavr_s4_instr32bits   <= '0';
2763 
 
2764 
      tmp2_1 := int_to_std_logic_vector(0, tmp2_1'length);
2765 
      tmp2_2 := int_to_std_logic_vector(0, tmp2_2'length);
2766 
      tmp2_3 := int_to_std_logic_vector(0, tmp2_3'length);
2767 
      tmp2_4 := int_to_std_logic_vector(0, tmp2_4'length);
2768 
      tmp2_5 := int_to_std_logic_vector(0, tmp2_5'length);
2769 
      tmp2_6 := int_to_std_logic_vector(0, tmp2_6'length);
2770 
      tmp2_7 := int_to_std_logic_vector(0, tmp2_7'length);
2771 
      tmp2_8 := int_to_std_logic_vector(0, tmp2_8'length);
2772 
      tmp2_9 := int_to_std_logic_vector(0, tmp2_9'length);
2773 
      tmp2_a := int_to_std_logic_vector(0, tmp2_a'length);
2774 
      tmp2_b := int_to_std_logic_vector(0, tmp2_b'length);
2775 
      tmp2_c := int_to_std_logic_vector(0, tmp2_c'length);
2776 
 
2777 
      tmp3_1 := int_to_std_logic_vector(0, tmp3_1'length);
2778 
      tmp3_2 := int_to_std_logic_vector(0, tmp3_2'length);
2779 
 
2780 
      tmp4_1 := int_to_std_logic_vector(0, tmp4_1'length);
2781 
      tmp4_2 := int_to_std_logic_vector(0, tmp4_2'length);
2782 
      tmp4_3 := int_to_std_logic_vector(0, tmp4_3'length);
2783 
      tmp4_4 := int_to_std_logic_vector(0, tmp4_4'length);
2784 
      tmp4_5 := int_to_std_logic_vector(0, tmp4_5'length);
2785 
 
2786 
      -- Pipeline stage s3
2787 
      -- Instruction decoder
2788 
      if pavr_int_rq='0' then
2789 
         if pavr_stall_s3='0' and pavr_flush_s3='0' and pavr_s4_instr32bits='0' then
2790 
            tmp3_1 := pavr_s3_instr(15 downto 14)&pavr_s3_instr(12);
2791 
            case tmp3_1 is
2792 
               when "000" =>
2793 
                  if pavr_s3_instr(13)='0' then
2794 
                     tmp2_1 := pavr_s3_instr(11 downto 10);
2795 
                     case tmp2_1 is
2796 
                        when "00" =>
2797 
                           tmp2_2 := pavr_s3_instr(9 downto 8);
2798 
                           case tmp2_2 is
2799 
                              when "01" =>
2800 
                                 -- MOVW Rd+1:Rd, Rr+1:Rr (Move word)
2801 
                                 pavr_s3_rfrd1_rq <= '1';                                        -- Request Register File (RF) read port 1 access, for reading operand 1.
2802 
                                 pavr_s3_rfrd2_rq <= '1';                                        -- Request RF read port 2 access, for reading operand 2.
2803 
                                 pavr_s3_rfrd1_addr <= pavr_s3_instr(3 downto 0)&'0';               -- Address of operand 1 in the RF.
2804 
                                 pavr_s3_rfrd2_addr <= pavr_s3_instr(3 downto 0)&'1';               -- Address of operand 2 in the RF.
2805 
                                 next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_op1, next_pavr_s4_s5_alu_opcode'length); -- ALU opcode
2806 
                                 next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_op1bpu; -- Select the high byte of operand 1 from RF - read port 1, via Bypass Unit.
2807 
                                 next_pavr_s4_s5_alu_bpr0wr_rq <= '1';                           -- Request Bypass Unit, bypass register 1 (bpr1) write access.
2808 
                                 next_pavr_s4_s5_alu_bpr1wr_rq <= '1';                           -- Request Bypass Unit, bypass register 2 (bpr2) write access.
2809 
                                 next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(7 downto 4)&'0';    -- Write-back address. 2 successive writes are needed here.
2810 
                                 next_pavr_s4_s61_rfwr_addr2 <= pavr_s3_instr(7 downto 4)&'1';
2811 
                                 next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';                       -- Request RF write port access for writing the result.
2812 
                                 next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
2813 
                                 next_pavr_s4_s6_stall_rq <= '1';                                -- In s6, request pipeline stall and s5 flush, to `steal' RF write access from next instruction.
2814 
                              when "10" =>
2815 
                                 -- MULS Rd, Rr (Multiply unsigned)
2816 
                                 pavr_s3_rfrd1_rq <= '1';
2817 
                                 pavr_s3_rfrd2_rq <= '1';
2818 
                                 pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4);     -- Only registers 16...31 can be used.
2819 
                                 pavr_s3_rfrd2_addr <= '1'&pavr_s3_instr(3 downto 0);
2820 
                                 next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_muls8, next_pavr_s4_s5_alu_opcode'length);
2821 
                                 next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2822 
                                 next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2823 
                                 next_pavr_s4_s5_alu_sregwr_rq <= '1';
2824 
                                 next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2825 
                                 next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
2826 
                                 next_pavr_s4_s6_rfwr_addr1 <= "00000";                -- Write result in R1:R0.
2827 
                                 next_pavr_s4_s61_rfwr_addr2 <= "00001";
2828 
                                 next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2829 
                                 next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
2830 
                                 next_pavr_s4_s6_stall_rq <= '1';
2831 
                              when "11" =>
2832 
                                 tmp2_3 := pavr_s3_instr(7)&pavr_s3_instr(3);
2833 
                                 case tmp2_3 is
2834 
                                    when "00" =>
2835 
                                       -- MULSU Rd, Rr (Multiply signed with unsigned)
2836 
                                       pavr_s3_rfrd1_rq <= '1';
2837 
                                       pavr_s3_rfrd2_rq <= '1';
2838 
                                       pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
2839 
                                       pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
2840 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_mulsu8, next_pavr_s4_s5_alu_opcode'length);
2841 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2842 
                                       next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2843 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
2844 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2845 
                                       next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
2846 
                                       next_pavr_s4_s6_rfwr_addr1 <= "00000";
2847 
                                       next_pavr_s4_s61_rfwr_addr2 <= "00001";
2848 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2849 
                                       next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
2850 
                                       next_pavr_s4_s6_stall_rq <= '1';
2851 
                                    when "01" =>
2852 
                                       -- FMUL Rd, Rr (Fractional multiply unsigned)
2853 
                                       pavr_s3_rfrd1_rq <= '1';
2854 
                                       pavr_s3_rfrd2_rq <= '1';
2855 
                                       pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
2856 
                                       pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
2857 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_fmul8, next_pavr_s4_s5_alu_opcode'length);
2858 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2859 
                                       next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2860 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
2861 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2862 
                                       next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
2863 
                                       next_pavr_s4_s6_rfwr_addr1 <= "00000";
2864 
                                       next_pavr_s4_s61_rfwr_addr2 <= "00001";
2865 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2866 
                                       next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
2867 
                                       next_pavr_s4_s6_stall_rq <= '1';
2868 
                                    when "10" =>
2869 
                                       -- FMULS Rd, Rr (Fractional multiply signed)
2870 
                                       pavr_s3_rfrd1_rq <= '1';
2871 
                                       pavr_s3_rfrd2_rq <= '1';
2872 
                                       pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
2873 
                                       pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
2874 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_fmuls8, next_pavr_s4_s5_alu_opcode'length);
2875 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2876 
                                       next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2877 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
2878 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2879 
                                       next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
2880 
                                       next_pavr_s4_s6_rfwr_addr1 <= "00000";
2881 
                                       next_pavr_s4_s61_rfwr_addr2 <= "00001";
2882 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2883 
                                       next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
2884 
                                       next_pavr_s4_s6_stall_rq <= '1';
2885 
                                    when others =>
2886 
                                       -- FMULSU Rd, Rr (Fractional multiply signed with unsigned)
2887 
                                       pavr_s3_rfrd1_rq <= '1';
2888 
                                       pavr_s3_rfrd2_rq <= '1';
2889 
                                       pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
2890 
                                       pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
2891 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_fmulsu8, next_pavr_s4_s5_alu_opcode'length);
2892 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2893 
                                       next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2894 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
2895 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2896 
                                       next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
2897 
                                       next_pavr_s4_s6_rfwr_addr1 <= "00000";
2898 
                                       next_pavr_s4_s61_rfwr_addr2 <= "00001";
2899 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2900 
                                       next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
2901 
                                       next_pavr_s4_s6_stall_rq <= '1';
2902 
                                 end case;
2903 
                              when others =>
2904 
                                 -- NOP (0000_0000_0000_0000) or invalid opcode (0000_0000_xxxx_xxxx, with xxxx_xxxx != 0000_0000)
2905 
                                 null;
2906 
                           end case;
2907 
                        when "01" =>
2908 
                           -- CPC Rd, Rr (Compare with carry)
2909 
                           pavr_s3_rfrd1_rq <= '1';
2910 
                           pavr_s3_rfrd2_rq <= '1';
2911 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
2912 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2913 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sbc8, next_pavr_s4_s5_alu_opcode'length);
2914 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2915 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2916 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
2917 
                        when "10" =>
2918 
                           -- SBC Rd, Rr (Substract with carry)
2919 
                           pavr_s3_rfrd1_rq <= '1';
2920 
                           pavr_s3_rfrd2_rq <= '1';
2921 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
2922 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2923 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sbc8, next_pavr_s4_s5_alu_opcode'length);
2924 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2925 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2926 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
2927 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2928 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
2929 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2930 
                        when others =>
2931 
                           -- ADD Rd, Rr
2932 
                           pavr_s3_rfrd1_rq <= '1';
2933 
                           pavr_s3_rfrd2_rq <= '1';
2934 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
2935 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2936 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_add8, next_pavr_s4_s5_alu_opcode'length);
2937 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2938 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2939 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
2940 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2941 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
2942 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2943 
                     end case;
2944 
                  else
2945 
                     tmp2_4 := pavr_s3_instr(11 downto 10);
2946 
                     case tmp2_4 is
2947 
                        when "00" =>
2948 
                           -- AND Rd, Rr
2949 
                           pavr_s3_rfrd1_rq <= '1';
2950 
                           pavr_s3_rfrd2_rq <= '1';
2951 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
2952 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2953 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_and8, next_pavr_s4_s5_alu_opcode'length);
2954 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2955 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2956 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
2957 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2958 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
2959 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2960 
                        when "01" =>
2961 
                           -- EOR Rd, Rr (Logical or exclusive)
2962 
                           pavr_s3_rfrd1_rq <= '1';
2963 
                           pavr_s3_rfrd2_rq <= '1';
2964 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
2965 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2966 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_eor8, next_pavr_s4_s5_alu_opcode'length);
2967 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2968 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2969 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
2970 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2971 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
2972 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2973 
                        when "10" =>
2974 
                           -- OR Rd, Rr
2975 
                           pavr_s3_rfrd1_rq <= '1';
2976 
                           pavr_s3_rfrd2_rq <= '1';
2977 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
2978 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2979 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_or8, next_pavr_s4_s5_alu_opcode'length);
2980 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2981 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
2982 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
2983 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2984 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
2985 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2986 
                        when others =>
2987 
                           -- MOV Rd, Rr
2988 
                           pavr_s3_rfrd1_rq <= '1';
2989 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
2990 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_op1, next_pavr_s4_s5_alu_opcode'length);
2991 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
2992 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
2993 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
2994 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
2995 
                     end case;
2996 
                  end if;
2997 
               when "001" =>
2998 
                  if pavr_s3_instr(13)='0' then
2999 
                     tmp2_5 := pavr_s3_instr(11 downto 10);
3000 
                     case tmp2_5 is
3001 
                        when "00" =>
3002 
                           -- CPSE Rd, Rr (Compare and skip if equal)
3003 
                           pavr_s3_rfrd1_rq <= '1';          -- Read two operands from RF, substract them, and use the zero aluout_flag as skip condition to be checked.
3004 
                           pavr_s3_rfrd2_rq <= '1';
3005 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3006 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
3007 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
3008 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3009 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
3010 
                           next_pavr_s4_s5_skip_cond_sel <= pavr_s5_skip_cond_sel_zflag;
3011 
                           next_pavr_s4_s5_skip_en <= '1';      -- Enable skip request in s5. If skip condition true, then: 1) stall (s6) and flush s5, 2) flush s3, 3) if instr32bits then flush s2
3012 
                           pavr_s3_stall_rq <= '1';
3013 
                           --next_pavr_s4_s5_stall_rq <= '1';     -- Request stall in s5. That's to have next two instruction words in s2 and s3, and be able to easely skip (flush) any or both of them.
3014 
                        when "01" =>
3015 
                           -- CP Rd, Rr (Compare)
3016 
                           pavr_s3_rfrd1_rq <= '1';                                     -- Set up the same signals as for CPC.
3017 
                           pavr_s3_rfrd2_rq <= '1';
3018 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3019 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
3020 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
3021 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3022 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
3023 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
3024 
                        when "10" =>
3025 
                           -- SUB Rd, Rr
3026 
                           pavr_s3_rfrd1_rq <= '1';
3027 
                           pavr_s3_rfrd2_rq <= '1';
3028 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3029 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
3030 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
3031 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3032 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
3033 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
3034 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3035 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3036 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3037 
                        when others =>
3038 
                           -- ADC Rd, Rr (Add with carry)
3039 
                           pavr_s3_rfrd1_rq <= '1';
3040 
                           pavr_s3_rfrd2_rq <= '1';
3041 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3042 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
3043 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_adc8, next_pavr_s4_s5_alu_opcode'length);
3044 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3045 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
3046 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
3047 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3048 
                           next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3049 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3050 
                     end case;
3051 
                  else
3052 
                     -- CPI Rd, k8 (Compare with immediate)
3053 
                     pavr_s3_rfrd1_rq <= '1';
3054 
                     pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4);                 -- Only registers 16...31 can be used.
3055 
                     next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
3056 
                     next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3057 
                     next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3058 
                     next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0); -- Load 8 bit constant from instruction opcode.
3059 
                     next_pavr_s4_s5_alu_sregwr_rq <= '1';
3060 
                  end if;
3061 
               when "010" =>
3062 
                  if pavr_s3_instr(13)='0' then
3063 
                     -- SBCI Rd, k8 (Substract immediate with carry)
3064 
                     pavr_s3_rfrd1_rq <= '1';
3065 
                     pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4);                 -- Only registers 16...31 can be used.
3066 
                     next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sbc8, next_pavr_s4_s5_alu_opcode'length);
3067 
                     next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3068 
                     next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3069 
                     next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0); -- Load 8 bit constant from instruction opcode.
3070 
                     next_pavr_s4_s5_alu_sregwr_rq <= '1';
3071 
                     next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3072 
                     next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
3073 
                     next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3074 
                  else
3075 
                     -- ORI Rd, k8 (Logical or with immediate)
3076 
                     pavr_s3_rfrd1_rq <= '1';
3077 
                     pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4);                 -- Only registers 16...31 can be used.
3078 
                     next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_or8, next_pavr_s4_s5_alu_opcode'length);
3079 
                     next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3080 
                     next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3081 
                     next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
3082 
                     next_pavr_s4_s5_alu_sregwr_rq <= '1';
3083 
                     next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3084 
                     next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
3085 
                     next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3086 
                  end if;
3087 
               when "011" =>
3088 
                  if pavr_s3_instr(13)='0' then
3089 
                     -- SUBI Rd, k8 (Substract immediate)
3090 
                     pavr_s3_rfrd1_rq <= '1';
3091 
                     pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4);                 -- Only registers 16...31 can be used.
3092 
                     next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
3093 
                     next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3094 
                     next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3095 
                     next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
3096 
                     next_pavr_s4_s5_alu_sregwr_rq <= '1';
3097 
                     next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3098 
                     next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
3099 
                     next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3100 
                  else
3101 
                     -- ANDI Rd, k8 (Logical or with immediate)
3102 
                     pavr_s3_rfrd1_rq <= '1';
3103 
                     pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4);                 -- Only registers 16...31 can be used.
3104 
                     next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_and8, next_pavr_s4_s5_alu_opcode'length);
3105 
                     next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3106 
                     next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3107 
                     next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
3108 
                     next_pavr_s4_s5_alu_sregwr_rq <= '1';
3109 
                     next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3110 
                     next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
3111 
                     next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3112 
                  end if;
3113 
               when "100" =>
3114 
                  tmp2_6 := pavr_s3_instr(9)&pavr_s3_instr(3);
3115 
                  case tmp2_6 is
3116 
                     when "00" =>
3117 
                        -- LDD Rd, Z+q (Load indirect with displacement, via Z register)
3118 
                        next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0); -- Load DACU displacement constant from instruction opcode.
3119 
                        next_pavr_s4_s5_z_dacurd_rq <= '1';                                                        -- Request DACU read access in s5.
3120 
                        next_pavr_s4_s6_dacu_rfwr_rq <= '1';                       -- Request RF write access.
3121 
                        next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);        -- Write-back address.
3122 
                        next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';                       -- Request BPR0 write access.
3123 
                        next_pavr_s4_s5_stall_rq <= '1';                             -- Stall the pipeline in s5, to `steal' RF read access from s3. A nop will be inserted before the load.
3124 
                     when "01" =>
3125 
                        -- LDD Rd, Y+q (Load indirect with displacement, via Y register)
3126 
                        next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0);
3127 
                        next_pavr_s4_s5_y_dacurd_rq <= '1';
3128 
                        next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3129 
                        next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3130 
                        next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3131 
                        next_pavr_s4_s5_stall_rq <= '1';
3132 
                     when "10" =>
3133 
                        -- STD Z+q, Rr (Store indirect with displacement, via Z register)
3134 
                        pavr_s3_rfrd1_rq <= '1';
3135 
                        pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3136 
                        next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0);
3137 
                        next_pavr_s4_s5_z_dacuwr_rq <= '1';
3138 
                        next_pavr_s4_nop_rq <= '1';
3139 
                     when others =>
3140 
                        -- STD Y+q, Rr (Store indirect with displacement, via Y register)
3141 
                        pavr_s3_rfrd1_rq <= '1';
3142 
                        pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3143 
                        next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0);
3144 
                        next_pavr_s4_s5_y_dacuwr_rq <= '1';
3145 
                        next_pavr_s4_nop_rq <= '1';
3146 
                  end case;
3147 
               when "101" =>
3148 
                  if pavr_s3_instr(13)='0' then
3149 
                     tmp2_7 := pavr_s3_instr(11 downto 10);
3150 
                     case tmp2_7 is
3151 
                        when "11" =>
3152 
                           -- MUL Rd, Rr (Multiply unsigned)
3153 
                           pavr_s3_rfrd1_rq <= '1';
3154 
                           pavr_s3_rfrd2_rq <= '1';
3155 
                           pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3156 
                           pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
3157 
                           next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_mul8, next_pavr_s4_s5_alu_opcode'length);
3158 
                           next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3159 
                           next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
3160 
                           next_pavr_s4_s5_alu_sregwr_rq <= '1';
3161 
                           next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3162 
                           next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
3163 
                           next_pavr_s4_s6_rfwr_addr1 <= "00000";           -- Write result in R1:R0.
3164 
                           next_pavr_s4_s61_rfwr_addr2 <= "00001";
3165 
                           next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3166 
                           next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
3167 
                           next_pavr_s4_s6_stall_rq <= '1';                 -- Request stall in stage 6.
3168 
                        when "10" =>
3169 
                           tmp2_8 := pavr_s3_instr(9 downto 8);
3170 
                           case tmp2_8 is
3171 
                              when "00" =>
3172 
                                 -- CBI A, b (Clear bit in IO register)
3173 
                                 next_pavr_s4_s5_iof_rq <= '1';                            -- Request IO file access in s5.
3174 
                                 next_pavr_s4_s6_iof_rq <= '1';                            -- Request IO file access in s6
3175 
                                 next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;     -- Set IOF opcode in s5 to `read byte'.
3176 
                                 next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_clrbit;     -- Set IOF opcode in s6 to `clear bit'.
3177 
                                 next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3); -- Set IOF address (s5, s6). Only lower 32 bytes of IOF can be used.
3178 
                                 next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0);  -- Set IOF bit address (s6).
3179 
                                 next_pavr_s4_s5_stall_rq <= '1';                          -- Request stall in s5.
3180 
                              when "01" =>
3181 
                                 -- SBIC A, b (Skip if bit in IO register is cleared)
3182 
                                 next_pavr_s4_s5_iof_rq <= '1';                                 -- Request IO file access in s5.
3183 
                                 next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
3184 
                                 next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3);   -- Only lower 32 bytes of IOF can be used.
3185 
                                 next_pavr_s4_s6_skip_bitiof_sel <= pavr_s3_instr(2 downto 0);
3186 
                                 next_pavr_s4_s6_skip_cond_sel <= pavr_s6_skip_cond_sel_notbitiof;
3187 
                                 next_pavr_s4_s6_skip_en <= '1';   -- Enable skip request in s61. If skip condition true, then: 1) stall rq (s61) and flush s6, 2) flush s3, 3) if instr32bits then flush s2
3188 
                                 pavr_s3_stall_rq <= '1';
3189 
                                 next_pavr_s4_s5_stall_rq <= '1';
3190 
                                 --next_pavr_s4_s6_stall_rq <= '1';
3191 
                              when "10" =>
3192 
                                 -- SBI A, b (Set bit in IO register)
3193 
                                 next_pavr_s4_s5_iof_rq <= '1';
3194 
                                 next_pavr_s4_s6_iof_rq <= '1';
3195 
                                 next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
3196 
                                 next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_setbit;
3197 
                                 next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3);
3198 
                                 next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0);
3199 
                                 next_pavr_s4_s5_stall_rq <= '1';
3200 
                              when others =>
3201 
                                 -- SBIS A, b (Skip if bit in IO register is set)
3202 
                                 next_pavr_s4_s5_iof_rq <= '1';                                 -- Request IO file access in s5.
3203 
                                 next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
3204 
                                 next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3);   -- Only lower 32 bytes of IOF can be used.
3205 
                                 next_pavr_s4_s6_skip_bitiof_sel <= pavr_s3_instr(2 downto 0);
3206 
                                 next_pavr_s4_s6_skip_cond_sel <= pavr_s6_skip_cond_sel_bitiof;
3207 
                                 next_pavr_s4_s6_skip_en <= '1';   -- Enable skip request in s61. If skip condition true, then: 1) stall rq (s61) and flush s6, 2) flush s3, 3) if instr32bits then flush s2
3208 
                                 pavr_s3_stall_rq <= '1';
3209 
                                 next_pavr_s4_s5_stall_rq <= '1';
3210 
                                 --next_pavr_s4_s6_stall_rq <= '1';
3211 
                           end case;
3212 
                        when "01" =>
3213 
                           if pavr_s3_instr(9)='1' then
3214 
                              if pavr_s3_instr(8)='0' then
3215 
                                 -- ADIW Rd+1:Rd, k6 (Add immediate to word)
3216 
                                 pavr_s3_rfrd1_rq <= '1';
3217 
                                 pavr_s3_rfrd2_rq <= '1';
3218 
                                 pavr_s3_rfrd1_addr <= "11"&pavr_s3_instr(5 downto 4)&'0';
3219 
                                 pavr_s3_rfrd2_addr <= "11"&pavr_s3_instr(5 downto 4)&'1';
3220 
                                 next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_add16, next_pavr_s4_s5_alu_opcode'length);
3221 
                                 next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_op1bpu;
3222 
                                 next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3223 
                                 next_pavr_s4_s5_k8 <= "00"&pavr_s3_instr(7 downto 6)&pavr_s3_instr(3 downto 0);
3224 
                                 next_pavr_s4_s5_alu_sregwr_rq <= '1';
3225 
                                 next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3226 
                                 next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
3227 
                                 next_pavr_s4_s6_rfwr_addr1 <= "11"&pavr_s3_instr(5 downto 4)&'0';
3228 
                                 next_pavr_s4_s61_rfwr_addr2 <= "11"&pavr_s3_instr(5 downto 4)&'1';
3229 
                                 next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3230 
                                 next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
3231 
                                 next_pavr_s4_s6_stall_rq <= '1';                   -- Request stall in stage 6.
3232 
                              else
3233 
                                 -- SBIW Rd+1:Rd, k6 (Substract immediate from word)
3234 
                                 pavr_s3_rfrd1_rq <= '1';
3235 
                                 pavr_s3_rfrd2_rq <= '1';
3236 
                                 pavr_s3_rfrd1_addr <= "11"&pavr_s3_instr(5 downto 4)&'0';
3237 
                                 pavr_s3_rfrd2_addr <= "11"&pavr_s3_instr(5 downto 4)&'1';
3238 
                                 next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub16, next_pavr_s4_s5_alu_opcode'length);
3239 
                                 next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_op1bpu;
3240 
                                 next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3241 
                                 next_pavr_s4_s5_k8 <= "00"&pavr_s3_instr(7 downto 6)&pavr_s3_instr(3 downto 0);
3242 
                                 next_pavr_s4_s5_alu_sregwr_rq <= '1';
3243 
                                 next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3244 
                                 next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
3245 
                                 next_pavr_s4_s6_rfwr_addr1 <= "11"&pavr_s3_instr(5 downto 4)&'0';
3246 
                                 next_pavr_s4_s61_rfwr_addr2 <= "11"&pavr_s3_instr(5 downto 4)&'1';
3247 
                                 next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3248 
                                 next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
3249 
                                 next_pavr_s4_s6_stall_rq <= '1';
3250 
                              end if;
3251 
                           else
3252 
                              tmp3_2 := pavr_s3_instr(3 downto 1);
3253 
                              case tmp3_2 is
3254 
                                 when "000" =>
3255 
                                    if pavr_s3_instr(0)='0' then
3256 
                                       -- COM Rd (One's complement)
3257 
                                       pavr_s3_rfrd1_rq <= '1';
3258 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3259 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_com8, next_pavr_s4_s5_alu_opcode'length);
3260 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3261 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3262 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3263 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3264 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3265 
                                    else
3266 
                                       -- NEG Rd (Two's complement)
3267 
                                       pavr_s3_rfrd1_rq <= '1';
3268 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3269 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_neg8, next_pavr_s4_s5_alu_opcode'length);
3270 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3271 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3272 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3273 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3274 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3275 
                                    end if;
3276 
                                 when "001" =>
3277 
                                    if pavr_s3_instr(0)='0' then
3278 
                                       -- SWAP Rd (Swap nibbles)
3279 
                                       pavr_s3_rfrd1_rq <= '1';
3280 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3281 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_swap8, next_pavr_s4_s5_alu_opcode'length);
3282 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3283 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3284 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3285 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3286 
                                    else
3287 
                                       -- INC Rd
3288 
                                       pavr_s3_rfrd1_rq <= '1';
3289 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3290 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_inc8, next_pavr_s4_s5_alu_opcode'length);
3291 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3292 
                                       next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_1;
3293 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3294 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3295 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3296 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3297 
                                    end if;
3298 
                                 when "010" =>
3299 
                                    if pavr_s3_instr(0)='0' then
3300 
                                       -- Invalid opcode (1001_010x_xxxx_0100)
3301 
                                       null;
3302 
                                    else
3303 
                                       -- ASR Rd (Arithmetic shift right)
3304 
                                       pavr_s3_rfrd1_rq <= '1';
3305 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3306 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_asr8, next_pavr_s4_s5_alu_opcode'length);
3307 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3308 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3309 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3310 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3311 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3312 
                                    end if;
3313 
                                 when "011" =>
3314 
                                    if pavr_s3_instr(0)='0' then
3315 
                                       -- LSR Rd (Logical shift right)
3316 
                                       pavr_s3_rfrd1_rq <= '1';
3317 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3318 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_lsr8, next_pavr_s4_s5_alu_opcode'length);
3319 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3320 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3321 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3322 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3323 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3324 
                                    else
3325 
                                       -- ROR Rd (Rotate right through carry)
3326 
                                       pavr_s3_rfrd1_rq <= '1';
3327 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3328 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_ror8, next_pavr_s4_s5_alu_opcode'length);
3329 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3330 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3331 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3332 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3333 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3334 
                                    end if;
3335 
                                 when "100" =>
3336 
                                    tmp2_9 := pavr_s3_instr(8)&pavr_s3_instr(0);
3337 
                                    case tmp2_9 is
3338 
                                       when "00" =>
3339 
                                          if pavr_s3_instr(7)='0' then
3340 
                                             -- BSET s (Bit set in SREG (Status Register))
3341 
                                             next_pavr_s4_s5_iof_rq <= '1';                            -- Request IO file access in s5.
3342 
                                             next_pavr_s4_s6_iof_rq <= '1';                            -- Request IO file access in s6
3343 
                                             next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;     -- Set IOF opcode in s5 to `read byte'.
3344 
                                             next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_setbit;     -- Set IOF opcode in s6 to `set bit'.
3345 
                                             next_pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(pavr_sreg_addr, next_pavr_s4_s5s6_iof_addr'length);  -- Set IOF address to SREG's address (s5, s6).
3346 
                                             next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(6 downto 4);  -- Set IOF bit address (s6).
3347 
                                             next_pavr_s4_s5_stall_rq <= '1';                          -- Request stall in s5.
3348 
                                          else
3349 
                                             -- BCLR s (Bit clear in SREG)
3350 
                                             next_pavr_s4_s5_iof_rq <= '1';
3351 
                                             next_pavr_s4_s6_iof_rq <= '1';
3352 
                                             next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
3353 
                                             next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_clrbit;
3354 
                                             next_pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(pavr_sreg_addr, next_pavr_s4_s5s6_iof_addr'length);
3355 
                                             next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(6 downto 4);
3356 
                                             next_pavr_s4_s5_stall_rq <= '1';
3357 
                                          end if;
3358 
                                       when "01" =>
3359 
                                          tmp4_1 := pavr_s3_instr(7 downto 4);
3360 
                                          case tmp4_1 is
3361 
                                             when "0000" =>
3362 
                                                -- IJMP (Indirect jump (16 bit absolute address), via Z register)
3363 
                                                next_pavr_s4_z_pm_rq <= '1';           -- Request PM access. Also, update PC. Next PC will be the present Z register.
3364 
                                                pavr_s3_flush_s2_rq <= '1';            -- Request flush s2 during s3 (next instruction is out of normal instruction flow).
3365 
                                                next_pavr_s4_flush_s2_rq <= '1';       -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
3366 
                                                next_pavr_s4_nop_rq <= '1';            -- Insert a nop *after* the instruction wavefront.
3367 
                                             when "0001" =>
3368 
                                                -- EIJMP (Extended indirect jump (24 bit absolute address), via Z and EIND registers)
3369 
                                                next_pavr_s4_zeind_pm_rq <= '1';       -- Request PM access. Also, update PC. Next PC will be the present Z:EIND registers.
3370 
                                                pavr_s3_flush_s2_rq <= '1';            -- Request flush s2 during s3 (next instruction is out of normal instruction flow).
3371 
                                                next_pavr_s4_flush_s2_rq <= '1';       -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
3372 
                                                next_pavr_s4_nop_rq <= '1';            -- Insert a nop *after* the instruction wavefront.
3373 
                                             when others =>
3374 
                                                -- Invalid opcode (1001_0100_xxxx_1001, with xxxx != 0000, 0001)
3375 
                                                null;
3376 
                                          end case;
3377 
                                       when "10" =>
3378 
                                          tmp4_2 := pavr_s3_instr(7 downto 4);
3379 
                                          case tmp4_2 is
3380 
                                             when "0000" =>
3381 
                                                -- RET (Return from subroutine)
3382 
                                                next_pavr_s4_s51s52s53_retpc_ld <= '1';       -- Load return PC from stack in stages s51, s52 and s53.
3383 
                                                next_pavr_s4_s5s51s52_pc_dacurd_rq <= '1';    -- Request DACU read for reading PC from stack, in stages s5, s51 and s52.
3384 
                                                next_pavr_s4_s54_ret_pm_rq <= '1';            -- Request PM access. Also, update PC.
3385 
                                                next_pavr_s4_dacu_q <= int_to_std_logic_vector(1, next_pavr_s4_dacu_q'length); -- Simulate pre-increment SP with a `1' initial displacement and post-increment.
3386 
                                                next_pavr_s4_s5s51_retinc_spwr_rq <= '1';     -- Request SP write access. SP will be (post-) incremented.
3387 
                                                pavr_s3_flush_s2_rq <= '1';             -- Request flush s2 in s3.
3388 
                                                next_pavr_s4_ret_flush_s2_rq <= '1';    -- Many, many flushes here (7 flushes; they shift from one stage into another, from s4 till s55).
3389 
                                                --next_pavr_s4_stall_rq <= '1';
3390 
                                             when "0001" =>
3391 
                                                -- RETI (Return from interrupt)
3392 
                                                next_pavr_s4_s51s52s53_retpc_ld <= '1';
3393 
                                                next_pavr_s4_s5s51s52_pc_dacurd_rq <= '1';
3394 
                                                next_pavr_s4_s54_ret_pm_rq <= '1';
3395 
                                                next_pavr_s4_s5_setiflag_sregwr_rq <= '1';    -- Request SREG write access, to set I (global interrupt enable) flag.
3396 
                                                next_pavr_s4_dacu_q <= int_to_std_logic_vector(1, next_pavr_s4_dacu_q'length);
3397 
                                                next_pavr_s4_s5s51_retinc_spwr_rq <= '1';
3398 
                                                pavr_s3_flush_s2_rq <= '1';
3399 
                                                next_pavr_s4_ret_flush_s2_rq <= '1';
3400 
                                                --next_pavr_s4_stall_rq <= '1';
3401 
                                             when "1000" =>
3402 
                                                -- SLEEP (Low power mode, not implemented)
3403 
                                                null;
3404 
                                             when "1001" =>
3405 
                                                -- BREAK (not implemented)
3406 
                                                null;
3407 
                                             when "1010" =>
3408 
                                                -- WDR (Reset watchdog timer, not implemented)
3409 
                                                null;
3410 
                                             when "1100" =>
3411 
                                                -- LPM (Load indirect Program Memory into R0, via Z register)
3412 
                                                next_pavr_s4_s5_lpm_pm_rq <= '1';         -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z register.
3413 
                                                next_pavr_s4_s6_pm_rfwr_rq <= '1';      -- Request RF write access. Write PM data out into the RF.
3414 
                                                next_pavr_s4_s6_rfwr_addr1 <= "00000";    -- Write-back address.
3415 
                                                next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1';    -- Request BPU write access.
3416 
                                                next_pavr_s4_s5_stall_rq <= '1';
3417 
                                             when "1101" =>
3418 
                                                -- ELPM (Load extended Program Memory into R0, via Z and RAMPZ registers)
3419 
                                                next_pavr_s4_s5_elpm_pm_rq <= '1';        -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z and RAMPZ registers.
3420 
                                                next_pavr_s4_s6_pm_rfwr_rq <= '1';      -- Request RF write access. Write PM data out into the RF.
3421 
                                                next_pavr_s4_s6_rfwr_addr1 <= "00000";    -- Write-back address.
3422 
                                                next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1';    -- Request BPU write access.
3423 
                                                next_pavr_s4_s5_stall_rq <= '1';
3424 
                                             when "1110" =>
3425 
                                                -- SPM (Store Program Memory, not implemented)
3426 
                                                null;
3427 
                                             when others =>
3428 
                                                -- Invalid opcode (1001_0101_xxxx_1000, with xxxx != 0000, 0001, 1000, 1001, 1010, 1100, 1101, 1110)
3429 
                                                null;
3430 
                                          end case;
3431 
                                       when others =>
3432 
                                          tmp4_3 := pavr_s3_instr(7 downto 4);
3433 
                                          case tmp4_3 is
3434 
                                             when "0000" =>
3435 
                                                -- ICALL (Indirect call (16 bit absolute address), via Z register)
3436 
                                                pavr_s3_flush_s2_rq <= '1';                   -- Flush the instructions that were already fetched but don't follow the normal instruction flow.
3437 
                                                next_pavr_s4_flush_s2_rq <= '1';
3438 
                                                next_pavr_s4_nop_rq <= '1';                   -- Insert a nop *after* the instruction wavefront.
3439 
                                                next_pavr_s4_z_pm_rq <= '1';                  -- Request PM access. Also, update PC.
3440 
                                                next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1';    -- Request DACU write access in s5, s51 and s52.
3441 
                                                next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
3442 
                                                --next_pavr_s4_stall_rq <= '1';
3443 
                                             when "0001" =>
3444 
                                                -- EICALL (Extended indirect call (24 bit absolute address), via Z and EIND registers)
3445 
                                                pavr_s3_flush_s2_rq <= '1';                   -- Flush the instructions that were already fetched but don't follow the normal instruction flow.
3446 
                                                next_pavr_s4_flush_s2_rq <= '1';
3447 
                                                next_pavr_s4_nop_rq <= '1';                   -- Insert a nop *after* the instruction wavefront.
3448 
                                                next_pavr_s4_zeind_pm_rq <= '1';              -- Request PM access. Also, update PC.
3449 
                                                next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1';    -- Request DACU write access in s5, s51 and s52.
3450 
                                                next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
3451 
                                                --next_pavr_s4_stall_rq <= '1';
3452 
                                             when others =>
3453 
                                                -- Invalid opcode (1001_0101_xxxx_1001, with xxxx != 0000, 0001)
3454 
                                                null;
3455 
                                          end case;
3456 
                                    end case;
3457 
                                 when "101" =>
3458 
                                    if pavr_s3_instr(0)='0' then
3459 
                                       -- DEC Rd
3460 
                                       pavr_s3_rfrd1_rq <= '1';
3461 
                                       pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3462 
                                       next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_dec8, next_pavr_s4_s5_alu_opcode'length);
3463 
                                       next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
3464 
                                       next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_minus1;
3465 
                                       next_pavr_s4_s5_alu_sregwr_rq <= '1';
3466 
                                       next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3467 
                                       next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3468 
                                       next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3469 
                                    else
3470 
                                       -- Invalid opcode (1001_010x_xxxx_1011)
3471 
                                       null;
3472 
                                    end if;
3473 
                                 when "110" =>
3474 
                                    -- JMP k16 (Long jump (22 bit absolute address); 32 bit instruction)
3475 
                                    next_pavr_s4_instr32bits <= '1';                          -- Signalize 32 bit instruction
3476 
                                    next_pavr_s4_k6 <= pavr_s3_instr(8 downto 4)&pavr_s3_instr(0);  -- Load lower 6 bits of the absolute jump address from instruction opcode.
3477 
                                    next_pavr_s4_k22abs_pm_rq <= '1';         -- Request PM access. (***) Attention, this also updates the PC.
3478 
                                    next_pavr_s4_flush_s2_rq <= '1';          -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
3479 
                                 when others =>
3480 
                                    -- CALL k16 (Long call (22 bit absolute address); 32 bit instruction)
3481 
                                    next_pavr_s4_instr32bits <= '1';              -- Signalize 32 bit instruction
3482 
                                    next_pavr_s4_pcinc <= '1';                    -- Increment return address to take into account that CALL has 32 bits.
3483 
                                    next_pavr_s4_flush_s2_rq <= '1';
3484 
                                    next_pavr_s4_nop_rq <= '1';                   -- Insert a nop *after* the instruction wavefront.
3485 
                                    next_pavr_s4_k22abs_pm_rq <= '1';             -- Request PM access. Also, update PC.
3486 
                                    next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1';    -- Request DACU write access in s5, s51 and s52.
3487 
                                    next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
3488 
                                    --next_pavr_s4_stall_rq <= '1';
3489 
                              end case;
3490 
                           end if;
3491 
                        when others =>
3492 
                           if pavr_s3_instr(9)='0' then
3493 
                              tmp4_4 := pavr_s3_instr(3 downto 0);
3494 
                              case tmp4_4 is
3495 
                                 when "1111" =>
3496 
                                    -- POP Rd
3497 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(1, next_pavr_s4_dacu_q'length); -- Simulate pre-increment with a `1' initial displacement and post-increment.
3498 
                                    next_pavr_s4_s5_sp_dacurd_rq <= '1';                                           -- Request DACU read access. Read UM via SP.
3499 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3500 
                                    next_pavr_s4_s5_inc_spwr_rq <= '1';                                            -- Request SP write access. SP will be (post-)incremented.
3501 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3502 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3503 
                                    next_pavr_s4_s5_stall_rq <= '1';
3504 
                                 when "0000" =>
3505 
                                    -- LDS Rd, k16 (Load direct from data space; 32 bit instruction)
3506 
                                    next_pavr_s4_instr32bits <= '1';        -- Signalize that this instruction is 32 bits wide. Next word (16 bits) will be ignored by the instruction decoder (nop). It's a constant that will be extracted by s5.
3507 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3508 
                                    next_pavr_s4_s5_k16_dacurd_rq <= '1';                        -- Request DACU read access. Read from dedicated 16 bit instruction constant register (s4).
3509 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';                       -- Request RF write access.
3510 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);     -- Write-back address.
3511 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';                       -- Request Bypass Unit (BPU) write access in s6.
3512 
                                    next_pavr_s4_s5_stall_rq <= '1';                             -- Stall the pipeline in s5, to `steal' RF read access from s3. A nop will be inserted after the load.
3513 
                                 when "1100" =>
3514 
                                    -- LD Rd, X (Load indirect via X register)
3515 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length); -- Load Data Address Calculation Unit (DACU) displacement constant (q).
3516 
                                    next_pavr_s4_s5_x_dacurd_rq <= '1';                          -- Request DACU read access in s5. Indirectly read Unified Memory (UM) via X register.
3517 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';                       -- Request RF write access.
3518 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);     -- Write-back address.
3519 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';                       -- Request Bypass Unit (BPU) write access in s6.
3520 
                                    next_pavr_s4_s5_stall_rq <= '1';                             -- Stall the pipeline in s5, to `steal' RF read access from s3. A nop will be inserted after the load.
3521 
                                 when "1101" =>
3522 
                                    -- LD Rd, X+ (Load indirect with post-increment via X register)
3523 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3524 
                                    next_pavr_s4_s5_x_dacurd_rq <= '1';
3525 
                                    next_pavr_s4_s5_ldstincrampx_xwr_rq <= '1';                                     -- Request X pointer write access. The X pointer will be (post-)incremented.
3526 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3527 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3528 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3529 
                                    next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
3530 
                                    next_pavr_s4_s5_stall_rq <= '1';
3531 
                                 when "1110" =>
3532 
                                    -- LD Rd, -X (Load indirect with pre-decrement via X register)
3533 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);   -- Simulate pre-decrement with a `-1' initial displacement and post-decrement.
3534 
                                    next_pavr_s4_s5_x_dacurd_rq <= '1';
3535 
                                    next_pavr_s4_s5_ldstdecrampx_xwr_rq <= '1';                                           -- Request X pointer write access. The X pointer will be (post-)decremented.
3536 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3537 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3538 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3539 
                                    next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
3540 
                                    next_pavr_s4_s5_stall_rq <= '1';
3541 
                                 when "1001" =>
3542 
                                    -- LD Rd, Y+ (Load indirect with post-increment via Y register)
3543 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3544 
                                    next_pavr_s4_s5_y_dacurd_rq <= '1';
3545 
                                    next_pavr_s4_s5_ldstincrampy_ywr_rq <= '1';                                     -- Request Y pointer write access. The Y pointer will be (post-)incremented.
3546 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3547 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3548 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3549 
                                    next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
3550 
                                    next_pavr_s4_s5_stall_rq <= '1';
3551 
                                 when "1010" =>
3552 
                                    -- LD Rd, -Y (Load indirect with pre-decrement via Y register)
3553 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);   -- Simulate pre-decrement with a `-1' initial displacement and post-decrement.
3554 
                                    next_pavr_s4_s5_y_dacurd_rq <= '1';
3555 
                                    next_pavr_s4_s5_ldstdecrampy_ywr_rq <= '1';                                           -- Request Y pointer write access. The Y pointer will be (post-)decremented.
3556 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3557 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3558 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3559 
                                    next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
3560 
                                    next_pavr_s4_s5_stall_rq <= '1';
3561 
                                 when "0001" =>
3562 
                                    -- LD Rd, Z+ (Load indirect with post-decrement via Z register)
3563 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3564 
                                    next_pavr_s4_s5_z_dacurd_rq <= '1';
3565 
                                    next_pavr_s4_s5_ldstincrampz_zwr_rq <= '1';                                       -- Request Z pointer write access. The Z pointer will be (post-)incremented.
3566 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3567 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3568 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3569 
                                    next_pavr_s4_s5_dacuz_bpr12wr_rq <='1';
3570 
                                    next_pavr_s4_s5_stall_rq <= '1';
3571 
                                 when "0010" =>
3572 
                                    -- LD Rd, -Z (Load indirect with pre-decrement via Z register)
3573 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);   -- Simulate pre-decrement with a `-1' initial displacement and post-decrement.
3574 
                                    next_pavr_s4_s5_z_dacurd_rq <= '1';
3575 
                                    next_pavr_s4_s5_ldstdecrampz_zwr_rq <= '1';                                           -- Request Z pointer write access. The Z pointer will be (post-)decremented.
3576 
                                    next_pavr_s4_s6_dacu_rfwr_rq <= '1';
3577 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3578 
                                    next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
3579 
                                    next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
3580 
                                    next_pavr_s4_s5_stall_rq <= '1';
3581 
                                 when "0100" =>
3582 
                                    -- LPM Rd, Z (Load indirect Program Memory)
3583 
                                    next_pavr_s4_s5_lpm_pm_rq <= '1';                     -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z register.
3584 
                                    next_pavr_s4_s6_pm_rfwr_rq <= '1';                  -- Request RF write access. Write PM data out into the RF.
3585 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);  -- Write-back address.
3586 
                                    next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1';                -- Request BPU write access.
3587 
                                    next_pavr_s4_s5_stall_rq <= '1';
3588 
                                 when "0101" =>
3589 
                                    -- LPM Rd, Z+ (Load indirect Program Memory with post-increment)
3590 
                                    next_pavr_s4_s5_lpm_pm_rq <= '1';                     -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z register.
3591 
                                    next_pavr_s4_s5_lpminc_zwr_rq <= '1';                    -- Request Z pointer write access. Z will be (post-)incremented.
3592 
                                    next_pavr_s4_s6_pm_rfwr_rq <= '1';                  -- Request RF write access. Write PM data out into the RF.
3593 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);  -- Write-back address.
3594 
                                    next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1';                -- Request BPU write access.
3595 
                                    next_pavr_s4_s5_stall_rq <= '1';
3596 
                                 when "0110" =>
3597 
                                    -- ELPM Rd, Z (Load extended indirect Program Memory)
3598 
                                    next_pavr_s4_s5_elpm_pm_rq <= '1';                    -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z and RAMPZ registers.
3599 
                                    next_pavr_s4_s6_pm_rfwr_rq <= '1';                  -- Request RF write access. Write PM data out into the RF.
3600 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);  -- Write-back address.
3601 
                                    next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1';                -- Request BPU write access.
3602 
                                    next_pavr_s4_s5_stall_rq <= '1';
3603 
                                 when "0111" =>
3604 
                                    -- ELPM Rd, Z+ (Load extended indirect Program Memory with post-increment)
3605 
                                    next_pavr_s4_s5_elpm_pm_rq <= '1';                    -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z and RAMPZ registers.
3606 
                                    next_pavr_s4_s5_elpmincrampz_zwr_rq <= '1';               -- Request Z pointer write access. RAMPZ:Z will be (post-)incremented.
3607 
                                    next_pavr_s4_s6_pm_rfwr_rq <= '1';                  -- Request RF write access. Write PM data out into the RF.
3608 
                                    next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);  -- Write-back address.
3609 
                                    next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1';                -- Request BPU write access.
3610 
                                    next_pavr_s4_s5_stall_rq <= '1';
3611 
                                 when others =>
3612 
                                    -- Invalid opcode (1001_000x_xxxx_yyyy, with yyyy = 0011, 1000, 1011)
3613 
                                    null;
3614 
                              end case;
3615 
                           else
3616 
                              tmp4_5 := pavr_s3_instr(3 downto 0);
3617 
                              case tmp4_5 is
3618 
                                 when "1111" =>
3619 
                                    -- PUSH Rr
3620 
                                    pavr_s3_rfrd1_rq <= '1';
3621 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3622 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3623 
                                    next_pavr_s4_s5_sp_dacuwr_rq <= '1';                -- Request DACU write access, at address given by Stack Pointer (SP).
3624 
                                    next_pavr_s4_s5_dec_spwr_rq <= '1';                 -- Request SP write access. SP will be (post-)decremented.
3625 
                                    next_pavr_s4_s5_stall_rq <= '1';                    -- Request stall in s5.
3626 
                                    next_pavr_s4_nop_rq <= '1';                         -- Request nop after the instrction wavefront.
3627 
                                 when "0000" =>
3628 
                                    -- STS k16, Rr (Store direct to data space; 32 bit instruction)
3629 
                                    next_pavr_s4_instr32bits <= '1';                    -- Signalize 32 bit instruction.
3630 
                                    pavr_s3_rfrd1_rq <= '1';                            -- Request RF read port 1 access.
3631 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);       -- Address of RF operand to be read.
3632 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3633 
                                    next_pavr_s4_s5_k16_dacuwr_rq <= '1';               -- Request DACU write access. Write UM at address given by 16 bit instruction constant (pavr_s5_k16).
3634 
                                    next_pavr_s4_nop_rq <= '1';                        -- Request a nop *after* the instruction wavefront. Do that for the store to wait its turn for RF write port access.
3635 
                                 when "1100" =>
3636 
                                    -- ST X, Rr (Store indirect via X register)
3637 
                                    pavr_s3_rfrd1_rq <= '1';                            -- Request RF read port 1 access.
3638 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);       -- Address of RF operand to be read.
3639 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3640 
                                    next_pavr_s4_s5_x_dacuwr_rq <= '1';
3641 
                                    next_pavr_s4_nop_rq <= '1';          -- Request a nop *after* the instruction wavefront. Do that for the store to wait its turn for RF write port access.
3642 
                                 when "1101" =>
3643 
                                    -- ST X+, Rr (Store indirect with post-increment via X register)
3644 
                                    pavr_s3_rfrd1_rq <= '1';
3645 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3646 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3647 
                                    next_pavr_s4_s5_x_dacuwr_rq <= '1';
3648 
                                    next_pavr_s4_s5_ldstincrampx_xwr_rq <= '1';   -- Request X pointer write access. The X pointer will be (post-)incremented.
3649 
                                    next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
3650 
                                    next_pavr_s4_nop_rq <= '1';
3651 
                                 when "1110" =>
3652 
                                    -- ST -X, Rr (Store indirect with pre-decrement via X register)
3653 
                                    pavr_s3_rfrd1_rq <= '1';
3654 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3655 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);
3656 
                                    next_pavr_s4_s5_x_dacuwr_rq <= '1';
3657 
                                    next_pavr_s4_s5_ldstdecrampx_xwr_rq <= '1';   -- Request X pointer write access. The X pointer will be (post-)decremented.
3658 
                                    next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
3659 
                                    next_pavr_s4_nop_rq <= '1';
3660 
                                 when "1001" =>
3661 
                                    -- ST Y+, Rr (Store indirect with post-increment via Y register)
3662 
                                    pavr_s3_rfrd1_rq <= '1';
3663 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3664 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3665 
                                    next_pavr_s4_s5_y_dacuwr_rq <= '1';
3666 
                                    next_pavr_s4_s5_ldstincrampy_ywr_rq <= '1';   -- Request Y pointer write access. The Y pointer will be (post-)incremented.
3667 
                                    next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
3668 
                                    next_pavr_s4_nop_rq <= '1';
3669 
                                 when "1010" =>
3670 
                                    -- ST -Y, Rr (Store indirect with pre-decrement via Y register)
3671 
                                    pavr_s3_rfrd1_rq <= '1';
3672 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3673 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);
3674 
                                    next_pavr_s4_s5_y_dacuwr_rq <= '1';
3675 
                                    next_pavr_s4_s5_ldstdecrampy_ywr_rq <= '1';   -- Request Y pointer write access. The Y pointer will be (post-)decremented.
3676 
                                    next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
3677 
                                    next_pavr_s4_nop_rq <= '1';
3678 
                                 when "0001" =>
3679 
                                    -- ST Z+, Rr (Store indirect with post-increment via Z register)
3680 
                                    pavr_s3_rfrd1_rq <= '1';
3681 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3682 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
3683 
                                    next_pavr_s4_s5_z_dacuwr_rq <= '1';
3684 
                                    next_pavr_s4_s5_ldstincrampz_zwr_rq <= '1';   -- Request Z pointer write access. The Z pointer will be (post-)incremented.
3685 
                                    next_pavr_s4_s5_dacuz_bpr12wr_rq <='1';
3686 
                                    next_pavr_s4_nop_rq <= '1';
3687 
                                 when "0010" =>
3688 
                                    -- ST -Z, Rr (Store indirect with pre-decrement via Z register)
3689 
                                    pavr_s3_rfrd1_rq <= '1';
3690 
                                    pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3691 
                                    next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);
3692 
                                    next_pavr_s4_s5_z_dacuwr_rq <= '1';
3693 
                                    next_pavr_s4_s5_ldstdecrampz_zwr_rq <= '1';   -- Request Z pointer write access. The Z pointer will be (post-)decremented.
3694 
                                    next_pavr_s4_s5_dacuz_bpr12wr_rq <='1';
3695 
                                    next_pavr_s4_nop_rq <= '1';
3696 
                                 when others =>
3697 
                                    -- Invalid opcode (1001_001x_xxxx_yyyy, with yyyy = 0011, 0100, 0101, 0110, 0111, 1000, 1110)
3698 
                                    null;
3699 
                              end case;
3700 
                           end if;
3701 
                     end case;
3702 
                  else
3703 
                     if pavr_s3_instr(11)='0' then
3704 
                        -- IN Rd, A (Load IO location to register)
3705 
                        next_pavr_s4_s5_iof_rq <= '1';
3706 
                        next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
3707 
                        next_pavr_s4_s5s6_iof_addr <= pavr_s3_instr(10 downto 9)&pavr_s3_instr(3 downto 0);
3708 
                        next_pavr_s4_s6_iof_bpr0wr_rq <= '1';
3709 
                        next_pavr_s4_s6_iof_rfwr_rq <= '1';
3710 
                        next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
3711 
                        next_pavr_s4_s5_stall_rq <= '1';                -- Steal BPU0 write access from next instruction.
3712 
                     else
3713 
                        -- OUT A, Rr (Store register into IO location)
3714 
                        pavr_s3_rfrd1_rq <= '1';
3715 
                        pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3716 
                        next_pavr_s4_s5_iof_rq <= '1';
3717 
                        next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_wrbyte;
3718 
                        next_pavr_s4_s5s6_iof_addr <= pavr_s3_instr(10 downto 9)&pavr_s3_instr(3 downto 0);
3719 
                     end if;
3720 
                  end if;
3721 
               when "110" =>
3722 
                  if pavr_s3_instr(13)='0' then
3723 
                     -- RJMP k12 (Relative jump (12 bit relative address))
3724 
                     next_pavr_s4_k12 <= pavr_s3_instr(11 downto 0);    -- Load 12 bit relative jump address from instruction opcode.
3725 
                     next_pavr_s4_k12rel_pm_rq <= '1';                  -- Request PM access.
3726 
                     pavr_s3_flush_s2_rq <= '1';                        -- Request flush s2 during s3 (next instruction is out of normal instruction flow).
3727 
                     next_pavr_s4_flush_s2_rq <= '1';                   -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
3728 
                  else
3729 
                     -- LDI k8 (Load immediate)
3730 
                     next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_op2, next_pavr_s4_s5_alu_opcode'length);
3731 
                     next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
3732 
                     next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
3733 
                     next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
3734 
                     next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
3735 
                     next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);   -- Only the higher 16 registers can be immediately loaded.
3736 
                  end if;
3737 
               when others =>
3738 
                  if pavr_s3_instr(13)='0' then
3739 
                     -- RCALL (Relative call (12 bit relative address))
3740 
                     next_pavr_s4_k12 <= pavr_s3_instr(11 downto 0); -- Load 12 bit relative jump address from instruction opcode.
3741 
                     pavr_s3_flush_s2_rq <= '1';                     -- Flush the instructions that were already fetched but don't follow the normal instruction flow.
3742 
                     next_pavr_s4_flush_s2_rq <= '1';
3743 
                     next_pavr_s4_nop_rq <= '1';                     -- Insert a nop *after* the instruction wavefront.
3744 
                     next_pavr_s4_k12rel_pm_rq <= '1';               -- Request PM access. Also, update PC.
3745 
                     next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1';      -- Request DACU write access in s5, s51 and s52.
3746 
                     next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1';   -- Decrement SP.
3747 
                     --next_pavr_s4_stall_rq <= '1';
3748 
                  else
3749 
                     tmp2_a := pavr_s3_instr(11 downto 10);
3750 
                     case tmp2_a is
3751 
                        when "00" =>
3752 
                           -- BRBS s, k7 (Branch if bit in SREG is set (7 bit relative address))
3753 
                           next_pavr_s4_s5_k7_branch_offset <= pavr_s3_instr(9 downto 3);       -- 7 bit relative jump address
3754 
                           next_pavr_s4_pcinc <= '1';
3755 
                           next_pavr_s4_s5_branch_cond_sel <= pavr_s5_branch_cond_sel_bitsreg;  -- Select jump condition.
3756 
                           next_pavr_s4_s5_branch_en <= '1';                                    -- Enable branch request.
3757 
                           next_pavr_s4_s5_branch_bitsreg_sel <= pavr_s3_instr(2 downto 0);     -- Select which bit in SREG will be checked as branch condition.
3758 
                           pavr_s3_stall_rq <= '1';
3759 
                        when "01" =>
3760 
                           -- BRBC s, k7 (Branch if bit in SREG is cleared (7 bit relative address))
3761 
                           next_pavr_s4_s5_k7_branch_offset <= pavr_s3_instr(9 downto 3);
3762 
                           next_pavr_s4_pcinc <= '1';
3763 
                           next_pavr_s4_s5_branch_cond_sel <= pavr_s5_branch_cond_sel_notbitsreg;
3764 
                           next_pavr_s4_s5_branch_en <= '1';
3765 
                           next_pavr_s4_s5_branch_bitsreg_sel <= pavr_s3_instr(2 downto 0);
3766 
                           pavr_s3_stall_rq <= '1';
3767 
                        when "10" =>
3768 
                           tmp2_b := pavr_s3_instr(9)&pavr_s3_instr(3);
3769 
                           case tmp2_b is
3770 
                              when "00" =>
3771 
                                 -- BLD Rd, b (Bit load from T flag in SREG into a bit in register)
3772 
                                 pavr_s3_rfrd1_rq <= '1';                                    -- Request RF read port 1 access in s3.
3773 
                                 pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);            -- Set address of operand to be read from RF read port 1.
3774 
                                 next_pavr_s4_s5_iof_rq <= '1';                              -- Request IOF access in s5 for loading the T flag in SREG into a bit in register.
3775 
                                 next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_ldbit;        -- Set IOF opcode in s5 to `load bit'.
3776 
                                 next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0); -- Set IOF bit address (s6).
3777 
                                 next_pavr_s4_s6_iof_bpr0wr_rq <= '1';                       -- Update BPU.
3778 
                                 next_pavr_s4_s6_iof_rfwr_rq <= '1';                         -- Request RF write port access.
3779 
                                 next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);    -- Set RF write-back address.
3780 
                                 next_pavr_s4_s5_stall_rq <= '1';                            -- Steal BPU0 write access from next instruction.
3781 
                              when "10" =>
3782 
                                 -- BST Rd, b (Bit store from a bit in register into T flag in SREG)
3783 
                                 pavr_s3_rfrd1_rq <= '1';                                    -- Request RF read port 1 access in s3.
3784 
                                 pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);            -- Set address of operand in RF.
3785 
                                 next_pavr_s4_s5_iof_rq <= '1';                              -- Request IOF access in s5 for storing the bit into T flag in SREG.
3786 
                                 next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_stbit;        -- Set IOF opcode in s5 to `store bit'.
3787 
                                 next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0); -- Set IOF bit address (s6).
3788 
                              when others =>
3789 
                                 -- Invalid opcode (1111_10xy_yyyy_xyyy, with xx = 01, 11)
3790 
                                 null;
3791 
                           end case;
3792 
                        when others =>
3793 
                           tmp2_c := pavr_s3_instr(9)&pavr_s3_instr(3);
3794 
                           case tmp2_c is
3795 
                              when "00" =>
3796 
                                 -- SBRC Rr, b (Skip if bit in register is cleared)
3797 
                                 pavr_s3_rfrd1_rq <= '1';          -- Read an operand from RF and use a specific bit of it (negated) as skip condition to be checked.
3798 
                                 pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3799 
                                 next_pavr_s4_s5_skip_bitrf_sel <= pavr_s3_instr(2 downto 0);
3800 
                                 next_pavr_s4_s5_skip_cond_sel <= pavr_s5_skip_cond_sel_notbitrf;
3801 
                                 next_pavr_s4_s5_skip_en <= '1';   -- Enable skip request in s5. If skip condition true, then: 1) stall (s6) and flush s5, 2) flush s3, 3) if instr32bits then flush s2
3802 
                                 pavr_s3_stall_rq <= '1';
3803 
                                 --next_pavr_s4_s5_stall_rq <= '1';  -- Request stall in s5. That's to have next two instruction words in s2 and s3, and be able to easely skip (flush) any or both of them.
3804 
                              when "10" =>
3805 
                                 -- SBRS Rr, b (Skip if bit in register is set)
3806 
                                 pavr_s3_rfrd1_rq <= '1';          -- Read an operand from RF and use a specific bit of it as skip condition to be checked.
3807 
                                 pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
3808 
                                 next_pavr_s4_s5_skip_bitrf_sel <= pavr_s3_instr(2 downto 0);
3809 
                                 next_pavr_s4_s5_skip_cond_sel <= pavr_s5_skip_cond_sel_bitrf;
3810 
                                 next_pavr_s4_s5_skip_en <= '1';
3811 
                                 pavr_s3_stall_rq <= '1';
3812 
                                 --next_pavr_s4_s5_stall_rq <= '1';
3813 
                              when others =>
3814 
                                 -- Invalid opcode (1111_11xy_yyyy_xyyy, with xx = 01, 11)
3815 
                                 null;
3816 
                           end case;
3817 
                     end case;
3818 
                  end if;
3819 
            end case;
3820 
         end if;
3821 
      else
3822 
 
3823 
         -- Interrupt request
3824 
         -- Forcedly place a call into the pipeline.
3825 
         next_pavr_s4_instr32bits <= '1';                -- Signalize 32 bit instruction (quite redundant here; kept for the regularity of the code).
3826 
         pavr_s3_flush_s2_rq <= '1';
3827 
         next_pavr_s4_flush_s2_rq <= '1';
3828 
         next_pavr_s4_nop_rq <= '1';                     -- Insert a nop *after* the instruction wavefront.
3829 
         next_pavr_s4_k22int_pm_rq <= '1';               -- Request PM access. Also, update PC.
3830 
         next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1';      -- Request DACU write access in s5, s51 and s52, to save the PC.
3831 
         next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1';   -- Decrement SP.
3832 
         next_pavr_s4_k22int <= pavr_int_vec;            -- Get absolute call address from interrupt vector.
3833 
         next_pavr_s4_s5_clriflag_sregwr_rq  <= '1';     -- Request clear I flag (general interrupt enable flag).
3834 
         next_pavr_s4_disable_int <= '1';                -- Disable interrupts in the next 4 clocks, so that at least an instruction is executed in the current interrupt routine.
3835 
         --next_pavr_s4_stall_rq <= '1';       -- !!! Needed?
3836 
 
3837 
      end if;
3838 
   end process instr_decoder;
3839 
 
3840 
 
3841 
 
3842 
 
3843 
 
3844 
 
3845 
 
3846 
 
3847 
 
3848 
 
3849 
   -- Hardware resources managers ---------------------------------------------
3850 
 
3851 
   -- RF read port 1
3852 
   -- Set the signals:
3853 
   --    - pavr_rf_rd1_addr
3854 
   --    - pavr_rf_rd1_rd
3855 
   rfrd1_manager:
3856 
   process(pavr_s3_rfrd1_rq,
3857 
           pavr_s5_dacu_rfrd1_rq,
3858 
 
3859 
           pavr_s3_hwrq_en,
3860 
           pavr_s5_hwrq_en,
3861 
 
3862 
           -- <Non synthesizable code>
3863 
           pavr_s2_pmdo_valid,
3864 
           -- </Non synthesizable code>
3865 
 
3866 
           pavr_rf_rd1_addr,
3867 
           pavr_s3_rfrd1_addr,
3868 
           pavr_s5_dacust_rf_addr)
3869 
      variable v_rfrd1rq_sel : std_logic_vector(1 downto 0);
3870 
   begin
3871 
      pavr_rf_rd1_addr <= int_to_std_logic_vector(0, pavr_rf_rd1_addr'length);
3872 
      pavr_rf_rd1_rd   <= '0';
3873 
 
3874 
      v_rfrd1rq_sel := pavr_s3_rfrd1_rq & pavr_s5_dacu_rfrd1_rq;
3875 
      case v_rfrd1rq_sel is
3876 
         when "00" =>
3877 
            -- No read requests.
3878 
            null;
3879 
         when "10" =>
3880 
            -- Instruction decoder RFRD1 request
3881 
            -- Only take action if permitted by older instructions.
3882 
            if pavr_s3_hwrq_en='1' then
3883 
               pavr_rf_rd1_addr <= pavr_s3_rfrd1_addr;
3884 
               pavr_rf_rd1_rd   <= '1';
3885 
            end if;
3886 
         when "01" =>
3887 
            -- DACU RFRD1 request, placed by loads and POP that decode UM as RF
3888 
            -- Only take action if permitted by older instructions.
3889 
            if pavr_s5_hwrq_en='1' then
3890 
               pavr_rf_rd1_addr <= pavr_s5_dacust_rf_addr;
3891 
               pavr_rf_rd1_rd   <= '1';
3892 
            end if;
3893 
         when others =>
3894 
            -- Multiple requests shouldn't happen.
3895 
            -- <Non synthesizable code>
3896 
            if pavr_s2_pmdo_valid='1' then
3897 
               assert false
3898 
                  report "Register File read port 1 error."
3899 
                  severity warning;
3900 
            end if;
3901 
            -- </Non synthesizable code>
3902 
            null;
3903 
      end case;
3904 
   end process rfrd1_manager;
3905 
 
3906 
 
3907 
 
3908 
   -- RF read port 2
3909 
   -- Set the signals:
3910 
   --    - pavr_rf_rd2_addr
3911 
   --    - pavr_rf_rd2_rd
3912 
   rfrd2_manager:
3913 
   process(pavr_s3_rfrd2_rq,
3914 
 
3915 
           pavr_s3_hwrq_en,
3916 
 
3917 
           pavr_rf_rd2_addr,
3918 
           pavr_s3_rfrd2_addr
3919 
          )
3920 
   begin
3921 
      pavr_rf_rd2_addr <= int_to_std_logic_vector(0, pavr_rf_rd2_addr'length);
3922 
      pavr_rf_rd2_rd   <= '0';
3923 
 
3924 
      if pavr_s3_rfrd2_rq='0' then
3925 
         -- No read requests.
3926 
         null;
3927 
      else
3928 
         -- Instruction decoder RFRD2 request
3929 
         -- Only take action if permitted by older instructions.
3930 
         if pavr_s3_hwrq_en='1' then
3931 
            pavr_rf_rd2_addr <= pavr_s3_rfrd2_addr;
3932 
            pavr_rf_rd2_rd   <= '1';
3933 
         end if;
3934 
      end if;
3935 
   end process rfrd2_manager;
3936 
 
3937 
 
3938 
 
3939 
   -- RF write port
3940 
   -- Set the signals:
3941 
   --    - pavr_rf_wr_addr
3942 
   --    - pavr_rf_wr_wr
3943 
   --    - pavr_rf_wr_di
3944 
   rfwr_manager:
3945 
   process(pavr_s6_aluoutlo8_rfwr_rq,
3946 
           pavr_s61_aluouthi8_rfwr_rq,
3947 
           pavr_s6_iof_rfwr_rq,
3948 
           pavr_s6_dacu_rfwr_rq,
3949 
           pavr_s6_pm_rfwr_rq,
3950 
           pavr_s5_dacu_rfwr_rq,
3951 
 
3952 
           pavr_s5_hwrq_en,
3953 
           pavr_s6_hwrq_en,
3954 
           pavr_s61_hwrq_en,
3955 
 
3956 
           -- <Non synthesizable code>
3957 
           pavr_s2_pmdo_valid,
3958 
           -- </Non synthesizable code>
3959 
 
3960 
           pavr_s6_zlsb,
3961 
           pavr_pm_do,
3962 
           pavr_rf_wr_addr,
3963 
           pavr_rf_wr_di,
3964 
           pavr_s6_rfwr_addr1,
3965 
           pavr_s61_rfwr_addr2,
3966 
           pavr_s6_alu_out,
3967 
           pavr_s61_alu_out_hi8,
3968 
           pavr_s5_dacust_rf_addr,
3969 
           pavr_s5_dacu_rfwr_di,
3970 
           pavr_iof_do_shadow_active,
3971 
           pavr_iof_do_shadow,
3972 
           pavr_iof_do,
3973 
           pavr_dacu_do_shadow_active,
3974 
           pavr_dacu_do_shadow,
3975 
           pavr_dacu_do,
3976 
           pavr_pm_do
3977 
          )
3978 
      variable v_rfwrrq_sel : std_logic_vector(5 downto 0);
3979 
   begin
3980 
      pavr_rf_wr_addr <= int_to_std_logic_vector(0, pavr_rf_wr_addr'length);
3981 
      pavr_rf_wr_wr   <= '0';
3982 
      pavr_rf_wr_di   <= int_to_std_logic_vector(0, pavr_rf_wr_di'length);
3983 
 
3984 
      v_rfwrrq_sel := pavr_s6_aluoutlo8_rfwr_rq &
3985 
                      pavr_s61_aluouthi8_rfwr_rq &
3986 
                      pavr_s6_iof_rfwr_rq &
3987 
                      pavr_s6_dacu_rfwr_rq &
3988 
                      pavr_s6_pm_rfwr_rq &
3989 
                      pavr_s5_dacu_rfwr_rq;
3990 
      case v_rfwrrq_sel is
3991 
         when "000000" =>
3992 
            -- No write requests.
3993 
            null;
3994 
         when "100000" =>
3995 
            -- ALU out lower 8 bits RFWR request
3996 
            -- Only take action if permitted by older instructions.
3997 
            if pavr_s6_hwrq_en='1' then
3998 
               pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
3999 
               pavr_rf_wr_wr   <= '1';
4000 
               pavr_rf_wr_di   <= pavr_s6_alu_out(7 downto 0);
4001 
            end if;
4002 
         when "010000" =>
4003 
            -- ALU out higher 8 bits RFWR request
4004 
            -- Only take action if permitted by older instructions.
4005 
            if pavr_s61_hwrq_en='1' then
4006 
               pavr_rf_wr_addr <= pavr_s61_rfwr_addr2;
4007 
               pavr_rf_wr_wr   <= '1';
4008 
               pavr_rf_wr_di   <= pavr_s61_alu_out_hi8;
4009 
            end if;
4010 
         when "001000" =>
4011 
            -- IOF out RFWR request
4012 
            -- Only take action if permitted by older instructions.
4013 
            if pavr_s6_hwrq_en='1' then
4014 
               pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
4015 
               pavr_rf_wr_wr   <= '1';
4016 
               if pavr_iof_do_shadow_active='0' then
4017 
                  pavr_rf_wr_di  <= pavr_iof_do;
4018 
               else
4019 
                  pavr_rf_wr_di  <= pavr_iof_do_shadow;
4020 
               end if;
4021 
            end if;
4022 
         when "000100" =>
4023 
            -- DACU out RFWR request, placed by loads and POP
4024 
            -- Only take action if permitted by older instructions.
4025 
            if pavr_s6_hwrq_en='1' then
4026 
               pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
4027 
               pavr_rf_wr_wr   <= '1';
4028 
               if pavr_dacu_do_shadow_active='0' then
4029 
                  pavr_rf_wr_di  <= pavr_dacu_do;
4030 
               else
4031 
                  pavr_rf_wr_di  <= pavr_dacu_do_shadow;
4032 
               end if;
4033 
            end if;
4034 
         when "000010" =>
4035 
            -- PM out RFWR request, placed by LPMs
4036 
            -- Only take action if permitted by older instructions.
4037 
            if pavr_s6_hwrq_en='1' then
4038 
               pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
4039 
               pavr_rf_wr_wr   <= '1';
4040 
               if pavr_s6_zlsb='0' then
4041 
                  -- *** Break a hole through the shadow protocol for this
4042 
                  --    off-placed PM read request.
4043 
                  -- Fortunately, there's no danger for PM data out to get
4044 
                  --    corrupted by a stall from older instructions, because this
4045 
                  --    request takes place so late in the pipeline, that no other
4046 
                  --    older instruction could stall it.
4047 
                  --if pavr_pm_do_shadow_active='0' then
4048 
                     pavr_rf_wr_di <= pavr_pm_do(7 downto 0);
4049 
                  --else
4050 
                  --   pavr_rf_wr_di <= pavr_pm_do_shadow(7 downto 0);
4051 
                  --end if;
4052 
               else
4053 
                  --if pavr_pm_do_shadow_active='0' then
4054 
                     pavr_rf_wr_di <= pavr_pm_do(15 downto 8);
4055 
                  --else
4056 
                  --   pavr_rf_wr_di <= pavr_pm_do_shadow(15 downto 8);
4057 
                  --end if;
4058 
               end if;
4059 
            end if;
4060 
         when "000001" =>
4061 
            -- DACU out RFWR request, placed by stores and PUSH
4062 
            -- Only take action if permitted by older instructions.
4063 
            if pavr_s5_hwrq_en='1' then
4064 
               pavr_rf_wr_addr <= pavr_s5_dacust_rf_addr;
4065 
               pavr_rf_wr_wr   <= '1';
4066 
               pavr_rf_wr_di   <= pavr_s5_dacu_rfwr_di;
4067 
            end if;
4068 
         when others =>
4069 
            -- Multiple requests shouldn't happen.
4070 
            -- <Non synthesizable code>
4071 
            if pavr_s2_pmdo_valid='1' then
4072 
               assert false
4073 
                  report "Register File write port error."
4074 
                  severity warning;
4075 
            end if;
4076 
            -- </Non synthesizable code>
4077 
            null;
4078 
      end case;
4079 
   end process rfwr_manager;
4080 
 
4081 
 
4082 
 
4083 
   -- X pointer write port
4084 
   -- Set the signals:
4085 
   --    - pavr_rf_x_wr
4086 
   --    - pavr_rf_x_di
4087 
   xwr_manager:
4088 
   process(pavr_s5_ldstincrampx_xwr_rq,
4089 
           pavr_s5_ldstdecrampx_xwr_rq,
4090 
 
4091 
           pavr_s5_hwrq_en,
4092 
 
4093 
           -- <Non synthesizable code>
4094 
           pavr_s2_pmdo_valid,
4095 
           -- </Non synthesizable code>
4096 
 
4097 
           pavr_rf_x_di,
4098 
           pavr_iof_rampx,
4099 
           pavr_xbpu
4100 
          )
4101 
      variable v_xwrrq_sel: std_logic_vector(1 downto 0);
4102 
      variable v_xrampx_inc: std_logic_vector(23 downto 0);
4103 
      variable v_xrampx_dec: std_logic_vector(23 downto 0);
4104 
   begin
4105 
      pavr_rf_x_wr <= '0';
4106 
      pavr_rf_x_di <= int_to_std_logic_vector(0, pavr_rf_x_di'length);
4107 
 
4108 
      v_xrampx_inc := (pavr_iof_rampx & pavr_xbpu) + 1;
4109 
      v_xrampx_dec := (pavr_iof_rampx & pavr_xbpu) - 1;
4110 
 
4111 
      v_xwrrq_sel := pavr_s5_ldstincrampx_xwr_rq & pavr_s5_ldstdecrampx_xwr_rq;
4112 
      case v_xwrrq_sel is
4113 
         when "00" =>
4114 
            -- No X write requests
4115 
            null;
4116 
         when "10" =>
4117 
            -- Increment X request, placed by loads and stores with post increment.
4118 
            -- Note that RAMPX is modified, if needed, by its own write manager.
4119 
            -- Only take action if permitted by older instructions.
4120 
            if pavr_s5_hwrq_en='1' then
4121 
               pavr_rf_x_wr <= '1';
4122 
               if pavr_dm_bigger_than_64K='1' then
4123 
                  pavr_rf_x_di <= v_xrampx_inc(15 downto 0);
4124 
               else
4125 
                  pavr_rf_x_di <= pavr_xbpu + 1;
4126 
               end if;
4127 
            end if;
4128 
         when "01" =>
4129 
            -- Decrement X request, placed by loads and stores with pre decrement.
4130 
            -- Only take action if permitted by older instructions.
4131 
            if pavr_s5_hwrq_en='1' then
4132 
               pavr_rf_x_wr <= '1';
4133 
               if pavr_dm_bigger_than_64K='1' then
4134 
                  pavr_rf_x_di <= v_xrampx_dec(15 downto 0);
4135 
               else
4136 
                  pavr_rf_x_di <= pavr_xbpu - 1;
4137 
               end if;
4138 
            end if;
4139 
         when others =>
4140 
            -- Multiple requests shouldn't happen.
4141 
            -- <Non synthesizable code>
4142 
            if pavr_s2_pmdo_valid='1' then
4143 
               assert false
4144 
                  report "X pointer error."
4145 
                  severity warning;
4146 
            end if;
4147 
            -- </Non synthesizable code>
4148 
            null;
4149 
      end case;
4150 
   end process xwr_manager;
4151 
 
4152 
 
4153 
 
4154 
   -- Y pointer write port
4155 
   -- Set the signals:
4156 
   --    - pavr_rf_y_wr
4157 
   --    - pavr_rf_y_di
4158 
   ywr_manager:
4159 
   process(pavr_s5_ldstincrampy_ywr_rq,
4160 
           pavr_s5_ldstdecrampy_ywr_rq,
4161 
 
4162 
           pavr_s5_hwrq_en,
4163 
 
4164 
           -- <Non synthesizable code>
4165 
           pavr_s2_pmdo_valid,
4166 
           -- </Non synthesizable code>
4167 
 
4168 
           pavr_rf_y_di,
4169 
           pavr_iof_rampy,
4170 
           pavr_ybpu,
4171 
           pavr_iof_rampy
4172 
          )
4173 
      variable v_ywrrq_sel: std_logic_vector(1 downto 0);
4174 
      variable v_yrampy_inc: std_logic_vector(23 downto 0);
4175 
      variable v_yrampy_dec: std_logic_vector(23 downto 0);
4176 
   begin
4177 
      pavr_rf_y_wr <= '0';
4178 
      pavr_rf_y_di <= int_to_std_logic_vector(0, pavr_rf_y_di'length);
4179 
 
4180 
      v_yrampy_inc := (pavr_iof_rampy & pavr_ybpu) + 1;
4181 
      v_yrampy_dec := (pavr_iof_rampy & pavr_ybpu) - 1;
4182 
 
4183 
      v_ywrrq_sel := pavr_s5_ldstincrampy_ywr_rq & pavr_s5_ldstdecrampy_ywr_rq;
4184 
      case v_ywrrq_sel is
4185 
         when "00" =>
4186 
            null;
4187 
         when "10" =>
4188 
            -- Increment Y request, placed by loads and stores with post increment.
4189 
            -- Note that RAMPY is modified, if needed, by its own write manager.
4190 
            -- Only take action if permitted by older instructions.
4191 
            if pavr_s5_hwrq_en='1' then
4192 
               pavr_rf_y_wr <= '1';
4193 
               if pavr_dm_bigger_than_64K='1' then
4194 
                  pavr_rf_y_di <= v_yrampy_inc(15 downto 0);
4195 
               else
4196 
                  pavr_rf_y_di <= pavr_ybpu + 1;
4197 
               end if;
4198 
            end if;
4199 
         when "01" =>
4200 
            -- Decrement Y request, placed by loads and stores with pre decrement.
4201 
            -- Only take action if permitted by older instructions.
4202 
            if pavr_s5_hwrq_en='1' then
4203 
               pavr_rf_y_wr <= '1';
4204 
               if pavr_dm_bigger_than_64K='1' then
4205 
                  pavr_rf_y_di <= v_yrampy_dec(15 downto 0);
4206 
               else
4207 
                  pavr_rf_y_di <= pavr_ybpu - 1;
4208 
               end if;
4209 
            end if;
4210 
         when others =>
4211 
            -- Multiple requests shouldn't happen.
4212 
            -- <Non synthesizable code>
4213 
            if pavr_s2_pmdo_valid='1' then
4214 
               assert false
4215 
                  report "Y pointer error."
4216 
                  severity warning;
4217 
            end if;
4218 
            -- </Non synthesizable code>
4219 
            null;
4220 
      end case;
4221 
   end process ywr_manager;
4222 
 
4223 
 
4224 
 
4225 
   -- Z pointer write port
4226 
   -- Set the signals:
4227 
   --    - pavr_rf_z_wr
4228 
   --    - pavr_rf_z_di
4229 
   zwr_manager:
4230 
   process(pavr_s5_ldstincrampz_zwr_rq,
4231 
           pavr_s5_ldstdecrampz_zwr_rq,
4232 
           pavr_s5_lpminc_zwr_rq,
4233 
           pavr_s5_elpmincrampz_zwr_rq,
4234 
 
4235 
           pavr_s5_hwrq_en,
4236 
 
4237 
           -- <Non synthesizable code>
4238 
           pavr_s2_pmdo_valid,
4239 
           -- </Non synthesizable code>
4240 
 
4241 
           pavr_zbpu,
4242 
           pavr_iof_rampz,
4243 
           pavr_rf_z_di
4244 
          )
4245 
      variable v_zwrrq_sel: std_logic_vector(3 downto 0);
4246 
      variable v_zrampz_inc: std_logic_vector(23 downto 0);
4247 
      variable v_zrampz_dec: std_logic_vector(23 downto 0);
4248 
   begin
4249 
      pavr_rf_z_wr <= '0';
4250 
      pavr_rf_z_di <= int_to_std_logic_vector(0, pavr_rf_z_di'length);
4251 
 
4252 
      v_zrampz_inc := (pavr_iof_rampz & pavr_zbpu) + 1;
4253 
      v_zrampz_dec := (pavr_iof_rampz & pavr_zbpu) - 1;
4254 
 
4255 
      v_zwrrq_sel := pavr_s5_ldstincrampz_zwr_rq &
4256 
                     pavr_s5_ldstdecrampz_zwr_rq &
4257 
                     pavr_s5_lpminc_zwr_rq       &
4258 
                     pavr_s5_elpmincrampz_zwr_rq;
4259 
      case v_zwrrq_sel is
4260 
         when "0000" =>
4261 
            null;
4262 
         when "1000" | "0001" =>
4263 
            -- Increment Z request, placed by loads, stores and ELPM with post increment.
4264 
            -- Note that RAMPZ is modified, if needed, by its own write manager.
4265 
            -- Only take action if permitted by older instructions.
4266 
            if pavr_s5_hwrq_en='1' then
4267 
               pavr_rf_z_wr <= '1';
4268 
               if pavr_dm_bigger_than_64K='1' then
4269 
                  pavr_rf_z_di <= v_zrampz_inc(15 downto 0);
4270 
               else
4271 
                  pavr_rf_z_di <= pavr_zbpu + 1;
4272 
               end if;
4273 
            end if;
4274 
         when "0100" =>
4275 
            -- Decrement Z request, placed by loads and stores with pre decrement.
4276 
            -- Only take action if permitted by older instructions.
4277 
            if pavr_s5_hwrq_en='1' then
4278 
               pavr_rf_z_wr <= '1';
4279 
               if pavr_dm_bigger_than_64K='1' then
4280 
                  pavr_rf_z_di <= v_zrampz_dec(15 downto 0);
4281 
               else
4282 
                  pavr_rf_z_di <= pavr_zbpu - 1;
4283 
               end if;
4284 
            end if;
4285 
         when "0010" =>
4286 
            -- Increment Z request, placed by LPM with post increment.
4287 
            -- Only take action if permitted by older instructions.
4288 
            if pavr_s5_hwrq_en='1' then
4289 
               pavr_rf_z_wr <= '1';
4290 
               pavr_rf_z_di <= pavr_zbpu + 1;
4291 
            end if;
4292 
         when others =>
4293 
            -- Multiple requests shouldn't happen.
4294 
            -- <Non synthesizable code>
4295 
            if pavr_s2_pmdo_valid='1' then
4296 
               assert false
4297 
                  report "Z pointer error."
4298 
                  severity warning;
4299 
            end if;
4300 
            -- </Non synthesizable code>
4301 
            null;
4302 
      end case;
4303 
   end process zwr_manager;
4304 
 
4305 
 
4306 
 
4307 
   -- BPU write, BPR0-related
4308 
   -- Set the signals:
4309 
   --    - next_pavr_bpr0
4310 
   --    - next_pavr_bpr0_addr
4311 
   --    - next_pavr_bpr0_active
4312 
   bpr0wr_manager:
4313 
   process(pavr_s5_alu_bpr0wr_rq,
4314 
           pavr_s6_iof_bpr0wr_rq,
4315 
           pavr_s6_daculd_bpr0wr_rq,
4316 
           pavr_s5_dacust_bpr0wr_rq,
4317 
           pavr_s6_pmdo_bpr0wr_rq,
4318 
 
4319 
           pavr_stall_s5,
4320 
           pavr_flush_s5,
4321 
           pavr_stall_s6,
4322 
           pavr_flush_s6,
4323 
 
4324 
           pavr_s6_zlsb,
4325 
           next_pavr_bpr0,
4326 
           next_pavr_bpr0_addr,
4327 
           pavr_s5_alu_out,
4328 
           pavr_s5_op1bpu,
4329 
           pavr_s6_rfwr_addr1,
4330 
           pavr_s5_s6_rfwr_addr1,
4331 
           pavr_s5_dacust_rf_addr,
4332 
 
4333 
           -- <Non synthesizable code>
4334 
           pavr_s2_pmdo_valid,
4335 
           -- </Non synthesizable code>
4336 
 
4337 
           pavr_iof_do_shadow_active,
4338 
           pavr_iof_do_shadow,
4339 
           pavr_dacu_do_shadow_active,
4340 
           pavr_dacu_do_shadow,
4341 
           pavr_dacu_do,
4342 
           pavr_iof_do,
4343 
           --pavr_pm_do_shadow_active,
4344 
           --pavr_pm_do_shadow,
4345 
           pavr_pm_do
4346 
          )
4347 
      variable v_bpr0wrrq_sel: std_logic_vector(4 downto 0);
4348 
   begin
4349 
      next_pavr_bpr0          <= int_to_std_logic_vector(0, next_pavr_bpr0'length);
4350 
      next_pavr_bpr0_addr     <= int_to_std_logic_vector(0, next_pavr_bpr0_addr'length);
4351 
      next_pavr_bpr0_active   <= '0';
4352 
 
4353 
      v_bpr0wrrq_sel := pavr_s5_alu_bpr0wr_rq    &
4354 
                        pavr_s6_iof_bpr0wr_rq    &
4355 
                        pavr_s6_daculd_bpr0wr_rq &
4356 
                        pavr_s5_dacust_bpr0wr_rq &
4357 
                        pavr_s6_pmdo_bpr0wr_rq;
4358 
 
4359 
      case v_bpr0wrrq_sel is
4360 
         when "00000" =>
4361 
            null;
4362 
         when "10000" =>
4363 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4364 
               next_pavr_bpr0          <= pavr_s5_alu_out(7 downto 0);
4365 
               next_pavr_bpr0_addr     <= pavr_s5_s6_rfwr_addr1;
4366 
               next_pavr_bpr0_active   <= '1';
4367 
            end if;
4368 
         when "01000" =>
4369 
            if pavr_stall_s6='0' and pavr_flush_s6='0' then
4370 
               if pavr_iof_do_shadow_active='0' then
4371 
                  next_pavr_bpr0 <= pavr_iof_do;
4372 
               else
4373 
                  next_pavr_bpr0 <= pavr_iof_do_shadow;
4374 
               end if;
4375 
               next_pavr_bpr0_addr     <= pavr_s6_rfwr_addr1;
4376 
               next_pavr_bpr0_active   <= '1';
4377 
            end if;
4378 
         when "00100" =>
4379 
            if pavr_stall_s6='0' and pavr_flush_s6='0' then
4380 
               if pavr_dacu_do_shadow_active='0' then
4381 
                  next_pavr_bpr0 <= pavr_dacu_do;
4382 
               else
4383 
                  next_pavr_bpr0 <= pavr_dacu_do_shadow;
4384 
               end if;
4385 
               next_pavr_bpr0_addr     <= pavr_s6_rfwr_addr1;
4386 
               next_pavr_bpr0_active   <= '1';
4387 
            end if;
4388 
         when "00010" =>
4389 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4390 
               next_pavr_bpr0          <= pavr_s5_op1bpu;
4391 
               next_pavr_bpr0_addr     <= pavr_s5_dacust_rf_addr;
4392 
               next_pavr_bpr0_active   <= '1';
4393 
            end if;
4394 
         when "00001" =>
4395 
            if pavr_stall_s6='0' and pavr_flush_s6='0' then
4396 
               if pavr_s6_zlsb='0' then
4397 
                  -- *** Break a hole through the shadow protocol.
4398 
                  --if pavr_pm_do_shadow_active='0' then
4399 
                     next_pavr_bpr0 <= pavr_pm_do(7 downto 0);
4400 
                  --else
4401 
                  --   next_pavr_bpr0 <= pavr_pm_do_shadow(7 downto 0);
4402 
                  --end if;
4403 
               else
4404 
                  --if pavr_pm_do_shadow_active='0' then
4405 
                     next_pavr_bpr0 <= pavr_pm_do(15 downto 8);
4406 
                  --else
4407 
                  --   next_pavr_bpr0 <= pavr_pm_do_shadow(15 downto 8);
4408 
                  --end if;
4409 
               end if;
4410 
               next_pavr_bpr0_addr     <= pavr_s6_rfwr_addr1;
4411 
               next_pavr_bpr0_active   <= '1';
4412 
            end if;
4413 
         when others =>
4414 
            -- <Non synthesizable code>
4415 
            if pavr_s2_pmdo_valid='1' then
4416 
               assert false
4417 
                  report "Bypass Unit, chain 0 error."
4418 
                  severity warning;
4419 
            end if;
4420 
            -- </Non synthesizable code>
4421 
            null;
4422 
      end case;
4423 
   end process bpr0wr_manager;
4424 
 
4425 
 
4426 
 
4427 
   -- BPU write, BPR1-related
4428 
   -- Set the signals:
4429 
   --    - next_pavr_bpr1
4430 
   --    - next_pavr_bpr1_addr
4431 
   --    - next_pavr_bpr1_active
4432 
   bpr1wr_manager:
4433 
   process(pavr_s5_alu_bpr1wr_rq,
4434 
           pavr_s5_dacux_bpr12wr_rq,
4435 
           pavr_s5_dacuy_bpr12wr_rq,
4436 
           pavr_s5_dacuz_bpr12wr_rq,
4437 
 
4438 
           pavr_rf_x_di,
4439 
           pavr_rf_y_di,
4440 
           pavr_rf_z_di,
4441 
 
4442 
           pavr_stall_s5,
4443 
           pavr_flush_s5,
4444 
 
4445 
           -- <Non synthesizable code>
4446 
           pavr_s2_pmdo_valid,
4447 
           -- </Non synthesizable code>
4448 
 
4449 
           next_pavr_bpr1,
4450 
           pavr_s5_alu_out,
4451 
           pavr_s5_s61_rfwr_addr2,
4452 
           next_pavr_bpr1_addr
4453 
          )
4454 
      variable v_bpr1wrrq_sel: std_logic_vector(3 downto 0);
4455 
   begin
4456 
      next_pavr_bpr1          <= int_to_std_logic_vector(0, next_pavr_bpr1'length);
4457 
      next_pavr_bpr1_addr     <= int_to_std_logic_vector(0, next_pavr_bpr1_addr'length);
4458 
      next_pavr_bpr1_active   <= '0';
4459 
 
4460 
      v_bpr1wrrq_sel := pavr_s5_alu_bpr1wr_rq    &
4461 
                        pavr_s5_dacux_bpr12wr_rq &
4462 
                        pavr_s5_dacuy_bpr12wr_rq &
4463 
                        pavr_s5_dacuz_bpr12wr_rq;
4464 
 
4465 
      case v_bpr1wrrq_sel is
4466 
         when "0000" =>
4467 
            null;
4468 
         when "1000" =>
4469 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4470 
               next_pavr_bpr1          <= pavr_s5_alu_out(15 downto 8);
4471 
               next_pavr_bpr1_addr     <= pavr_s5_s61_rfwr_addr2;
4472 
               next_pavr_bpr1_active   <= '1';
4473 
            end if;
4474 
         when "0100" =>
4475 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4476 
               next_pavr_bpr1          <= pavr_rf_x_di(7 downto 0);
4477 
               next_pavr_bpr1_addr     <= int_to_std_logic_vector(26, next_pavr_bpr1_addr'length);
4478 
               next_pavr_bpr1_active   <= '1';
4479 
            end if;
4480 
         when "0010" =>
4481 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4482 
               next_pavr_bpr1          <= pavr_rf_y_di(7 downto 0);
4483 
               next_pavr_bpr1_addr     <= int_to_std_logic_vector(28, next_pavr_bpr1_addr'length);
4484 
               next_pavr_bpr1_active   <= '1';
4485 
            end if;
4486 
         when "0001" =>
4487 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4488 
               next_pavr_bpr1          <= pavr_rf_z_di(7 downto 0);
4489 
               next_pavr_bpr1_addr     <= int_to_std_logic_vector(30, next_pavr_bpr1_addr'length);
4490 
               next_pavr_bpr1_active   <= '1';
4491 
            end if;
4492 
         when others =>
4493 
            -- <Non synthesizable code>
4494 
            if pavr_s2_pmdo_valid='1' then
4495 
               assert false
4496 
                  report "Bypass Unit, chain 1 error."
4497 
                  severity warning;
4498 
            end if;
4499 
            -- </Non synthesizable code>
4500 
            null;
4501 
      end case;
4502 
   end process bpr1wr_manager;
4503 
 
4504 
 
4505 
 
4506 
   -- BPU write, BPR2-related
4507 
   -- Set the signals:
4508 
   --    - next_pavr_bpr2
4509 
   --    - next_pavr_bpr2_addr
4510 
   --    - next_pavr_bpr2_active
4511 
   bpr2wr_manager:
4512 
   process(pavr_s5_dacux_bpr12wr_rq,
4513 
           pavr_s5_dacuy_bpr12wr_rq,
4514 
           pavr_s5_dacuz_bpr12wr_rq,
4515 
 
4516 
           next_pavr_bpr2,
4517 
           next_pavr_bpr2_addr,
4518 
 
4519 
           pavr_rf_x_di,
4520 
           pavr_rf_y_di,
4521 
           pavr_rf_z_di,
4522 
 
4523 
           -- <Non synthesizable code>
4524 
           pavr_s2_pmdo_valid,
4525 
           -- </Non synthesizable code>
4526 
 
4527 
           pavr_stall_s5,
4528 
           pavr_flush_s5
4529 
          )
4530 
      variable v_bpr2wrrq_sel: std_logic_vector(2 downto 0);
4531 
   begin
4532 
      next_pavr_bpr2          <= int_to_std_logic_vector(0, next_pavr_bpr2'length);
4533 
      next_pavr_bpr2_addr     <= int_to_std_logic_vector(0, next_pavr_bpr2_addr'length);
4534 
      next_pavr_bpr2_active   <= '0';
4535 
 
4536 
      v_bpr2wrrq_sel := pavr_s5_dacux_bpr12wr_rq &
4537 
                        pavr_s5_dacuy_bpr12wr_rq &
4538 
                        pavr_s5_dacuz_bpr12wr_rq;
4539 
 
4540 
      case v_bpr2wrrq_sel is
4541 
         when "000" =>
4542 
            null;
4543 
         when "100" =>
4544 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4545 
               next_pavr_bpr2          <= pavr_rf_x_di(15 downto 8);
4546 
               next_pavr_bpr2_addr     <= int_to_std_logic_vector(27, next_pavr_bpr2_addr'length);
4547 
               next_pavr_bpr2_active   <= '1';
4548 
            end if;
4549 
         when "010" =>
4550 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4551 
               next_pavr_bpr2          <= pavr_rf_y_di(15 downto 8);
4552 
               next_pavr_bpr2_addr     <= int_to_std_logic_vector(29, next_pavr_bpr2_addr'length);
4553 
               next_pavr_bpr2_active   <= '1';
4554 
            end if;
4555 
         when "001" =>
4556 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4557 
               next_pavr_bpr2          <= pavr_rf_z_di(15 downto 8);
4558 
               next_pavr_bpr2_addr     <= int_to_std_logic_vector(31, next_pavr_bpr2_addr'length);
4559 
               next_pavr_bpr2_active   <= '1';
4560 
            end if;
4561 
         when others =>
4562 
            -- <Non synthesizable code>
4563 
            if pavr_s2_pmdo_valid='1' then
4564 
               assert false
4565 
                  report "Bypass Unit, chain 2 error."
4566 
                  severity warning;
4567 
            end if;
4568 
            -- </Non synthesizable code>
4569 
            null;
4570 
      end case;
4571 
   end process bpr2wr_manager;
4572 
 
4573 
 
4574 
 
4575 
   -- IOF general port-related (write/read)
4576 
   -- Set the signals:
4577 
   --    - pavr_iof_di
4578 
   --    - pavr_iof_opcode
4579 
   --    - pavr_iof_addr
4580 
   --    - pavr_iof_bitaddr
4581 
   iof_manager:
4582 
   process(pavr_s5_iof_rq,
4583 
           pavr_s6_iof_rq,
4584 
           pavr_s5_dacu_iof_rq,
4585 
 
4586 
           pavr_stall_s5,
4587 
           pavr_flush_s5,
4588 
           pavr_stall_s6,
4589 
           pavr_flush_s6,
4590 
 
4591 
           -- <Non synthesizable code>
4592 
           pavr_s2_pmdo_valid,
4593 
           -- </Non synthesizable code>
4594 
 
4595 
           pavr_s5_op1bpu,
4596 
           pavr_s5_iof_opcode,
4597 
           pavr_s5_iof_addr,
4598 
           pavr_s5_iof_bitaddr,
4599 
           pavr_s6_iof_opcode,
4600 
           pavr_s6_iof_addr,
4601 
           pavr_s6_iof_bitaddr,
4602 
           pavr_s5_dacu_iof_opcode,
4603 
           pavr_s5_dacu_iof_addr,
4604 
           pavr_s5_dacu_iofwr_di,
4605 
           pavr_iof_di,
4606 
           pavr_iof_opcode,
4607 
           pavr_iof_addr,
4608 
           pavr_iof_bitaddr,
4609 
           pavr_iof_do,
4610 
           pavr_iof_do_shadow,
4611 
           pavr_iof_do_shadow_active
4612 
          )
4613 
      variable v_iofrq_sel: std_logic_vector(2 downto 0);
4614 
   begin
4615 
      pavr_iof_di       <= int_to_std_logic_vector(0, pavr_iof_di'length);
4616 
      pavr_iof_opcode   <= int_to_std_logic_vector(0, pavr_iof_opcode'length);
4617 
      pavr_iof_addr     <= int_to_std_logic_vector(0, pavr_iof_addr'length);
4618 
      pavr_iof_bitaddr  <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
4619 
 
4620 
      v_iofrq_sel := pavr_s5_iof_rq & pavr_s6_iof_rq & pavr_s5_dacu_iof_rq;
4621 
      case v_iofrq_sel is
4622 
         when "000" =>
4623 
            pavr_iof_di       <= int_to_std_logic_vector(0, pavr_iof_di'length);
4624 
            pavr_iof_opcode   <= int_to_std_logic_vector(0, pavr_iof_opcode'length);
4625 
            pavr_iof_addr     <= int_to_std_logic_vector(0, pavr_iof_addr'length);
4626 
            pavr_iof_bitaddr  <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
4627 
         when "100" =>
4628 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4629 
               pavr_iof_di       <= pavr_s5_op1bpu;
4630 
               pavr_iof_opcode   <= pavr_s5_iof_opcode;
4631 
               pavr_iof_addr     <= pavr_s5_iof_addr;
4632 
               pavr_iof_bitaddr  <= pavr_s5_iof_bitaddr;
4633 
            end if;
4634 
         when "010" =>
4635 
            if pavr_stall_s6='0' and pavr_flush_s6='0' then
4636 
               if pavr_s6_iof_opcode=pavr_iof_opcode_ldbit then
4637 
                  pavr_iof_di    <= pavr_s5_op1bpu;
4638 
               else
4639 
                  if pavr_iof_do_shadow_active='0' then
4640 
                     pavr_iof_di <= pavr_iof_do;
4641 
                  else
4642 
                     pavr_iof_di <= pavr_iof_do_shadow;
4643 
                  end if;
4644 
               end if;
4645 
               pavr_iof_opcode   <= pavr_s6_iof_opcode;
4646 
               pavr_iof_addr     <= pavr_s6_iof_addr;
4647 
               pavr_iof_bitaddr  <= pavr_s6_iof_bitaddr;
4648 
            end if;
4649 
         when "001" =>
4650 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4651 
               pavr_iof_di       <= pavr_s5_dacu_iofwr_di;
4652 
               pavr_iof_opcode   <= pavr_s5_dacu_iof_opcode;
4653 
               pavr_iof_addr     <= pavr_s5_dacu_iof_addr;
4654 
               pavr_iof_bitaddr  <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
4655 
            end if;
4656 
         when others =>
4657 
            -- Multiple requests shouldn't happen.
4658 
            -- <Non synthesizable code>
4659 
            if pavr_s2_pmdo_valid='1' then
4660 
               assert false
4661 
                  report "IO File error."
4662 
                  severity warning;
4663 
            end if;
4664 
            -- </Non synthesizable code>
4665 
            null;
4666 
      end case;
4667 
   end process iof_manager;
4668 
 
4669 
 
4670 
 
4671 
   -- SREG-related
4672 
   -- Set the signals:
4673 
   --    - pavr_iof_sreg_wr
4674 
   --    - pavr_iof_sreg_di
4675 
   sregwr_manager:
4676 
   process(pavr_s5_alu_sregwr_rq,
4677 
           pavr_s5_clriflag_sregwr_rq,
4678 
           pavr_s5_setiflag_sregwr_rq,
4679 
 
4680 
           pavr_stall_s5,
4681 
           pavr_flush_s5,
4682 
 
4683 
           -- <Non synthesizable code>
4684 
           pavr_s2_pmdo_valid,
4685 
           -- </Non synthesizable code>
4686 
 
4687 
           pavr_iof_sreg,
4688 
           pavr_iof_sreg_di,
4689 
           pavr_s5_alu_flagsout
4690 
          )
4691 
      variable v_sregwrrq_sel: std_logic_vector(2 downto 0);
4692 
   begin
4693 
      pavr_iof_sreg_wr <= '0';
4694 
      pavr_iof_sreg_di <= int_to_std_logic_vector(0, pavr_iof_sreg_di'length);
4695 
 
4696 
      v_sregwrrq_sel := pavr_s5_alu_sregwr_rq & pavr_s5_clriflag_sregwr_rq & pavr_s5_setiflag_sregwr_rq;
4697 
      case v_sregwrrq_sel is
4698 
         when "000" =>
4699 
            pavr_iof_sreg_wr <= '0';
4700 
            pavr_iof_sreg_di <= int_to_std_logic_vector(0, pavr_iof_sreg_di'length);
4701 
         when "100" =>
4702 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4703 
               pavr_iof_sreg_wr <= '1';
4704 
               pavr_iof_sreg_di <= pavr_iof_sreg(7 downto 6) & pavr_s5_alu_flagsout;
4705 
            end if;
4706 
         when "010" =>
4707 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4708 
               pavr_iof_sreg_wr <= '1';
4709 
               pavr_iof_sreg_di <= '0' & pavr_iof_sreg(6 downto 0);
4710 
            end if;
4711 
         when "001" =>
4712 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4713 
               pavr_iof_sreg_wr <= '1';
4714 
               pavr_iof_sreg_di <= '1' & pavr_iof_sreg(6 downto 0);
4715 
            end if;
4716 
         when others =>
4717 
            -- Multiple requests shouldn't happen.
4718 
            -- <Non synthesizable code>
4719 
            if pavr_s2_pmdo_valid='1' then
4720 
               assert false
4721 
                  report "SREG error."
4722 
                  severity warning;
4723 
            end if;
4724 
            -- </Non synthesizable code>
4725 
            null;
4726 
      end case;
4727 
   end process sregwr_manager;
4728 
 
4729 
 
4730 
 
4731 
   -- SP-related
4732 
   -- Set the signals:
4733 
   --    - pavr_iof_spl_wr
4734 
   --    - pavr_iof_spl_di
4735 
   --    - pavr_iof_sph_wr
4736 
   --    - pavr_iof_sph_di
4737 
   spwr_manager:
4738 
   process(pavr_s5_inc_spwr_rq, pavr_s5_dec_spwr_rq,
4739 
           pavr_s5_calldec_spwr_rq, pavr_s51_calldec_spwr_rq, pavr_s52_calldec_spwr_rq,
4740 
           pavr_s5_retinc2_spwr_rq, pavr_s51_retinc_spwr_rq,
4741 
 
4742 
           pavr_stall_s5,
4743 
           pavr_flush_s5,
4744 
 
4745 
           -- <Non synthesizable code>
4746 
           pavr_s2_pmdo_valid,
4747 
           -- </Non synthesizable code>
4748 
 
4749 
           pavr_iof_spl_di,
4750 
           pavr_iof_sph_di,
4751 
           pavr_iof_sph,
4752 
           pavr_iof_spl
4753 
          )
4754 
      variable v_spwrrq_sel: std_logic_vector(6 downto 0);
4755 
      variable v_sp_inc  : std_logic_vector(15 downto 0);
4756 
      variable v_sp_inc2 : std_logic_vector(15 downto 0);
4757 
      variable v_sp_dec  : std_logic_vector(15 downto 0);
4758 
   begin
4759 
      pavr_iof_spl_wr <= '0';
4760 
      pavr_iof_spl_di <= int_to_std_logic_vector(0, pavr_iof_spl_di'length);
4761 
      pavr_iof_sph_wr <= '0';
4762 
      pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4763 
 
4764 
      v_sp_inc  := (pavr_iof_sph & pavr_iof_spl) + 1;
4765 
      v_sp_inc2 := (pavr_iof_sph & pavr_iof_spl) + 2;
4766 
      v_sp_dec  := (pavr_iof_sph & pavr_iof_spl) - 1;
4767 
      v_spwrrq_sel := pavr_s5_inc_spwr_rq & pavr_s5_dec_spwr_rq &
4768 
                      pavr_s5_calldec_spwr_rq & pavr_s51_calldec_spwr_rq & pavr_s52_calldec_spwr_rq &
4769 
                      pavr_s5_retinc2_spwr_rq & pavr_s51_retinc_spwr_rq;
4770 
 
4771 
      case v_spwrrq_sel is
4772 
         -- No SP write requests. Set SP inputs to a most benign state. Only change inputs when write is requested, to minimize power consumption.
4773 
         when "0000000" =>
4774 
            pavr_iof_spl_wr <= '0';
4775 
            pavr_iof_spl_di <= int_to_std_logic_vector(0, pavr_iof_spl_di'length);
4776 
            pavr_iof_sph_wr <= '0';
4777 
            pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4778 
         -- Increment SP request. For devices with 256B or less of Unified Memory, only update lower byte of SP. For the other devices, modify all 16 bits of SP.
4779 
         when "1000000" =>
4780 
            -- Stall capability in s5.
4781 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4782 
               if pavr_dm_bigger_than_256='0' then
4783 
                  pavr_iof_spl_wr <= '1';
4784 
                  pavr_iof_spl_di <= v_sp_inc(7 downto 0);
4785 
                  pavr_iof_sph_wr <= '0';
4786 
                  pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4787 
               else
4788 
                  pavr_iof_spl_wr <= '1';
4789 
                  pavr_iof_spl_di <= v_sp_inc(7 downto 0);
4790 
                  pavr_iof_sph_wr <= '1';
4791 
                  pavr_iof_sph_di <= v_sp_inc(15 downto 8);
4792 
               end if;
4793 
            end if;
4794 
         -- Increment SP request. For devices with 256B or less of Unified Memory, only update lower byte of SP. For the other devices, modify all 16 bits of SP.
4795 
         when "0000001" =>
4796 
            if pavr_dm_bigger_than_256='0' then
4797 
               pavr_iof_spl_wr <= '1';
4798 
               pavr_iof_spl_di <= v_sp_inc(7 downto 0);
4799 
               pavr_iof_sph_wr <= '0';
4800 
               pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4801 
            else
4802 
               pavr_iof_spl_wr <= '1';
4803 
               pavr_iof_spl_di <= v_sp_inc(7 downto 0);
4804 
               pavr_iof_sph_wr <= '1';
4805 
               pavr_iof_sph_di <= v_sp_inc(15 downto 8);
4806 
            end if;
4807 
         -- Increment by 2 SP request.
4808 
         when "0000010" =>
4809 
            -- Stall capability in s5.
4810 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4811 
               if pavr_dm_bigger_than_256='0' then
4812 
                  pavr_iof_spl_wr <= '1';
4813 
                  pavr_iof_spl_di <= v_sp_inc2(7 downto 0);
4814 
                  pavr_iof_sph_wr <= '0';
4815 
                  pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4816 
               else
4817 
                  pavr_iof_spl_wr <= '1';
4818 
                  pavr_iof_spl_di <= v_sp_inc2(7 downto 0);
4819 
                  pavr_iof_sph_wr <= '1';
4820 
                  pavr_iof_sph_di <= v_sp_inc2(15 downto 8);
4821 
               end if;
4822 
            end if;
4823 
         -- Decrement SP request.
4824 
         when "0100000" | "0010000" =>
4825 
            -- Stall capability in s5.
4826 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4827 
               if pavr_dm_bigger_than_256='0' then
4828 
                  pavr_iof_spl_wr <= '1';
4829 
                  pavr_iof_spl_di <= v_sp_dec(7 downto 0);
4830 
                  pavr_iof_sph_wr <= '0';
4831 
                  pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4832 
               else
4833 
                  pavr_iof_spl_wr <= '1';
4834 
                  pavr_iof_spl_di <= v_sp_dec(7 downto 0);
4835 
                  pavr_iof_sph_wr <= '1';
4836 
                  pavr_iof_sph_di <= v_sp_dec(15 downto 8);
4837 
               end if;
4838 
            end if;
4839 
         -- Decrement SP request.
4840 
         when "0000100" | "0001000" =>
4841 
            if pavr_dm_bigger_than_256='0' then
4842 
               pavr_iof_spl_wr <= '1';
4843 
               pavr_iof_spl_di <= v_sp_dec(7 downto 0);
4844 
               pavr_iof_sph_wr <= '0';
4845 
               pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
4846 
            else
4847 
               pavr_iof_spl_wr <= '1';
4848 
               pavr_iof_spl_di <= v_sp_dec(7 downto 0);
4849 
               pavr_iof_sph_wr <= '1';
4850 
               pavr_iof_sph_di <= v_sp_dec(15 downto 8);
4851 
            end if;
4852 
         when others =>
4853 
            -- Multiple requests shouldn't happen.
4854 
            -- <Non synthesizable code>
4855 
            if pavr_s2_pmdo_valid='1' then
4856 
               assert false
4857 
                  report "SP error."
4858 
                  severity warning;
4859 
            end if;
4860 
            -- </Non synthesizable code>
4861 
            null;
4862 
      end case;
4863 
   end process spwr_manager;
4864 
 
4865 
 
4866 
 
4867 
   -- RAMPX-related
4868 
   -- Set the signals:
4869 
   --    - pavr_iof_rampx_wr
4870 
   --    - pavr_iof_rampx_di
4871 
   rampxwr_manager:
4872 
   process(pavr_s5_ldstincrampx_xwr_rq,
4873 
           pavr_s5_ldstdecrampx_xwr_rq,
4874 
 
4875 
           pavr_stall_s5,
4876 
           pavr_flush_s5,
4877 
 
4878 
           -- <Non synthesizable code>
4879 
           pavr_s2_pmdo_valid,
4880 
           -- </Non synthesizable code>
4881 
 
4882 
           pavr_iof_rampx_di,
4883 
           pavr_iof_rampx,
4884 
           pavr_xbpu
4885 
          )
4886 
      variable v_rampxwrrq_sel: std_logic_vector(1 downto 0);
4887 
      variable v_xrampx_inc : std_logic_vector(23 downto 0);
4888 
      variable v_xrampx_dec : std_logic_vector(23 downto 0);
4889 
   begin
4890 
      pavr_iof_rampx_wr <= '0';
4891 
      pavr_iof_rampx_di <= int_to_std_logic_vector(0, pavr_iof_rampx_di'length);
4892 
 
4893 
      v_xrampx_inc := (pavr_iof_rampx & pavr_xbpu) + 1;
4894 
      v_xrampx_dec := (pavr_iof_rampx & pavr_xbpu) - 1;
4895 
 
4896 
      v_rampxwrrq_sel := pavr_s5_ldstincrampx_xwr_rq & pavr_s5_ldstdecrampx_xwr_rq;
4897 
      case v_rampxwrrq_sel is
4898 
         -- No RAMPX write requests. Nothing to be done.
4899 
         when "00" =>
4900 
            null;
4901 
         -- Increment RAMPX:X request.
4902 
         when "10" =>
4903 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4904 
               if pavr_dm_bigger_than_64K='1' then
4905 
                  pavr_iof_rampx_wr <= '1';
4906 
                  pavr_iof_rampx_di <= v_xrampx_inc(23 downto 16);
4907 
               end if;
4908 
            end if;
4909 
         -- Decrement RAMPX:X request.
4910 
         when "01" =>
4911 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4912 
               if pavr_dm_bigger_than_64K='1' then
4913 
                  pavr_iof_rampx_wr <= '1';
4914 
                  pavr_iof_rampx_di <= v_xrampx_dec(23 downto 16);
4915 
               end if;
4916 
            end if;
4917 
         when others =>
4918 
            -- Multiple requests shouldn't happen.
4919 
            -- <Non synthesizable code>
4920 
            if pavr_s2_pmdo_valid='1' then
4921 
               assert false
4922 
                  report "RAMPX error."
4923 
                  severity warning;
4924 
            end if;
4925 
            -- </Non synthesizable code>
4926 
            null;
4927 
      end case;
4928 
   end process rampxwr_manager;
4929 
 
4930 
 
4931 
 
4932 
   -- RAMPY-related
4933 
   -- Set the signals:
4934 
   --    - pavr_iof_rampy_wr
4935 
   --    - pavr_iof_rampy_di
4936 
   rampywr_manager:
4937 
   process(pavr_s5_ldstincrampy_ywr_rq,
4938 
           pavr_s5_ldstdecrampy_ywr_rq,
4939 
 
4940 
           pavr_stall_s5,
4941 
           pavr_flush_s5,
4942 
 
4943 
           -- <Non synthesizable code>
4944 
           pavr_s2_pmdo_valid,
4945 
           -- </Non synthesizable code>
4946 
 
4947 
           pavr_iof_rampy_di,
4948 
           pavr_iof_rampy,
4949 
           pavr_ybpu
4950 
          )
4951 
      variable v_rampywrrq_sel: std_logic_vector(1 downto 0);
4952 
      variable v_yrampy_inc : std_logic_vector(23 downto 0);
4953 
      variable v_yrampy_dec : std_logic_vector(23 downto 0);
4954 
   begin
4955 
      pavr_iof_rampy_wr <= '0';
4956 
      pavr_iof_rampy_di <= int_to_std_logic_vector(0, pavr_iof_rampy_di'length);
4957 
 
4958 
      v_yrampy_inc := (pavr_iof_rampy & pavr_ybpu) + 1;
4959 
      v_yrampy_dec := (pavr_iof_rampy & pavr_ybpu) - 1;
4960 
 
4961 
      v_rampywrrq_sel := pavr_s5_ldstincrampy_ywr_rq & pavr_s5_ldstdecrampy_ywr_rq;
4962 
      case v_rampywrrq_sel is
4963 
         -- No RAMPY write requests. Nothing to be done.
4964 
         when "00" =>
4965 
            null;
4966 
         -- Increment RAMPY:Y request.
4967 
         when "10" =>
4968 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4969 
               if pavr_dm_bigger_than_64K='1' then
4970 
                  pavr_iof_rampy_wr <= '1';
4971 
                  pavr_iof_rampy_di <= v_yrampy_inc(23 downto 16);
4972 
               end if;
4973 
            end if;
4974 
         -- Decrement RAMPY:Y request.
4975 
         when "01" =>
4976 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
4977 
               if pavr_dm_bigger_than_64K='1' then
4978 
                  pavr_iof_rampy_wr <= '1';
4979 
                  pavr_iof_rampy_di <= v_yrampy_dec(23 downto 16);
4980 
               end if;
4981 
            end if;
4982 
         when others =>
4983 
            -- Multiple requests shouldn't happen.
4984 
            -- <Non synthesizable code>
4985 
            if pavr_s2_pmdo_valid='1' then
4986 
               assert false
4987 
                  report "RAMPY error."
4988 
                  severity warning;
4989 
            end if;
4990 
            -- </Non synthesizable code>
4991 
            null;
4992 
      end case;
4993 
   end process rampywr_manager;
4994 
 
4995 
 
4996 
 
4997 
   -- RAMPZ-related
4998 
   -- Set the signals:
4999 
   --    - pavr_iof_rampz_wr
5000 
   --    - pavr_iof_rampz_di
5001 
   rampzwr_manager:
5002 
   process(pavr_s5_ldstincrampz_zwr_rq,
5003 
           pavr_s5_ldstdecrampz_zwr_rq,
5004 
           pavr_s5_elpmincrampz_zwr_rq,
5005 
 
5006 
           pavr_stall_s5,
5007 
           pavr_flush_s5,
5008 
 
5009 
           -- <Non synthesizable code>
5010 
           pavr_s2_pmdo_valid,
5011 
           -- </Non synthesizable code>
5012 
 
5013 
           pavr_iof_rampz_di,
5014 
           pavr_iof_rampz,
5015 
           pavr_zbpu
5016 
          )
5017 
      variable v_rampzwrrq_sel: std_logic_vector(2 downto 0);
5018 
      variable v_zrampz_inc : std_logic_vector(23 downto 0);
5019 
      variable v_zrampz_dec : std_logic_vector(23 downto 0);
5020 
   begin
5021 
      pavr_iof_rampz_wr <= '0';
5022 
      pavr_iof_rampz_di <= int_to_std_logic_vector(0, pavr_iof_rampz_di'length);
5023 
 
5024 
      v_zrampz_inc := (pavr_iof_rampz & pavr_zbpu) + 1;
5025 
      v_zrampz_dec := (pavr_iof_rampz & pavr_zbpu) - 1;
5026 
 
5027 
      v_rampzwrrq_sel := pavr_s5_ldstincrampz_zwr_rq & pavr_s5_ldstdecrampz_zwr_rq & pavr_s5_elpmincrampz_zwr_rq;
5028 
      case v_rampzwrrq_sel is
5029 
         -- No RAMPZ write requests. Nothing to be done.
5030 
         when "000" =>
5031 
            null;
5032 
         -- Increment RAMPZ:Z request.
5033 
         when "100" =>
5034 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
5035 
               if pavr_dm_bigger_than_64K='1' then
5036 
                  pavr_iof_rampz_wr <= '1';
5037 
                  pavr_iof_rampz_di <= v_zrampz_inc(23 downto 16);
5038 
               end if;
5039 
            end if;
5040 
         -- Decrement RAMPZ:Z request.
5041 
         when "010" =>
5042 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
5043 
               if pavr_dm_bigger_than_64K='1' then
5044 
                  pavr_iof_rampz_wr <= '1';
5045 
                  pavr_iof_rampz_di <= v_zrampz_dec(23 downto 16);
5046 
               end if;
5047 
            end if;
5048 
         -- Increment RAMPZ:Z request from ELPM instruction.
5049 
         when "001" =>
5050 
            if pavr_stall_s5='0' and pavr_flush_s5='0' then
5051 
               pavr_iof_rampz_wr <= '1';
5052 
               pavr_iof_rampz_di <= v_zrampz_inc(23 downto 16);
5053 
            end if;
5054 
         when others =>
5055 
            -- Multiple requests shouldn't happen.
5056 
            -- <Non synthesizable code>
5057 
            if pavr_s2_pmdo_valid='1' then
5058 
               assert false
5059 
                  report "RAMPZ error."
5060 
                  severity warning;
5061 
            end if;
5062 
            -- </Non synthesizable code>
5063 
            null;
5064 
      end case;
5065 
   end process rampzwr_manager;
5066 
 
5067 
 
5068 
 
5069 
   -- RAMPD-related
5070 
   -- *** Void manager. No instruction needs to write RAMPD.
5071 
   rampdwr_manager:
5072 
   process(pavr_iof_rampd_di)
5073 
   begin
5074 
      pavr_iof_rampd_wr <= '0';
5075 
      pavr_iof_rampd_di <= int_to_std_logic_vector(0, pavr_iof_rampd_di'length);
5076 
   end process rampdwr_manager;
5077 
 
5078 
 
5079 
 
5080 
   -- EIND-related
5081 
   -- *** Void manager. No instruction needs to write EIND.
5082 
   eindwr_manager:
5083 
   process(pavr_iof_eind_di)
5084 
   begin
5085 
      pavr_iof_eind_wr <= '0';
5086 
      pavr_iof_eind_di <= int_to_std_logic_vector(0, pavr_iof_eind_di'length);
5087 
   end process eindwr_manager;
5088 
 
5089 
 
5090 
 
5091 
   -- ALU-related
5092 
   -- The ALU is not a potentially conflicting resource. There's no need to
5093 
   --    arbitrate requests to ALU. This section only takes care of setting ALU-
5094 
   --    related signals, that feed ALU inputs and connect its outputs to other
5095 
   --    modules.
5096 
   -- Set the signals:
5097 
   --    - pavr_s5_alu_op1
5098 
   --    - pavr_s5_alu_op2
5099 
   alu_manager:
5100 
   process(pavr_s5_alu_op1,
5101 
           pavr_s5_alu_op2,
5102 
           pavr_s5_alu_op1_hi8_sel,
5103 
           pavr_s5_op2bpu,
5104 
           pavr_s5_op1bpu,
5105 
           pavr_s5_alu_op2_sel,
5106 
           pavr_s5_op2bpu,
5107 
           pavr_s5_k8
5108 
          )
5109 
   begin
5110 
      pavr_s5_alu_op1 <= int_to_std_logic_vector(0, pavr_s5_alu_op1'length);
5111 
      pavr_s5_alu_op2 <= int_to_std_logic_vector(0, pavr_s5_alu_op2'length);
5112 
 
5113 
      case pavr_s5_alu_op1_hi8_sel is
5114 
         when pavr_alu_op1_hi8_sel_zero =>
5115 
            pavr_s5_alu_op1(15 downto 8) <= int_to_std_logic_vector(0, 8);
5116 
         when others =>
5117 
            pavr_s5_alu_op1(15 downto 8) <= pavr_s5_op2bpu;
5118 
      end case;
5119 
 
5120 
      pavr_s5_alu_op1( 7 downto 0) <= pavr_s5_op1bpu;
5121 
 
5122 
      case pavr_s5_alu_op2_sel is
5123 
         when pavr_alu_op2_sel_op2bpu =>
5124 
            pavr_s5_alu_op2 <= pavr_s5_op2bpu;
5125 
         when pavr_alu_op2_sel_k8 =>
5126 
            pavr_s5_alu_op2 <= pavr_s5_k8;
5127 
         when pavr_alu_op2_sel_1 =>
5128 
            pavr_s5_alu_op2 <= int_to_std_logic_vector(1, 8);
5129 
         when others =>
5130 
            pavr_s5_alu_op2 <= int_to_std_logic_vector(-1, 8);
5131 
      end case;
5132 
 
5133 
   end process alu_manager;
5134 
 
5135 
 
5136 
 
5137 
   -- DACU read and write-related
5138 
   -- Set the signals:
5139 
   --    - pavr_s5_dacu_rfrd1_rq
5140 
   --    - pavr_s5_dacust_rf_addr
5141 
   --    - pavr_s5_dacu_rfwr_rq
5142 
   --    - pavr_s5_dacu_rfwr_di
5143 
   --
5144 
   --    - pavr_s5_dacu_iof_rq
5145 
   --    - pavr_s5_dacu_iof_addr
5146 
   --    - pavr_s5_dacu_iof_opcode
5147 
   --    - pavr_s5_dacu_iofwr_di
5148 
   --
5149 
   --    - pavr_s5_dacu_dmrd_rq
5150 
   --    - pavr_s5_dacu_dm_addr
5151 
   --    - pavr_s5_dacu_dmwr_rq
5152 
   --    - pavr_s5_dacu_dmwr_di
5153 
   --
5154 
   --    - pavr_s5_dacust_bpr0wr_rq
5155 
   --
5156 
   --    - pavr_s5_dacudo_sel
5157 
   --    - pavr_s6_dacudo_sel
5158 
   --
5159 
   --    - pavr_dacu_do
5160 
   dacu_manager:
5161 
   process(
5162 
           -- DACU read-related requests
5163 
           pavr_s5_x_dacurd_rq, pavr_s5_y_dacurd_rq, pavr_s5_z_dacurd_rq,
5164 
           pavr_s5_sp_dacurd_rq,
5165 
           pavr_s5_k16_dacurd_rq,
5166 
           pavr_s5_pchi8_dacurd_rq, pavr_s51_pcmid8_dacurd_rq, pavr_s52_pclo8_dacurd_rq,
5167 
 
5168 
           -- DACU write-related requests
5169 
           pavr_s5_x_dacuwr_rq, pavr_s5_y_dacuwr_rq, pavr_s5_z_dacuwr_rq,
5170 
           pavr_s5_sp_dacuwr_rq,
5171 
           pavr_s5_k16_dacuwr_rq,
5172 
           pavr_s5_pclo8_dacuwr_rq, pavr_s51_pcmid8_dacuwr_rq, pavr_s52_pchi8_dacuwr_rq,
5173 
 
5174 
           -- <Non synthesizable code>
5175 
           pavr_s2_pmdo_valid,
5176 
           -- </Non synthesizable code>
5177 
 
5178 
           pavr_xbpu,
5179 
           pavr_ybpu,
5180 
           pavr_zbpu,
5181 
           pavr_s5_dacust_rf_addr,
5182 
           pavr_s5_dacu_rfwr_di,
5183 
           pavr_s5_dacu_iof_addr,
5184 
           pavr_s5_dacu_iofwr_di,
5185 
           pavr_s5_dacu_dm_addr,
5186 
           pavr_s5_dacu_dmwr_di,
5187 
           pavr_s5_dacu_iof_opcode,
5188 
           pavr_s5_dacudo_sel,
5189 
           pavr_dacu_do,
5190 
           pavr_s4_dacu_q,
5191 
           pavr_iof_rampx,
5192 
           pavr_iof_rampy,
5193 
           pavr_iof_rampz,
5194 
           pavr_iof_spl,
5195 
           pavr_iof_sph,
5196 
           pavr_s5_k16,
5197 
           pavr_iof_rampd,
5198 
           pavr_s5_rf_dacu_q,
5199 
           pavr_s5_iof_dacu_q,
5200 
           pavr_s5_dm_dacu_q,
5201 
           pavr_s6_dacudo_sel,
5202 
           pavr_s5_op1bpu,
5203 
           pavr_s5_pc,
5204 
           pavr_rf_rd1_do,
5205 
           pavr_iof_do,
5206 
           pavr_dm_do
5207 
          )
5208 
      variable tmpv_rd   : std_logic_vector(7 downto 0);
5209 
      variable tmpv_wr   : std_logic_vector(7 downto 0);
5210 
      variable tmpv_rdwr : std_logic_vector(7 downto 0);
5211 
      variable v_dacu_wr_di: std_logic_vector(7 downto 0);
5212 
      variable v_pavr_s5_dacu_ptr : std_logic_vector(23 downto 0);
5213 
      variable v_pavr_s5_rf_dacu_addrtest  : std_logic_vector(24 downto 0);
5214 
      variable v_pavr_s5_iof_dacu_addrtest : std_logic_vector(24 downto 0);
5215 
      variable v_pavr_s5_dm_dacu_addrtest  : std_logic_vector(24 downto 0);
5216 
      variable v_pavr_dacu_device_sel : std_logic_vector(pavr_dacu_device_sel_w - 1 downto 0);
5217 
   begin
5218 
      pavr_s5_dacu_rfrd1_rq <= '0';
5219 
      pavr_s5_dacu_rfwr_rq  <= '0';
5220 
      pavr_s5_dacu_rfwr_di <= int_to_std_logic_vector(0, pavr_s5_dacu_rfwr_di'length);
5221 
      pavr_s5_dacu_iof_rq <= '0';
5222 
      pavr_s5_dacu_iofwr_di <= int_to_std_logic_vector(0, pavr_s5_dacu_iofwr_di'length);
5223 
      pavr_s5_dacu_dmrd_rq <= '0';
5224 
      pavr_s5_dacu_dmwr_rq <= '0';
5225 
      pavr_s5_dacu_dmwr_di <= int_to_std_logic_vector(0, pavr_s5_dacu_dmwr_di'length);
5226 
      pavr_s5_dacust_bpr0wr_rq <= '0';
5227 
      pavr_s5_dacust_rf_addr  <= int_to_std_logic_vector(0, pavr_s5_dacust_rf_addr'length);
5228 
      pavr_s5_dacu_iof_addr <= int_to_std_logic_vector(0, pavr_s5_dacu_iof_addr'length);
5229 
      pavr_s5_dacu_dm_addr  <= int_to_std_logic_vector(0, pavr_s5_dacu_dm_addr'length);
5230 
      pavr_s5_dacu_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_dacu_iof_opcode'length);
5231 
      pavr_s5_dacudo_sel <= int_to_std_logic_vector(0, pavr_s5_dacudo_sel'length);
5232 
      pavr_dacu_do <= int_to_std_logic_vector(0, pavr_dacu_do'length);
5233 
 
5234 
      pavr_s4_iof_dacu_q <= pavr_s4_dacu_q - 32;
5235 
      pavr_s4_dm_dacu_q  <= pavr_s4_dacu_q - 96;
5236 
 
5237 
      tmpv_rd := int_to_std_logic_vector(0, tmpv_rd'length);
5238 
      tmpv_wr := int_to_std_logic_vector(0, tmpv_wr'length);
5239 
      tmpv_rdwr := int_to_std_logic_vector(0, tmpv_rdwr'length);
5240 
      v_dacu_wr_di := int_to_std_logic_vector(0, v_dacu_wr_di'length);
5241 
      v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, v_pavr_s5_dacu_ptr'length);
5242 
      v_pavr_s5_rf_dacu_addrtest  := int_to_std_logic_vector(0, v_pavr_s5_rf_dacu_addrtest'length);
5243 
      v_pavr_s5_iof_dacu_addrtest := int_to_std_logic_vector(0, v_pavr_s5_iof_dacu_addrtest'length);
5244 
      v_pavr_s5_dm_dacu_addrtest  := int_to_std_logic_vector(0, v_pavr_s5_dm_dacu_addrtest'length);
5245 
      v_pavr_dacu_device_sel := int_to_std_logic_vector(0, v_pavr_dacu_device_sel'length);
5246 
 
5247 
      -- This vector holds the DACU read requests.
5248 
      tmpv_rd := pavr_s5_x_dacurd_rq & pavr_s5_y_dacurd_rq & pavr_s5_z_dacurd_rq &
5249 
                 pavr_s5_sp_dacurd_rq &
5250 
                 pavr_s5_k16_dacurd_rq &
5251 
                 pavr_s5_pchi8_dacurd_rq & pavr_s51_pcmid8_dacurd_rq & pavr_s52_pclo8_dacurd_rq;
5252 
      -- This vector holds the DACU write requests.
5253 
      tmpv_wr := pavr_s5_x_dacuwr_rq & pavr_s5_y_dacuwr_rq & pavr_s5_z_dacuwr_rq &
5254 
                 pavr_s5_sp_dacuwr_rq &
5255 
                 pavr_s5_k16_dacuwr_rq &
5256 
                 pavr_s5_pclo8_dacuwr_rq & pavr_s51_pcmid8_dacuwr_rq & pavr_s52_pchi8_dacuwr_rq;
5257 
      -- This vector holds the requests to DACU access (for write or read). Note
5258 
      --    that (coincidentaly or not) all the DACU access requests for read have
5259 
      --    a mirror pair for write access. OR-ing read with write access requests
5260 
      --    (taking care to pair correctly read and write mirror images) will
5261 
      --    result in a pattern that can be used to select the proper source for
5262 
      --    the DACU address, when computing the Unified Memory address.
5263 
      tmpv_rdwr := tmpv_rd or tmpv_wr;
5264 
      case tmpv_rdwr is
5265 
         -- No DACU access requests.
5266 
         when "00000000" =>
5267 
            v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, v_pavr_s5_dacu_ptr'length);
5268 
         -- DACU access requests from/to Unified Memory address given by X (and RAMPX) pointer register.
5269 
         when "10000000" =>
5270 
            if pavr_dm_bigger_than_256='0' then
5271 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_xbpu(7 downto 0);
5272 
            elsif pavr_dm_bigger_than_64K='0' then
5273 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_xbpu;
5274 
            else
5275 
               v_pavr_s5_dacu_ptr := pavr_iof_rampx & pavr_xbpu;
5276 
            end if;
5277 
         -- DACU access requests from/to Unified Memory address given by Y (and RAMPY) pointer register.
5278 
         when "01000000" =>
5279 
            if pavr_dm_bigger_than_256='0' then
5280 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_ybpu(7 downto 0);
5281 
            elsif pavr_dm_bigger_than_64K='0' then
5282 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_ybpu;
5283 
            else
5284 
               v_pavr_s5_dacu_ptr := pavr_iof_rampy & pavr_ybpu;
5285 
            end if;
5286 
         -- DACU access requests from/to Unified Memory address given by Z (and RAMPZ) pointer register.
5287 
         when "00100000" =>
5288 
            if pavr_dm_bigger_than_256='0' then
5289 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_zbpu(7 downto 0);
5290 
            elsif pavr_dm_bigger_than_64K='0' then
5291 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_zbpu;
5292 
            else
5293 
               v_pavr_s5_dacu_ptr := pavr_iof_rampz & pavr_zbpu;
5294 
            end if;
5295 
         -- DACU access requests from/to Unified Memory address given by SP.
5296 
         when "00010000" |
5297 
              "00000100" | "00000010" | "00000001" =>
5298 
            if pavr_dm_bigger_than_256='0' then
5299 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_iof_spl;
5300 
            else
5301 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_iof_sph & pavr_iof_spl;
5302 
            end if;
5303 
         -- DACU access requests from/to Unified Memory address given by a 16 bit constant (pavr_s5_k16).
5304 
         when "00001000" =>
5305 
            if pavr_dm_bigger_than_256='0' then
5306 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_s5_k16(7 downto 0);
5307 
            elsif pavr_dm_bigger_than_64K='0' then
5308 
               v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_s5_k16;
5309 
            else
5310 
               v_pavr_s5_dacu_ptr := pavr_iof_rampd & pavr_s5_k16;
5311 
            end if;
5312 
         when others =>
5313 
            -- Multiple requests shouldn't happen.
5314 
            -- <Non synthesizable code>
5315 
            if pavr_s2_pmdo_valid='1' then
5316 
               assert false
5317 
                  report "DACU error."
5318 
                  severity warning;
5319 
            end if;
5320 
            -- </Non synthesizable code>
5321 
            null;
5322 
 
5323 
      end case;
5324 
 
5325 
      v_pavr_s5_rf_dacu_addrtest  := v_pavr_s5_dacu_ptr + sign_extend(pavr_s5_rf_dacu_q, 25);
5326 
      v_pavr_s5_iof_dacu_addrtest := v_pavr_s5_dacu_ptr + sign_extend(pavr_s5_iof_dacu_q, 25);
5327 
      v_pavr_s5_dm_dacu_addrtest  := v_pavr_s5_dacu_ptr + sign_extend(pavr_s5_dm_dacu_q, 25);
5328 
 
5329 
      -- If none of the 3 tests below results in positive addresses, use DM.
5330 
      v_pavr_dacu_device_sel := pavr_dacu_device_sel_dm;
5331 
      -- Test which device to use, RF/IOF/DM. Remember that the Unified Memory is composed of these 3 entities.
5332 
      if v_pavr_s5_rf_dacu_addrtest(24)='0' then
5333 
         v_pavr_dacu_device_sel := pavr_dacu_device_sel_rf;
5334 
      end if;
5335 
      if v_pavr_s5_iof_dacu_addrtest(24)='0' then
5336 
         v_pavr_dacu_device_sel := pavr_dacu_device_sel_iof;
5337 
      end if;
5338 
      if v_pavr_s5_dm_dacu_addrtest(24)='0' then
5339 
         v_pavr_dacu_device_sel := pavr_dacu_device_sel_dm;
5340 
      end if;
5341 
      -- Now we know what device to access during UM requests. That info is stored in `v_pavr_dacu_device_sel'.
5342 
 
5343 
      -- Manage DACU read requests.
5344 
      if tmpv_rd/="00000000" then
5345 
         case v_pavr_dacu_device_sel is
5346 
            -- UM read request is decoded into RF read port 1 access request.
5347 
            when pavr_dacu_device_sel_rf =>
5348 
               pavr_s5_dacu_rfrd1_rq   <= '1';
5349 
               pavr_s5_dacust_rf_addr  <= v_pavr_s5_rf_dacu_addrtest(4 downto 0);
5350 
               pavr_s5_dacudo_sel      <= pavr_dacudo_sel_rfrd1do;
5351 
            -- UM read request is decoded into IOF port access request.
5352 
            when pavr_dacu_device_sel_iof =>
5353 
               pavr_s5_dacu_iof_rq     <= '1';
5354 
               pavr_s5_dacu_iof_addr   <= v_pavr_s5_iof_dacu_addrtest(5 downto 0);
5355 
               pavr_s5_dacu_iof_opcode <= pavr_iof_opcode_rdbyte;
5356 
               pavr_s5_dacudo_sel      <= pavr_dacudo_sel_iofdo;
5357 
            -- UM read request is decoded into DM port access request.
5358 
            when others =>
5359 
               pavr_s5_dacu_dmrd_rq <= '1';
5360 
               pavr_s5_dacu_dm_addr <= v_pavr_s5_dm_dacu_addrtest(23 downto 0);
5361 
               pavr_s5_dacudo_sel   <= pavr_dacudo_sel_dmdo;
5362 
         end case;
5363 
      end if;
5364 
 
5365 
      -- DACU data out. Select data out from proper device (RF/IOF/DM).
5366 
      case pavr_s6_dacudo_sel is
5367 
         -- *** Bypass shadow protocol.
5368 
         when pavr_dacudo_sel_rfrd1do =>
5369 
            --if pavr_rf_do_shadow_active='0' then
5370 
               pavr_dacu_do   <= pavr_rf_rd1_do;
5371 
            --else
5372 
            --   pavr_dacu_do <= pavr_rf_rd1_do_shadow;
5373 
            --end if;
5374 
         when pavr_dacudo_sel_iofdo =>
5375 
            --if pavr_iof_do_shadow_active='0' then
5376 
               pavr_dacu_do   <= pavr_iof_do;
5377 
            --else
5378 
            --   pavr_dacu_do <= pavr_iof_do_shadow;
5379 
            --end if;
5380 
         -- When pavr_dacudo_sel_dmdo
5381 
         when others =>
5382 
            --if pavr_dm_do_shadow_active='0' then
5383 
               pavr_dacu_do   <= pavr_dm_do;
5384 
            --else
5385 
            --   pavr_dacu_do <= pavr_dm_do_shadow;
5386 
            --end if;
5387 
      end case;
5388 
 
5389 
      -- Manage DACU write requests.
5390 
      case tmpv_wr is
5391 
         -- Nothing to be done.
5392 
         when "00000000" =>
5393 
            null;
5394 
         -- X, Y, Z, SP or k16 DACUWR request
5395 
         when "10000000" | "01000000" | "00100000" | "00010000"  | "00001000"=>
5396 
            v_dacu_wr_di := pavr_s5_op1bpu;
5397 
         -- SP DACUWR request, data in = pclo8
5398 
         when  "00000100" =>
5399 
            v_dacu_wr_di := pavr_s5_pc(7 downto 0);
5400 
         -- SP DACUWR request, data in = pcmid8
5401 
         when  "00000010" =>
5402 
            v_dacu_wr_di := pavr_s5_pc(15 downto 8);
5403 
         -- SP DACUWR request, data in = pchi8
5404 
         when  others =>
5405 
            v_dacu_wr_di := "00" & pavr_s5_pc(21 downto 16);
5406 
      end case;
5407 
      if tmpv_wr/="00000000" then
5408 
         case v_pavr_dacu_device_sel is
5409 
            -- UM write request is decoded into RF write port access request.
5410 
            when pavr_dacu_device_sel_rf =>
5411 
               pavr_s5_dacu_rfwr_rq       <= '1';
5412 
               pavr_s5_dacust_rf_addr     <= v_pavr_s5_rf_dacu_addrtest(4 downto 0);
5413 
               pavr_s5_dacust_bpr0wr_rq   <= '1';                          -- *** Take care to also update BPU. Note that it will happen next clock.
5414 
               pavr_s5_dacu_rfwr_di       <= v_dacu_wr_di;
5415 
            -- UM write request is decoded into IOF port access request.
5416 
            when pavr_dacu_device_sel_iof =>
5417 
               pavr_s5_dacu_iof_rq     <= '1';
5418 
               pavr_s5_dacu_iof_addr   <= v_pavr_s5_iof_dacu_addrtest(5 downto 0);
5419 
               pavr_s5_dacu_iof_opcode <= pavr_iof_opcode_wrbyte;
5420 
               pavr_s5_dacu_iofwr_di   <= v_dacu_wr_di;
5421 
            -- UM write request is decoded into DM port access request.
5422 
            when others =>
5423 
               pavr_s5_dacu_dmwr_rq <= '1';
5424 
               pavr_s5_dacu_dm_addr <= v_pavr_s5_dm_dacu_addrtest(23 downto 0);
5425 
               pavr_s5_dacu_dmwr_di <= v_dacu_wr_di;
5426 
         end case;
5427 
      end if;
5428 
   end process dacu_manager;
5429 
 
5430 
 
5431 
 
5432 
   -- DM-related
5433 
   -- Set the signals:
5434 
   --    - pavr_dm_wr
5435 
   --    - pavr_dm_addr
5436 
   --    - pavr_dm_di
5437 
   dm_manager:
5438 
   process(pavr_s5_dacu_dmrd_rq,
5439 
           pavr_s5_dacu_dmwr_rq,
5440 
 
5441 
           -- <Non synthesizable code>
5442 
           pavr_s2_pmdo_valid,
5443 
           -- </Non synthesizable code>
5444 
 
5445 
           pavr_dm_addr,
5446 
           pavr_dm_di,
5447 
           pavr_s5_dacu_dm_addr,
5448 
           pavr_s5_dacu_dmwr_di
5449 
          )
5450 
      variable v_dmrq_sel: std_logic_vector(1 downto 0);
5451 
   begin
5452 
      pavr_dm_wr     <= '0';
5453 
      pavr_dm_addr   <= int_to_std_logic_vector(0, pavr_dm_addr'length);
5454 
      pavr_dm_di     <= int_to_std_logic_vector(0, pavr_dm_di'length);
5455 
 
5456 
      -- Note that DACU is the only unit that requests read/write accesses to DM.
5457 
      v_dmrq_sel := pavr_s5_dacu_dmrd_rq & pavr_s5_dacu_dmwr_rq;
5458 
      case v_dmrq_sel is
5459 
         -- No DM access requests. Nothing to be done.
5460 
         when "00" =>
5461 
            null;
5462 
         -- Read DM request
5463 
         when "10" =>
5464 
            pavr_dm_wr     <= '0';
5465 
            pavr_dm_addr   <= pavr_s5_dacu_dm_addr(pavr_dm_addr'length - 1 downto 0);
5466 
            pavr_dm_di     <= int_to_std_logic_vector(0, pavr_dm_di'length);
5467 
         -- Write DM request
5468 
         when "01" =>
5469 
            pavr_dm_wr     <= '1';
5470 
            pavr_dm_addr   <= pavr_s5_dacu_dm_addr(pavr_dm_addr'length - 1 downto 0);
5471 
            pavr_dm_di     <= pavr_s5_dacu_dmwr_di;
5472 
         when others =>
5473 
            -- Multiple requests shouldn't happen.
5474 
            -- <Non synthesizable code>
5475 
            if pavr_s2_pmdo_valid='1' then
5476 
               assert false
5477 
                  report "Data Memory error."
5478 
                  severity warning;
5479 
            end if;
5480 
            -- </Non synthesizable code>
5481 
            null;
5482 
      end case;
5483 
   end process dm_manager;
5484 
 
5485 
 
5486 
 
5487 
   -- PM access-related
5488 
   -- Load PC here. Some PM access requests modify the PC, others don't. The only
5489 
   --    PM requests that don't modify the PC are the loads from PM (LPM and ELPM
5490 
   --    instructions). The other requests correspond to instructions that
5491 
   --    want to modify the instruction flow, thus modify the PC (jumps, branches
5492 
   --    calls, returns).
5493 
   -- Set the signals:
5494 
   --    - pavr_pm_addr_int
5495 
   --    - next_pavr_s1_pc
5496 
   --    - next_pavr_s2_pmdo_valid
5497 
   pm_manager:
5498 
   process(pavr_s5_lpm_pm_rq,
5499 
           pavr_s5_elpm_pm_rq,
5500 
           pavr_s4_z_pm_rq,
5501 
           pavr_s4_zeind_pm_rq,
5502 
           pavr_s4_k22abs_pm_rq,
5503 
           pavr_s4_k12rel_pm_rq,
5504 
           pavr_s6_branch_pm_rq,
5505 
           pavr_s6_skip_pm_rq,
5506 
           pavr_s61_skip_pm_rq,
5507 
           pavr_s4_k22int_pm_rq,
5508 
           pavr_s54_ret_pm_rq,
5509 
 
5510 
           pavr_s4_hwrq_en,
5511 
           pavr_s5_hwrq_en,
5512 
           pavr_s6_hwrq_en,
5513 
           pavr_s61_hwrq_en,
5514 
 
5515 
           pavr_stall_s1,
5516 
           pavr_stall_s2,
5517 
           pavr_flush_s2,
5518 
           pavr_s2_pc,
5519 
           pavr_s3_pc,
5520 
 
5521 
           -- <Non synthesizable code>
5522 
           pavr_s2_pmdo_valid,
5523 
           -- </Non synthesizable code>
5524 
 
5525 
           pavr_grant_control_flow_access,
5526 
           pavr_pm_do_shadow_active,
5527 
           pavr_pm_do_shadow,
5528 
           pavr_pm_do,
5529 
 
5530 
           pavr_zbpu,
5531 
           pavr_s1_pc,
5532 
           pavr_s4_k12,
5533 
           pavr_s4_pc,
5534 
           pavr_iof_rampz,
5535 
           pavr_iof_eind,
5536 
           pavr_s4_k6,
5537 
           pavr_s3_instr,
5538 
           pavr_s6_branch_pc,
5539 
           pavr_s4_k22int,
5540 
           pavr_s52_retpchi8,
5541 
           pavr_s53_retpcmid8,
5542 
           pavr_s54_retpclo8,
5543 
           pavr_pm_addr_int
5544 
          )
5545 
      variable v_pmrq_sel: std_logic_vector(10 downto 0);
5546 
      variable v_pavr_pc_sel: std_logic;
5547 
 
5548 
      variable v_22b_op1:              std_logic_vector(22 downto 0);
5549 
      variable v_22b_op2:              std_logic_vector(22 downto 0);
5550 
      variable v_pavr_pc_k12rel_23b:   std_logic_vector(22 downto 0);
5551 
      variable v_grant_s2_pm_access:        std_logic;
5552 
      --variable pavr_grant_control_flow_access: std_logic;
5553 
      variable v_freeze_control_flow:       std_logic;
5554 
      variable v_instr32bits_tmp1:  std_logic_vector(9 downto 0);
5555 
      variable v_instr32bits_tmp2:  std_logic_vector(8 downto 0);
5556 
      variable v_instr32bits:       std_logic;
5557 
 
5558 
   begin
5559 
      -- Default values:
5560 
      --    - PM addr = PC
5561 
      --    - next PC = crt PC + 1.
5562 
      --    - don't grant access to control flow (enabled later if requested)
5563 
      --    - grant PM access (disabled later if the instruction doesn't
5564 
      --       explicitely requests it)
5565 
      --    - don't freeze control flow (enabled later if a LPM family
5566 
      --       requests PM access)
5567 
      pavr_pm_addr_int <= pavr_s1_pc;
5568 
      v_pavr_pc_sel := pavr_pc_sel_inc;
5569 
      v_grant_s2_pm_access := '1';
5570 
      v_freeze_control_flow := '0';
5571 
      pavr_grant_control_flow_access <= '0';
5572 
 
5573 
      -- Detect if the instruction to stall is 16 bits or 32 bits wide.
5574 
      -- Is it a LDS or a STS?
5575 
      v_instr32bits_tmp1 := pavr_s3_instr(15 downto 10) & pavr_s3_instr(3 downto 0);
5576 
      -- Is it a JMP or a CALL?
5577 
      v_instr32bits_tmp2 := pavr_s3_instr(15 downto  9) & pavr_s3_instr(3 downto 2);
5578 
      if v_instr32bits_tmp1="1001000000" or v_instr32bits_tmp2="100101011" then
5579 
         v_instr32bits := '1';
5580 
      else
5581 
         v_instr32bits := '0';
5582 
      end if;
5583 
 
5584 
      -- Add 12 bits offset with current instruction's PC and with 1. The result
5585 
      --    is the relative address needed by intructions RJMP/RCALL.
5586 
      v_22b_op1(0) := '1';
5587 
      v_22b_op2(0) := '1';
5588 
      if pavr_s6_branch_pm_rq='1' then
5589 
         if v_instr32bits ='0' then
5590 
            v_22b_op1(22 downto 1) := sign_extend("01", 22);
5591 
            v_22b_op2(22 downto 1) := pavr_s4_pc;
5592 
         else
5593 
            v_22b_op1(22 downto 1) := sign_extend("00", 22);
5594 
            v_22b_op2(22 downto 1) := pavr_s4_pc;
5595 
         end if;
5596 
      else
5597 
         v_22b_op1(22 downto 1) := sign_extend(pavr_s4_k12, 22);
5598 
         v_22b_op2(22 downto 1) := pavr_s4_pc;
5599 
      end if;
5600 
      v_pavr_pc_k12rel_23b := v_22b_op1 + v_22b_op2;
5601 
 
5602 
      v_pmrq_sel := (pavr_s5_lpm_pm_rq    and pavr_s5_hwrq_en) &
5603 
                    (pavr_s5_elpm_pm_rq   and pavr_s5_hwrq_en) &
5604 
                    (pavr_s4_z_pm_rq      and pavr_s4_hwrq_en) &
5605 
                    (pavr_s4_zeind_pm_rq  and pavr_s4_hwrq_en) &
5606 
                    (pavr_s4_k22abs_pm_rq and pavr_s4_hwrq_en) &
5607 
                    (pavr_s4_k12rel_pm_rq and pavr_s4_hwrq_en) &
5608 
                    (pavr_s6_branch_pm_rq and pavr_s6_hwrq_en) &
5609 
                    (pavr_s6_skip_pm_rq   and pavr_s6_hwrq_en) &
5610 
                     pavr_s61_skip_pm_rq                       &
5611 
                    (pavr_s4_k22int_pm_rq and pavr_s4_hwrq_en) &
5612 
                     pavr_s54_ret_pm_rq;
5613 
      case v_pmrq_sel is
5614 
         -- No PM access requests. Don't grant access to PM.
5615 
         when "00000000000" =>
5616 
            v_grant_s2_pm_access := '0';
5617 
         -- LPM PM request. Freeze PC.
5618 
         when "10000000000" =>
5619 
            -- Only take action if permitted by older instructions.
5620 
            -- *** Note that the condition is stall enabled in s6, not s5. That's
5621 
            --    because LPM stalls s5 at the same time it tries to read PM.
5622 
            if pavr_s6_hwrq_en='1' then
5623 
               pavr_pm_addr_int <= int_to_std_logic_vector(0, 6) & '0' & pavr_zbpu(15 downto 1);
5624 
               v_pavr_pc_sel := pavr_pc_sel_same;
5625 
               v_freeze_control_flow := '1';
5626 
            end if;
5627 
         -- ELPM PM request. Freeze PC.
5628 
         when "01000000000" =>
5629 
            -- *** Note that the condition is stall enabled in s6, not s5. That's
5630 
            --    because ELPM stalls  s5 at the same time it tries to read PM.
5631 
            if pavr_s6_hwrq_en='1' then
5632 
               pavr_pm_addr_int <= '0' & pavr_iof_rampz(5 downto 0) & pavr_zbpu(15 downto 1);
5633 
               v_pavr_pc_sel := pavr_pc_sel_same;
5634 
               v_freeze_control_flow := '1';
5635 
            end if;
5636 
         -- IJMP/ICALL PM request.
5637 
         when "00100000000" =>
5638 
            if pavr_s4_hwrq_en='1' then
5639 
               pavr_pm_addr_int <= int_to_std_logic_vector(0, 6) & pavr_zbpu;
5640 
               pavr_grant_control_flow_access <= '1';
5641 
            end if;
5642 
         -- EIJMP/EICALL PM request.
5643 
         when "00010000000" =>
5644 
            if pavr_s4_hwrq_en='1' then
5645 
               pavr_pm_addr_int <= pavr_iof_eind(5 downto 0) & pavr_zbpu;
5646 
               pavr_grant_control_flow_access <= '1';
5647 
            end if;
5648 
         -- JMP/CALL PM request.
5649 
         when "00001000000" =>
5650 
            if pavr_s4_hwrq_en='1' then
5651 
               pavr_pm_addr_int <= pavr_s4_k6 & pavr_s3_instr;
5652 
               pavr_grant_control_flow_access <= '1';
5653 
            end if;
5654 
         -- RJMP/RCALL PM request.
5655 
         when "00000100000" =>
5656 
            if pavr_s4_hwrq_en='1' then
5657 
               pavr_pm_addr_int <= v_pavr_pc_k12rel_23b(22 downto 1);
5658 
               pavr_grant_control_flow_access <= '1';
5659 
            end if;
5660 
         -- Branch PM requests (SBRC, SBRS instructions).
5661 
         when "00000010000" =>
5662 
            if pavr_s6_hwrq_en='1' then
5663 
               pavr_pm_addr_int <= pavr_s6_branch_pc;
5664 
               pavr_grant_control_flow_access <= '1';
5665 
            end if;
5666 
         -- Skip PM requests (CPSE, SBRC, SBRS instructions).
5667 
         when "00000001000" =>
5668 
            if pavr_s6_hwrq_en='1' then
5669 
               pavr_pm_addr_int <= v_pavr_pc_k12rel_23b(22 downto 1);
5670 
               pavr_grant_control_flow_access <= '1';
5671 
            end if;
5672 
         -- Skip PM requests (SBIC, SBIS instructions).
5673 
         when "00000000100" =>
5674 
            if pavr_s61_hwrq_en='1' then
5675 
               pavr_pm_addr_int <= v_pavr_pc_k12rel_23b(22 downto 1);
5676 
               pavr_grant_control_flow_access <= '1';
5677 
            end if;
5678 
         -- Interrupt PM requests. No instruction requests this. Only the
5679 
         --    Interrupt Manager can request this.
5680 
         when "00000000010" =>
5681 
            -- !!! Any condition here?
5682 
            pavr_pm_addr_int <= pavr_s4_k22int;
5683 
            pavr_grant_control_flow_access <= '1';
5684 
         -- RET/RETI PM requests.
5685 
         when "00000000001" =>
5686 
            pavr_pm_addr_int <= pavr_s52_retpchi8(5 downto 0) & pavr_s53_retpcmid8 & pavr_s54_retpclo8;
5687 
            pavr_grant_control_flow_access <= '1';
5688 
         when others =>
5689 
            -- <Non synthesizable code>
5690 
            if pavr_s2_pmdo_valid='1' then
5691 
               assert false
5692 
                  report "Program Memory error."
5693 
                  severity warning;
5694 
            end if;
5695 
            -- </Non synthesizable code>
5696 
            null;
5697 
      end case;
5698 
 
5699 
      -- Set PM address.
5700 
      -- Take care of potential direct PM access requests placed by control or LPM
5701 
      --    instructions.
5702 
      if v_grant_s2_pm_access='0' and pavr_stall_s1='1' then
5703 
         pavr_pm_addr_int <= pavr_s1_pc;
5704 
      end if;
5705 
 
5706 
      -- Here is an instruction register-related code that's a workaround on an
5707 
      --    after-reset false instruction register initializing.
5708 
      -- During reset, PM was read. When reset lines are released, the controller
5709 
      --    didn't wait to read the first instruction (at address 0). It
5710 
      --    considered it already read during reset. Wrong. This corrects this
5711 
      --    behavior.
5712 
      if pavr_stall_s1='0' then
5713 
         next_pavr_s2_pmdo_valid <= '1';
5714 
      else
5715 
         next_pavr_s2_pmdo_valid <= pavr_s2_pmdo_valid;
5716 
      end if;
5717 
 
5718 
      -- Now we know what to do with the PC. Do it.
5719 
      if pavr_grant_control_flow_access='1' then
5720 
         next_pavr_s1_pc <= pavr_pm_addr_int + 1;
5721 
      else
5722 
         if pavr_stall_s1='1' then
5723 
            next_pavr_s1_pc <= pavr_s1_pc;
5724 
         else
5725 
            if v_pavr_pc_sel=pavr_pc_sel_same then
5726 
               next_pavr_s1_pc <= pavr_s1_pc;
5727 
            else
5728 
               next_pavr_s1_pc <= pavr_pm_addr_int + 1;
5729 
            end if;
5730 
         end if;
5731 
      end if;
5732 
 
5733 
      -- pavr_s2_pc
5734 
      if pavr_grant_control_flow_access='1' then
5735 
         next_pavr_s2_pc <= pavr_pm_addr_int;
5736 
      else
5737 
         if pavr_stall_s1='1' then
5738 
            next_pavr_s2_pc <= pavr_s2_pc;
5739 
         else
5740 
            next_pavr_s2_pc <= pavr_s1_pc;
5741 
         end if;
5742 
      end if;
5743 
 
5744 
      -- pavr_s3_pc
5745 
      if pavr_stall_s2='1' then
5746 
         next_pavr_s3_pc <= pavr_s3_pc;
5747 
      else
5748 
         next_pavr_s3_pc <= pavr_s2_pc;
5749 
      end if;
5750 
 
5751 
      -- pavr_s3_instr (instruction register)
5752 
      if pavr_flush_s2='1' or pavr_s2_pmdo_valid='0' then
5753 
         next_pavr_s3_instr <= int_to_std_logic_vector(0, pavr_s3_instr'length);
5754 
      else
5755 
         if pavr_stall_s2='1' then
5756 
            next_pavr_s3_instr <= pavr_s3_instr;
5757 
         else
5758 
            if pavr_pm_do_shadow_active='0' then
5759 
               next_pavr_s3_instr <= pavr_pm_do;
5760 
            else
5761 
               next_pavr_s3_instr <= pavr_pm_do_shadow;
5762 
            end if;
5763 
         end if;
5764 
      end if;
5765 
 
5766 
   end process pm_manager;
5767 
 
5768 
 
5769 
 
5770 
   -- Stall and Flush Unit (SFU)
5771 
   -- The pipeline controls its own stall and flush status, through specific
5772 
   --    stall and flush-related request signals. These requests are sent to
5773 
   --    the SFU. The output of the SFU is a set of signals that directly
5774 
   --    control pipeline stages (a stall and flush control signals pair for
5775 
   --    each stage).
5776 
   -- The pipeline sets up 5 kinds of stall and flush-related requests:
5777 
   --    - stall request
5778 
   --       The SFU stalls *all* younger stages. However, by stalling-only, the
5779 
   --          current instruction is spawned into 2 instances. One of them must
5780 
   --          be killed (flushed). The the younger instance is killed (the
5781 
   --          previous stage is flushed).
5782 
   --       Thus, a nop is introduced in the pipeline *before* the instruction
5783 
   --          wavefront.
5784 
   --       If more than one stage requests a stall at the same time, the older
5785 
   --          one has priority (the younger one will be stalled along with the
5786 
   --          others). Only after that, the younger one will be ackowledged its
5787 
   --          stall by means of appropriate stall and flush control signals.
5788 
   --    - flush request
5789 
   --       The SFU simply flushes that stage.
5790 
   --       More than one flush can be acknolewdged at the same time, without
5791 
   --          competition.
5792 
   --    - branch request
5793 
   --       The SFU flushes about all stags (s2...s5) and requests
5794 
   --       the PC to be loaded with the relative jump address.
5795 
   --    - skip request
5796 
   --       Skips are processed the same way as branches. However, there are 2
5797 
   --       kinds of skips: one in stage s6 (requested by instructions CPSE,
5798 
   --       SBRC, SBRS) and one in stage s61 (SBIC, SBIS). Those active in s6
5799 
   --       also supplementary request stall and flush s6.
5800 
   --    - nop request
5801 
   --       The SFU stalls all younger instructions. The current instruction is
5802 
   --          spawned into 2 instances. The older instance is killed (the very
5803 
   --          same stage that requested the nop stage is flushed).
5804 
   --       Thus, a nop is introduced in the pipeline *after* the instruction
5805 
   --          wavefront.
5806 
   --       In order to do that, a micro-state machine is needed outside the
5807 
   --          pipeline, because otherwise that stage will undefinitely stall
5808 
   --          itself.
5809 
   -- Each pipeline stage has 2 kinds of control signals, that are generated by
5810 
   --    the SFU:
5811 
   --    - stall control
5812 
   --       All registers in this stage are instructed to remain unchanged
5813 
   --          (ignore `next...' signals that feed the registers in that
5814 
   --          stage, or mirror registers in previous stages). Also, all
5815 
   --          possible requests to hardware resources (such as RF, IOF, BPU,
5816 
   --          DACU, SREG, etc) are reseted (to 0).
5817 
   --    - flush control
5818 
   --       All registers in this stage are reseted (to 0), to a most "benign"
5819 
   --          state (a nop). Also, all requests to hardware resources are
5820 
   --          reseted.
5821 
   --
5822 
   -- SFU requests:
5823 
   --    - stall
5824 
   --    - flush
5825 
   --    - skip
5826 
   --    - branch
5827 
   --    - nop
5828 
   -- SFU requests influence the way that hardware resources are granted to
5829 
   --    pipeline stages. That way is given by the SFU rule below.
5830 
   -- The SFU rule: older SFU hardware resource requests have priority over
5831 
   --    younger ones.
5832 
   --
5833 
   -- The SFU manager sets the signals:
5834 
   --    - pavr_stall_s1
5835 
   --    - pavr_stall_s2
5836 
   --    - pavr_stall_s3
5837 
   --    - pavr_stall_s4
5838 
   --    - pavr_stall_s5
5839 
   --    - pavr_stall_s6
5840 
   --    - pavr_flush_s1
5841 
   --    - pavr_flush_s2
5842 
   --    - pavr_flush_s3
5843 
   --    - pavr_flush_s4
5844 
   --    - pavr_flush_s5
5845 
   --    - pavr_flush_s6
5846 
   --    - pavr_s6_branch_pm_rq
5847 
   --    - pavr_s6_skip_pm_rq
5848 
   --    - pavr_s61_skip_pm_rq
5849 
   --    - pavr_stall_bpu
5850 
   --    - pavr_s61_hwrq_en
5851 
   --    - pavr_s6_hwrq_en
5852 
   --    - pavr_s5_hwrq_en
5853 
   --    - pavr_s4_hwrq_en
5854 
   --    - pavr_s3_hwrq_en
5855 
   --    - pavr_s2_hwrq_en
5856 
   --    - pavr_s1_hwrq_en
5857 
   --
5858 
   sfu_manager:
5859 
   process(pavr_s3_stall_rq, pavr_s4_stall_rq, pavr_s5_stall_rq, pavr_s6_stall_rq,
5860 
           pavr_s3_flush_s2_rq, pavr_s4_flush_s2_rq,
5861 
           pavr_s4_ret_flush_s2_rq, pavr_s5_ret_flush_s2_rq, pavr_s51_ret_flush_s2_rq, pavr_s52_ret_flush_s2_rq,
5862 
           pavr_s53_ret_flush_s2_rq, pavr_s54_ret_flush_s2_rq, pavr_s55_ret_flush_s2_rq,
5863 
           pavr_s6_skip_rq, pavr_s61_skip_rq,
5864 
           pavr_s6_branch_rq,
5865 
           pavr_s4_nop_rq,
5866 
 
5867 
           pavr_s6_hwrq_en,
5868 
           pavr_s5_hwrq_en,
5869 
           pavr_s4_hwrq_en,
5870 
           pavr_s3_hwrq_en,
5871 
 
5872 
           pavr_nop_ack
5873 
          )
5874 
   begin
5875 
      -- By default:
5876 
      --    - don't stall any pipe stage.
5877 
      --    - grant to all pipe stages access to hardware resources.
5878 
      pavr_stall_s1        <= '0';
5879 
      pavr_stall_s2        <= '0';
5880 
      pavr_stall_s3        <= '0';
5881 
      pavr_stall_s4        <= '0';
5882 
      pavr_stall_s5        <= '0';
5883 
      pavr_stall_s6        <= '0';
5884 
      pavr_flush_s1        <= '0';
5885 
      pavr_flush_s2        <= '0';
5886 
      pavr_flush_s3        <= '0';
5887 
      pavr_flush_s4        <= '0';
5888 
      pavr_flush_s5        <= '0';
5889 
      pavr_flush_s6        <= '0';
5890 
      pavr_s6_branch_pm_rq <= '0';
5891 
      pavr_s6_skip_pm_rq   <= '0';
5892 
      pavr_s61_skip_pm_rq  <= '0';
5893 
      pavr_stall_bpu       <= '0';
5894 
      pavr_s61_hwrq_en     <= '1';
5895 
      pavr_s6_hwrq_en      <= '1';
5896 
      pavr_s5_hwrq_en      <= '1';
5897 
      pavr_s4_hwrq_en      <= '1';
5898 
      pavr_s3_hwrq_en      <= '1';
5899 
      pavr_s2_hwrq_en      <= '1';
5900 
      pavr_s1_hwrq_en      <= '1';
5901 
 
5902 
      -- Prioritize hardware resource requests.
5903 
      -- Only one such request can be received by a given resource at a time. If
5904 
      --    multiple accesses are requested from a resource, its access manager
5905 
      --    will assert an error; that would indicate a design bug.
5906 
      -- The pipeline is built so that each resource is normally accessed during a
5907 
      --    fixed pipeline stage:
5908 
      --    - RF is normally read in s2 and written in s6.
5909 
      --    - IOF is normally read/written in s5.
5910 
      --    - DM is normally read/written in s5.
5911 
      --    - DACU is normally read/written in s5.
5912 
      --    - PM is normally read in s1.
5913 
      -- However, exceptions can occur. For example, LPM instructions need to read
5914 
      --    PM in stage s5. Also, loads/stores must be able to read/write RF, IOF
5915 
      --    or DM (depending on addresses involved) in stage s5. Exceptions are
5916 
      --    handled in the hardware resource managers of those resources.
5917 
      -- These are the stall/flush/skip/branch requests that matter when deciding
5918 
      --    whether or not a pipe stage has the right to access hardware resources
5919 
      --    (in priority order):
5920 
      --    - pavr_s61_skip_rq
5921 
      --    - pavr_s6_stall_rq
5922 
      --    - pavr_s6_skip_rq
5923 
      --    - pavr_s6_branch_rq
5924 
      --    - pavr_s5_stall_rq
5925 
      --    - pavr_s4_stall_rq
5926 
      --    - pavr_s4_nop_rq & not pavr_nop_ack
5927 
      --    - pavr_s3_stall_rq
5928 
      --    - pavr_s3_flush_s2_rq
5929 
      --    - pavr_s4_flush_s2_rq
5930 
      --    - pavr_s4_ret_flush_s2_rq
5931 
      --    - pavr_s5_ret_flush_s2_rq
5932 
      --    - pavr_s51_ret_flush_s2_rq
5933 
      --    - pavr_s52_ret_flush_s2_rq
5934 
      --    - pavr_s53_ret_flush_s2_rq
5935 
      --    - pavr_s54_ret_flush_s2_rq
5936 
      --    - pavr_s55_ret_flush_s2_rq
5937 
      -- Stage s61 is always permitted to access hardware resource requests, as
5938 
      --    it is as old that a stage that can place hardware resource requests
5939 
      --    can be.
5940 
      -- Stages s6, s5, s4, s3, s2, s1 are conditionally permitted to do that.
5941 
      if pavr_s61_skip_rq='1' then
5942 
         pavr_s6_hwrq_en <= '0';
5943 
      end if;
5944 
      if  pavr_s61_skip_rq  ='1' or
5945 
          pavr_s6_stall_rq  ='1' or
5946 
          pavr_s6_skip_rq   ='1' or
5947 
          pavr_s6_branch_rq ='1' then
5948 
         pavr_s5_hwrq_en <= '0';
5949 
      end if;
5950 
      if  pavr_s61_skip_rq  ='1' or
5951 
          pavr_s6_stall_rq  ='1' or
5952 
          pavr_s6_skip_rq   ='1' or
5953 
          pavr_s6_branch_rq ='1' or
5954 
          pavr_s5_stall_rq  ='1' or
5955 
          -- *** Check nop requests too here, as nops are inserted *after* the
5956 
          --   instruction wavefront.
5957 
          (pavr_s4_nop_rq='1' and pavr_nop_ack='0') then
5958 
         pavr_s4_hwrq_en <= '0';
5959 
      end if;
5960 
      if  pavr_s61_skip_rq  ='1' or
5961 
          pavr_s6_stall_rq  ='1' or
5962 
          pavr_s6_skip_rq   ='1' or
5963 
          pavr_s6_branch_rq ='1' or
5964 
          pavr_s5_stall_rq  ='1' or
5965 
          pavr_s4_stall_rq  ='1' or
5966 
          (pavr_s4_nop_rq='1' and pavr_nop_ack='0') then
5967 
         pavr_s3_hwrq_en <= '0';
5968 
      end if;
5969 
      if  pavr_s61_skip_rq         ='1' or
5970 
          pavr_s6_stall_rq         ='1' or
5971 
          pavr_s6_skip_rq          ='1' or
5972 
          pavr_s6_branch_rq        ='1' or
5973 
          pavr_s5_stall_rq         ='1' or
5974 
          pavr_s4_stall_rq         ='1' or
5975 
          pavr_s3_stall_rq         ='1' or
5976 
          (pavr_s4_nop_rq='1' and pavr_nop_ack='0')
5977 
          --or
5978 
          --pavr_s3_flush_s2_rq      ='1' or
5979 
          --pavr_s4_flush_s2_rq      ='1' or
5980 
          --pavr_s4_ret_flush_s2_rq  ='1' or
5981 
          --pavr_s5_ret_flush_s2_rq  ='1' or
5982 
          --pavr_s51_ret_flush_s2_rq ='1' or
5983 
          --pavr_s52_ret_flush_s2_rq ='1' or
5984 
          --pavr_s53_ret_flush_s2_rq ='1' or
5985 
          --pavr_s54_ret_flush_s2_rq ='1' or
5986 
          --pavr_s55_ret_flush_s2_rq ='1'
5987 
          then
5988 
         pavr_s2_hwrq_en <= '0';
5989 
      end if;
5990 
      if  pavr_s61_skip_rq ='1' or
5991 
          pavr_s6_stall_rq ='1' or
5992 
          pavr_s6_skip_rq  ='1' or
5993 
          pavr_s6_branch_rq='1' or
5994 
          pavr_s5_stall_rq ='1' or
5995 
          pavr_s4_stall_rq  ='1' or
5996 
          pavr_s3_stall_rq  ='1' or
5997 
          (pavr_s4_nop_rq='1' and pavr_nop_ack='0')
5998 
          then
5999 
         pavr_s1_hwrq_en <= '0';
6000 
      end if;
6001 
 
6002 
      -- Process stall requests according to the SFU rule above.
6003 
      -- Consequences of the SFU rule above:
6004 
      --    - a stall request stalls in turn all younger pipe stages. By doing
6005 
      --       that, the oldest instruction in the pipeline that needs a stall
6006 
      --       wins, and gets its stall clock. All younger instructions are
6007 
      --       postponed, their stall included. They will get their stall later,
6008 
      --       after they resume execution.
6009 
      --    - only a pipe stage that has resources access can win a stall (in
6010 
      --       fact, winning a stall can be considered as winning access to the
6011 
      --       Stall and Flush Unit hardware resource).
6012 
      if pavr_s3_stall_rq='1' and pavr_s3_hwrq_en='1' then
6013 
         pavr_stall_s1  <= '1';
6014 
         pavr_stall_s2  <= '1';
6015 
         pavr_flush_s2  <= '1';
6016 
      end if;
6017 
      if pavr_s4_stall_rq='1' and pavr_s4_hwrq_en='1' then
6018 
         pavr_stall_s1  <= '1';
6019 
         pavr_stall_s2  <= '1';
6020 
         pavr_stall_s3  <= '1';
6021 
         pavr_flush_s3  <= '1';
6022 
      end if;
6023 
      if pavr_s5_stall_rq='1' and pavr_s5_hwrq_en='1' then
6024 
         pavr_stall_s1  <= '1';
6025 
         pavr_stall_s2  <= '1';
6026 
         pavr_stall_s3  <= '1';
6027 
         pavr_stall_s4  <= '1';
6028 
         pavr_flush_s4  <= '1';
6029 
      end if;
6030 
      if pavr_s6_stall_rq='1' and pavr_s6_hwrq_en='1' then
6031 
         pavr_stall_s1  <= '1';
6032 
         pavr_stall_s2  <= '1';
6033 
         pavr_stall_s3  <= '1';
6034 
         pavr_stall_s4  <= '1';
6035 
         pavr_stall_s5  <= '1';
6036 
         pavr_flush_s5  <= '1';
6037 
         pavr_stall_bpu <= '1';
6038 
      end if;
6039 
 
6040 
      -- Process flush requests according to the SFU rule above.
6041 
      -- Examples of the SFU rule above:
6042 
      --    - flush s2 requested in s3, s4 and s5 won't be acknowledged if older
6043 
      --       instructions require a stall, and, consequently, disable resources
6044 
      --       access in s3, s4 respectively s5.
6045 
      --    - s2 can't be flushed when nop is requested in s4.
6046 
      if ((pavr_s3_flush_s2_rq     and pavr_s3_hwrq_en) or
6047 
          (pavr_s4_flush_s2_rq     and pavr_s4_hwrq_en) or
6048 
          (pavr_s4_ret_flush_s2_rq and pavr_s4_hwrq_en) or
6049 
          (pavr_s5_ret_flush_s2_rq and pavr_s5_hwrq_en) or
6050 
           pavr_s51_ret_flush_s2_rq                     or
6051 
           pavr_s52_ret_flush_s2_rq                     or
6052 
           pavr_s53_ret_flush_s2_rq                     or
6053 
           pavr_s54_ret_flush_s2_rq                     or
6054 
           pavr_s55_ret_flush_s2_rq)='1'
6055 
        and
6056 
         ((pavr_s4_nop_rq='0' and pavr_nop_ack='0') or (pavr_s4_nop_rq='1' and pavr_nop_ack='1')) then
6057 
         pavr_flush_s2 <= '1';
6058 
      end if;
6059 
 
6060 
      -- Process skip requests according to the SFU rule above.
6061 
      if pavr_s61_skip_rq='1' then
6062 
         pavr_stall_s1  <= '1';
6063 
         pavr_stall_s2  <= '1';
6064 
         pavr_stall_s3  <= '1';
6065 
         pavr_stall_s4  <= '1';
6066 
         pavr_stall_s5  <= '1';
6067 
         pavr_stall_s6  <= '1';
6068 
         pavr_flush_s2  <= '1';
6069 
         pavr_flush_s3  <= '1';
6070 
         pavr_flush_s4  <= '1';
6071 
         pavr_flush_s5  <= '1';
6072 
         pavr_flush_s6  <= '1';
6073 
         pavr_s61_skip_pm_rq <= '1';
6074 
         pavr_stall_bpu <= '1';
6075 
      end if;
6076 
      if pavr_s6_skip_rq='1' and pavr_s6_hwrq_en='1' then
6077 
         pavr_stall_s1  <= '1';
6078 
         pavr_stall_s2  <= '1';
6079 
         pavr_stall_s3  <= '1';
6080 
         pavr_stall_s4  <= '1';
6081 
         pavr_stall_s5  <= '1';
6082 
         pavr_flush_s2  <= '1';
6083 
         pavr_flush_s3  <= '1';
6084 
         pavr_flush_s4  <= '1';
6085 
         pavr_flush_s5  <= '1';
6086 
         pavr_s6_skip_pm_rq <= '1';
6087 
         pavr_stall_bpu <= '1';
6088 
      end if;
6089 
 
6090 
      -- Process branch requests according to the SFU rule above.
6091 
      if pavr_s6_branch_rq='1' and pavr_s6_hwrq_en='1' then
6092 
         pavr_stall_s1        <= '1';
6093 
         pavr_stall_s2        <= '1';
6094 
         pavr_stall_s3        <= '1';
6095 
         pavr_stall_s4        <= '1';
6096 
         pavr_stall_s5        <= '1';
6097 
         pavr_flush_s2        <= '1';
6098 
         pavr_flush_s3        <= '1';
6099 
         pavr_flush_s4        <= '1';
6100 
         pavr_flush_s5        <= '1';
6101 
         pavr_s6_branch_pm_rq <= '1';
6102 
         pavr_stall_bpu       <= '1';
6103 
      end if;
6104 
 
6105 
      -- Process nop requests according to the SFU rule above.
6106 
      -- *** Condition is hardware resource enabled in s5, not s4, because nop
6107 
      --    request influences the very same pipe stage that placed the
6108 
      --    request (s4).
6109 
      if pavr_s4_nop_rq='1' and pavr_nop_ack='0' and pavr_s5_hwrq_en='1' then
6110 
         pavr_stall_s1  <= '1';
6111 
         pavr_stall_s2  <= '1';
6112 
         pavr_stall_s3  <= '1';
6113 
         pavr_stall_s4  <= '1';
6114 
         pavr_flush_s4  <= '1';
6115 
      end if;
6116 
   end process sfu_manager;
6117 
 
6118 
 
6119 
 
6120 
   -- Shadow manager (Synchronous)
6121 
   -- To understand why the shadow protocol is needed, let's consider the
6122 
   --    following example: a load instruction reads the Data Memory during pipe
6123 
   --    stage s5. Suppose that next clock stalls s6, during which Data Memory
6124 
   --    output was supposed to be written into the Register File. After another
6125 
   --    clock, the stall is removed, and s6 requests to write the Register File,
6126 
   --    but the Data Memory output has changed during the stall. Corrupted data
6127 
   --    will be written into the Register File. With the shadow protocol, the
6128 
   --    Data Memory output is saved during the stall, and the Register File is
6129 
   --    written with the saved data.
6130 
   -- Shadow protocol:
6131 
   --    If a pipe stage is not permitted to place hardware resource requests,
6132 
   --       then mark every memory-like entity in that stage as having its output
6133 
   --       `shadowed'. That is, its output will be read (by whatever process
6134 
   --       needs it) from the associated shadow register, rather than directly
6135 
   --       from memory-like entity's output.
6136 
   --    Basically, the condition that shadows a memory-like entity's output is
6137 
   --       `hardware resource enabled during that stage'=0. However, there are
6138 
   --       exceptions. For example, LPM family instructions steal Program Memory
6139 
   --       access by stalling the instruction that would normally be fetched that
6140 
   --       time. By stalling, hardware resource requests become disabled in that
6141 
   --       pipe stage. Still, LPM family instructions must be able to request
6142 
   --       Program Memory access. Here, the PM must not be shadowed even though
6143 
   --       during its pipe stage s2 (during which PM is normally accessed) all
6144 
   --       hardware requests are disabled by default.
6145 
   --    In order to enable shadowing during multiple, successive stalls, shadow
6146 
   --       memory-like entities outputs only if they aren't already shadowed.
6147 
   -- Set the signals:
6148 
   --    - !!!
6149 
   shadow_manager:
6150 
   process(pavr_res, pavr_syncres, pavr_clk,
6151 
 
6152 
           pavr_s3_stall_rq,
6153 
 
6154 
           pavr_s5_hwrq_en,
6155 
           pavr_s2_hwrq_en,
6156 
           pavr_s1_hwrq_en,
6157 
 
6158 
           pavr_grant_control_flow_access,
6159 
 
6160 
           pavr_rf_do_shadow_active,
6161 
           pavr_rf_rd1_do_shadow,
6162 
           pavr_rf_rd2_do_shadow,
6163 
           pavr_iof_do_shadow_active,
6164 
           pavr_iof_do_shadow,
6165 
           pavr_dm_do_shadow_active,
6166 
           pavr_dm_do_shadow,
6167 
           pavr_dacu_do_shadow_active,
6168 
           pavr_dacu_do_shadow,
6169 
           pavr_pm_do_shadow_active,
6170 
           pavr_pm_do_shadow,
6171 
 
6172 
           pavr_pm_do,
6173 
           pavr_s2_pmdo_valid,
6174 
           pavr_rf_rd1_do,
6175 
           pavr_rf_rd2_do,
6176 
           pavr_iof_do,
6177 
           pavr_dm_do,
6178 
           pavr_dacu_do
6179 
          )
6180 
   begin
6181 
         if pavr_res='1' then
6182 
         -- Asynchronous reset
6183 
         -- RF-related shadow registers
6184 
         pavr_rf_rd1_do_shadow      <= int_to_std_logic_vector(0, pavr_rf_rd1_do_shadow'length);
6185 
         pavr_rf_rd2_do_shadow      <= int_to_std_logic_vector(0, pavr_rf_rd2_do_shadow'length);
6186 
         pavr_rf_do_shadow_active   <= '0';
6187 
         -- IOF-related shadow registers
6188 
         pavr_iof_do_shadow         <= int_to_std_logic_vector(0, pavr_iof_do_shadow'length);
6189 
         pavr_iof_do_shadow_active  <= '0';
6190 
         -- DM-related shadow registers
6191 
         pavr_dm_do_shadow          <= int_to_std_logic_vector(0, pavr_dm_do_shadow'length);
6192 
         pavr_dm_do_shadow_active   <= '0';
6193 
         -- DACU-related shadow registers
6194 
         pavr_dacu_do_shadow        <= int_to_std_logic_vector(0, pavr_dacu_do_shadow'length);
6195 
         pavr_dacu_do_shadow_active <= '0';
6196 
         -- PM-related shadow registers
6197 
         pavr_pm_do_shadow          <= int_to_std_logic_vector(0, pavr_pm_do_shadow'length);
6198 
         pavr_s2_pmdo_valid_shadow  <= '0';
6199 
         pavr_pm_do_shadow_active   <= '0';
6200 
 
6201 
      elsif pavr_clk'event and pavr_clk='1' then
6202 
         -- RF-related shadow registers
6203 
         -- RF is normally read in pipe stage s2.
6204 
         -- ** Don't shadow RF if s3 stall request (hole through shadow protocol).
6205 
         --    That's because s3 stall requests are intended only to delay youger
6206 
         --    instructions with one clock. During this stalls, the instruction
6207 
         --    that requests s3 stall might need to read RF (for example, the
6208 
         --    instruction CPSE). If RF is shadowed, that instruction will
6209 
         --    incorrectly read from shadow register.
6210 
         -- Note
6211 
         --    Fortunately, there are only a few such exceptions (holes through
6212 
         --    the shadow protocol). Overall, the shadow protocol is still a good
6213 
         --    idea, as it permits natural & automatic handling of a bunch of
6214 
         --    registers placed in delicated areas.
6215 
         if pavr_s2_hwrq_en='0' and pavr_s3_stall_rq='0' then     -- ... if `hardware resources are disabled' and 's3 doesn't request stall'
6216 
            if pavr_rf_do_shadow_active='0' then                  --        and `shadow isn't already active'
6217 
               pavr_rf_rd1_do_shadow      <= pavr_rf_rd1_do;      --     then `shadow Register File read ports 1 and 2'
6218 
               pavr_rf_rd2_do_shadow      <= pavr_rf_rd2_do;
6219 
               pavr_rf_do_shadow_active   <= '1';
6220 
            end if;
6221 
         else
6222 
            pavr_rf_do_shadow_active   <= '0';                    --     else `unshadow Register File read ports 1 and 2'
6223 
         end if;
6224 
 
6225 
         -- IOF-related shadow registers
6226 
         -- IOF is normally read in pipe stage s5.
6227 
         if pavr_s5_hwrq_en='0' then
6228 
            if pavr_iof_do_shadow_active='0' then
6229 
               pavr_iof_do_shadow         <= pavr_iof_do;
6230 
               pavr_iof_do_shadow_active  <= '1';
6231 
            end if;
6232 
         else
6233 
            pavr_iof_do_shadow_active  <= '0';
6234 
         end if;
6235 
 
6236 
         -- DM-related shadow registers
6237 
         -- DM is normally read in pipe stage s5.
6238 
         if pavr_s5_hwrq_en='0' then
6239 
            if pavr_dm_do_shadow_active='0' then
6240 
               pavr_dm_do_shadow          <= pavr_dm_do;
6241 
               pavr_dm_do_shadow_active   <= '1';
6242 
            end if;
6243 
         else
6244 
            pavr_dm_do_shadow_active   <= '0';
6245 
         end if;
6246 
 
6247 
         -- DACU-related shadow registers
6248 
         -- DACU is normally read in pipe stage s5.
6249 
         if pavr_s5_hwrq_en='0' then
6250 
            if pavr_dacu_do_shadow_active='0' then
6251 
               pavr_dacu_do_shadow        <= pavr_dacu_do;
6252 
               pavr_dacu_do_shadow_active <= '1';
6253 
            end if;
6254 
         else
6255 
            pavr_dacu_do_shadow_active <= '0';
6256 
         end if;
6257 
 
6258 
         -- Setting PM-related shadow registers
6259 
         -- PM is normally read in pipe stage s1.
6260 
         -- *** If a control instruction instruction wants flow control access,
6261 
         --    don't shadow PM (hole through shadow protocol).
6262 
         if pavr_s1_hwrq_en='0' and pavr_grant_control_flow_access='0' then
6263 
            if  pavr_pm_do_shadow_active='0' then
6264 
               -- Shadow PM.
6265 
               pavr_pm_do_shadow          <= pavr_pm_do;
6266 
               pavr_s2_pmdo_valid_shadow  <= pavr_s2_pmdo_valid;
6267 
               pavr_pm_do_shadow_active   <= '1';
6268 
            end if;
6269 
         else
6270 
            -- Unshadow PM.
6271 
            pavr_pm_do_shadow_active   <= '0';
6272 
         end if;
6273 
 
6274 
         if pavr_syncres='1' then
6275 
            -- Synchronous reset
6276 
            -- RF-related shadow registers
6277 
            pavr_rf_rd1_do_shadow      <= int_to_std_logic_vector(0, pavr_rf_rd1_do_shadow'length);
6278 
            pavr_rf_rd2_do_shadow      <= int_to_std_logic_vector(0, pavr_rf_rd2_do_shadow'length);
6279 
            pavr_rf_do_shadow_active   <= '0';
6280 
            -- IOF-related shadow registers
6281 
            pavr_iof_do_shadow         <= int_to_std_logic_vector(0, pavr_iof_do_shadow'length);
6282 
            pavr_iof_do_shadow_active  <= '0';
6283 
            -- DM-related shadow registers
6284 
            pavr_dm_do_shadow          <= int_to_std_logic_vector(0, pavr_dm_do_shadow'length);
6285 
            pavr_dm_do_shadow_active   <= '0';
6286 
            -- DACU-related shadow registers
6287 
            pavr_dacu_do_shadow        <= int_to_std_logic_vector(0, pavr_dacu_do_shadow'length);
6288 
            pavr_dacu_do_shadow_active <= '0';
6289 
            -- PM-related shadow registers
6290 
            pavr_pm_do_shadow          <= int_to_std_logic_vector(0, pavr_pm_do_shadow'length);
6291 
            pavr_s2_pmdo_valid_shadow  <= '0';
6292 
            pavr_pm_do_shadow_active   <= '0';
6293 
         end if;
6294 
      end if;
6295 
   end process shadow_manager;
6296 
 
6297 
 
6298 
 
6299 
   -- Computing branch and skip conditions
6300 
   -- Set signals:
6301 
   --    - next_pavr_s6_branch_rq
6302 
   --    - next_pavr_s6_skip_rq
6303 
   --    - next_pavr_s61_skip_rq
6304 
   br_skip_cond:
6305 
   process(pavr_s5_branch_bitsreg_sel, pavr_s5_branch_cond_sel, pavr_s5_branch_en, pavr_iof_sreg,
6306 
           pavr_s5_skip_bitrf_sel,     pavr_s5_skip_cond_sel,   pavr_s5_skip_en,   pavr_s5_op1bpu, pavr_s5_alu_flagsout,
6307 
           pavr_s6_skip_bitiof_sel,    pavr_s6_skip_cond_sel,   pavr_s6_skip_en,   pavr_iof_do,
6308 
           pavr_iof_do_shadow, pavr_iof_do_shadow_active
6309 
          )
6310 
      variable t_pavr_s5_branch_bitsreg, t_pavr_s5_branch_cond: std_logic;
6311 
      variable t_pavr_s5_skip_bitrf,     t_pavr_s5_skip_cond:   std_logic;
6312 
      variable t_pavr_s6_skip_bitiof,    t_pavr_s6_skip_cond:   std_logic;
6313 
      variable t_pavr_iof_do: std_logic_vector(7 downto 0);
6314 
   begin
6315 
      -- Compute branch condition in stage s5.
6316 
      case std_logic_vector_to_nat(pavr_s5_branch_bitsreg_sel) is
6317 
         when 0 =>
6318 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(0);
6319 
         when 1 =>
6320 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(1);
6321 
         when 2 =>
6322 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(2);
6323 
         when 3 =>
6324 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(3);
6325 
         when 4 =>
6326 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(4);
6327 
         when 5 =>
6328 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(5);
6329 
         when 6 =>
6330 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(6);
6331 
         when others =>
6332 
            t_pavr_s5_branch_bitsreg := pavr_iof_sreg(7);
6333 
      end case;
6334 
      case pavr_s5_branch_cond_sel is
6335 
         when pavr_s5_branch_cond_sel_bitsreg =>
6336 
            t_pavr_s5_branch_cond := t_pavr_s5_branch_bitsreg;
6337 
         -- When pavr_s5_branch_cond_sel_notbitsreg
6338 
         when others =>
6339 
            t_pavr_s5_branch_cond := not t_pavr_s5_branch_bitsreg;
6340 
      end case;
6341 
      next_pavr_s6_branch_rq <= t_pavr_s5_branch_cond and pavr_s5_branch_en;
6342 
 
6343 
      -- Compute skip condition in stage s5.
6344 
      case std_logic_vector_to_nat(pavr_s5_skip_bitrf_sel) is
6345 
         when 0 =>
6346 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(0);
6347 
         when 1 =>
6348 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(1);
6349 
         when 2 =>
6350 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(2);
6351 
         when 3 =>
6352 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(3);
6353 
         when 4 =>
6354 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(4);
6355 
         when 5 =>
6356 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(5);
6357 
         when 6 =>
6358 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(6);
6359 
         when others =>
6360 
            t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(7);
6361 
      end case;
6362 
      case pavr_s5_skip_cond_sel is
6363 
         when pavr_s5_skip_cond_sel_zflag =>
6364 
            t_pavr_s5_skip_cond := pavr_s5_alu_flagsout(1);
6365 
         when pavr_s5_skip_cond_sel_bitrf =>
6366 
            t_pavr_s5_skip_cond := t_pavr_s5_skip_bitrf;
6367 
         -- When pavr_s5_skip_cond_sel_notbitrf
6368 
         when others =>
6369 
            t_pavr_s5_skip_cond := not t_pavr_s5_skip_bitrf;
6370 
      end case;
6371 
      next_pavr_s6_skip_rq <= t_pavr_s5_skip_cond and pavr_s5_skip_en;
6372 
 
6373 
      -- Compute skip condition in stage s6.
6374 
      if pavr_iof_do_shadow_active='0' then
6375 
         t_pavr_iof_do := pavr_iof_do;
6376 
      else
6377 
         t_pavr_iof_do := pavr_iof_do_shadow;
6378 
      end if;
6379 
      case std_logic_vector_to_nat(pavr_s6_skip_bitiof_sel) is
6380 
         when 0 =>
6381 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(0);
6382 
         when 1 =>
6383 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(1);
6384 
         when 2 =>
6385 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(2);
6386 
         when 3 =>
6387 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(3);
6388 
         when 4 =>
6389 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(4);
6390 
         when 5 =>
6391 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(5);
6392 
         when 6 =>
6393 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(6);
6394 
         when others =>
6395 
            t_pavr_s6_skip_bitiof := t_pavr_iof_do(7);
6396 
      end case;
6397 
      case pavr_s6_skip_cond_sel is
6398 
         when pavr_s6_skip_cond_sel_bitiof =>
6399 
            t_pavr_s6_skip_cond := t_pavr_s6_skip_bitiof;
6400 
         -- When pavr_s6_skip_cond_sel_notbitiof
6401 
         when others =>
6402 
            t_pavr_s6_skip_cond := not t_pavr_s6_skip_bitiof;
6403 
      end case;
6404 
      next_pavr_s61_skip_rq <= t_pavr_s6_skip_cond and pavr_s6_skip_en;
6405 
 
6406 
   end process br_skip_cond;
6407 
 
6408 
 
6409 
 
6410 
   -- Zero-level assignments --------------------------------------------------
6411 
   -- Read Bypass Unit.
6412 
   pavr_s5_op1bpu <= read_through_bpu(pavr_s5_op1, pavr_s5_op1_addr,
6413 
                                      pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6414 
                                      pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6415 
                                      pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6416 
                                      pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6417 
                                      pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6418 
                                      pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6419 
                                      pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6420 
                                      pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6421 
                                      pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6422 
                                      pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6423 
                                      pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6424 
                                      pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6425 
   pavr_s5_op2bpu <= read_through_bpu(pavr_s5_op2, pavr_s5_op2_addr,
6426 
                                      pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6427 
                                      pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6428 
                                      pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6429 
                                      pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6430 
                                      pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6431 
                                      pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6432 
                                      pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6433 
                                      pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6434 
                                      pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6435 
                                      pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6436 
                                      pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6437 
                                      pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6438 
   pavr_xbpu(7 downto 0)  <= read_through_bpu(pavr_rf_x(7 downto 0),  int_to_std_logic_vector(26, 5),
6439 
                                              pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6440 
                                              pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6441 
                                              pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6442 
                                              pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6443 
                                              pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6444 
                                              pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6445 
                                              pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6446 
                                              pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6447 
                                              pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6448 
                                              pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6449 
                                              pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6450 
                                              pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6451 
   pavr_xbpu(15 downto 8) <= read_through_bpu(pavr_rf_x(15 downto 8), int_to_std_logic_vector(27, 5),
6452 
                                              pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6453 
                                              pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6454 
                                              pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6455 
                                              pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6456 
                                              pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6457 
                                              pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6458 
                                              pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6459 
                                              pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6460 
                                              pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6461 
                                              pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6462 
                                              pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6463 
                                              pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6464 
   pavr_ybpu(7 downto 0)  <= read_through_bpu(pavr_rf_y(7 downto 0),  int_to_std_logic_vector(28, 5),
6465 
                                              pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6466 
                                              pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6467 
                                              pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6468 
                                              pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6469 
                                              pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6470 
                                              pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6471 
                                              pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6472 
                                              pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6473 
                                              pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6474 
                                              pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6475 
                                              pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6476 
                                              pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6477 
   pavr_ybpu(15 downto 8) <= read_through_bpu(pavr_rf_y(15 downto 8), int_to_std_logic_vector(29, 5),
6478 
                                              pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6479 
                                              pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6480 
                                              pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6481 
                                              pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6482 
                                              pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6483 
                                              pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6484 
                                              pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6485 
                                              pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6486 
                                              pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6487 
                                              pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6488 
                                              pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6489 
                                              pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6490 
   pavr_zbpu(7 downto 0)  <= read_through_bpu(pavr_rf_z(7 downto 0),  int_to_std_logic_vector(30, 5),
6491 
                                              pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6492 
                                              pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6493 
                                              pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6494 
                                              pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6495 
                                              pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6496 
                                              pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6497 
                                              pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6498 
                                              pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6499 
                                              pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6500 
                                              pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6501 
                                              pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6502 
                                              pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6503 
   pavr_zbpu(15 downto 8) <= read_through_bpu(pavr_rf_z(15 downto 8), int_to_std_logic_vector(31, 5),
6504 
                                              pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
6505 
                                              pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
6506 
                                              pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
6507 
                                              pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
6508 
                                              pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
6509 
                                              pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
6510 
                                              pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
6511 
                                              pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
6512 
                                              pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
6513 
                                              pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
6514 
                                              pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
6515 
                                              pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
6516 
   pavr_pm_addr <= pavr_pm_addr_int;
6517 
   pavr_pm_wr <= '0';
6518 
   pavr_s5_alu_flagsin <= pavr_iof_sreg(5 downto 0);
6519 
   pavr_disable_int <= pavr_s4_disable_int  or
6520 
                       pavr_s5_disable_int  or
6521 
                       pavr_s51_disable_int or
6522 
                       pavr_s52_disable_int;
6523 
 
6524 
   -- <DEBUG>
6525 
   -- Instruction counting.
6526 
   -- Note that the instruction count is not exact:
6527 
   --    - explicit nops are not counted.
6528 
   --    - skips/branches followed by a 32 bit instruction are counted twice.
6529 
   instr_cnt:
6530 
   process(pavr_stall_s2,
6531 
           pavr_s5_branch_en, pavr_s5_skip_en, pavr_s6_skip_en,
6532 
           pavr_s5_hwrq_en, pavr_s6_hwrq_en, pavr_s6_branch_rq, pavr_s6_skip_rq, pavr_s61_skip_rq,
6533 
           pavr_s3_instr, pavr_s2_pmdo_valid, pavr_s4_instr32bits )
6534 
   begin
6535 
      pavr_inc_instr_cnt <= "00";
6536 
      if (pavr_s2_pmdo_valid='1' and
6537 
          pavr_stall_s2='0' and
6538 
          pavr_s4_instr32bits='0' and
6539 
          std_logic_vector_to_nat(pavr_s3_instr)/=0)
6540 
         then
6541 
         -- Add 1 to instruction counter.
6542 
         pavr_inc_instr_cnt <= "01";
6543 
      end if;
6544 
      if  (pavr_s5_hwrq_en='1' and pavr_s5_branch_en='1') or
6545 
          (pavr_s5_hwrq_en='1' and pavr_s5_skip_en='1')   or
6546 
          (pavr_s6_hwrq_en='1' and pavr_s6_skip_en='1')
6547 
         then
6548 
         -- Add 2 to instruction counter.
6549 
         pavr_inc_instr_cnt <= "10";
6550 
      end if;
6551 
      if  (pavr_s6_hwrq_en='1' and pavr_s6_branch_rq='1') or
6552 
          (pavr_s6_hwrq_en='1' and pavr_s6_skip_rq  ='1') or
6553 
          (                        pavr_s61_skip_rq ='1')
6554 
          then
6555 
         -- Substract 1 from from instruction counter.
6556 
         pavr_inc_instr_cnt <= "11";
6557 
      end if;
6558 
   end process instr_cnt;
6559 
   -- </DEBUG>
6560 
 
6561 
end;
6562 
-- </File body>

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