URL https://opencores.org/ocsvn/pavr/pavr/trunk

Subversion Repositories pavr

[/] [pavr/] [trunk/] [test/] [gentest/] [gentest.asm] - Blame information for rev 6

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; Project
;    pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
;    AVR core, but about 3x faster in terms of both clock frequency and MIPS.
;    The increase in speed comes from a relatively deep pipeline. The original
;    AVR core has only two pipeline stages (fetch and execute), while pAVR has
;    6 pipeline stages:
;       1. PM    (read Program Memory)
;       2. INSTR (load Instruction)
;       3. RFRD  (decode Instruction and read Register File)
;       4. OPS   (load Operands)
;       5. ALU   (execute ALU opcode or access Unified Memory)
;       6. RFWR  (write Register File)
; Version
;    0.32
; Date
;    2002 August 07
; Author
;    Doru Cuturela, doruu@yahoo.com
; License
;    This program is free software; you can redistribute it and/or modify
;    it under the terms of the GNU General Public License as published by
;    the Free Software Foundation; either version 2 of the License, or
;    (at your option) any later version.
;    This program is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;    You should have received a copy of the GNU General Public License
;    along with this program; if not, write to the Free Software
;    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 
 
; About this file...
;   This tests all instructions, one by one.
 
 
 
.include "m103def.inc"
 
   ; Initialize some registers.
   rjmp start
 
.org 400
start:
   LDI R17, 0x90
   MOV R0,  R17
   MOV R1,  R17
   MOV R2,  R17
   MOV R4,  R17
   MOV R7,  R17
   MOV R12, R17
   MOV R14, R17
   MOV R16, R17
   MOV R18, R17
   MOV R20, R17
   MOV R22, R17
   MOV R23, R17
   MOV R24, R17
   MOV R25, R17
   MOV R26, R17
   MOV R29, R17
   MOV R31, R17
   LDI R28, 0xd5
   MOV R3,  R28
   MOV R5,  R28
   MOV R6,  R28
   MOV R8,  R28
   MOV R9,  R28
   MOV R10, R28
   MOV R11, R28
   MOV R13, R28
   MOV R15, R28
   MOV R19, R28
   MOV R21, R28
   MOV R24, R28
   MOV R27, R28
   MOV R30, R28
 
   ; These replace original nops, for maintaining absolute addresses used for jumping during the test.
   MOV R0, R0
   MOV R0, R0
   MOV R0, R0
   MOV R0, R0
   MOV R0, R0
   MOV R0, R0
 
   ADD  R28, R17        ; r28 = d5+90=65 (modulo 256)    SREG=19
   ADC  R25, R28        ; r25 = 90+65+1=f6               SREG=14
   ADIW R25:R24, 0x35   ; r25:r24 = f6:d5+65=f7:0a       SREG=14
 
   SUB  R23, R24        ; r23 = 90-a=86                  SREG=34
   SUBI R23, 0xf6       ; r23 = 86-f6=90                 SREG=15
   SBC  R26, R23        ; r26 = 90-90-1=ff               SREG=35
   SBIW R27:R26, 0x2d   ; r27:r26 = d5:ff-2d=d5:d2       SREG=34
 
   ; Intermediate result: r26=0xd2
 
   INC r26              ; r26=d2+1=d3     SREG=34
   INC r26              ; r26=d3+1=d4     SREG=34
   INC r26              ; r26=d4+1=d5     SREG=34
   INC r26              ; r26=d5+1=d6     SREG=34
   INC r26              ; r26=d6+1=d7     SREG=34
   DEC r26              ; r25=d7-1=d6     SREG=34
 
   AND   r28, r26       ; r28=65&d6=44    SREG=20
   ANDI  r28, 0x43      ; r28=44&43=40    SREG=20
   OR    r31, r28       ; r31=90|40=d0    SREG=34
   ORI   r31, 0x63      ; r31=d0|63=f3    SREG=34
   EOR   r10, r31       ; r10=d5^f3=26    SREG=20
 
   ; Intermediate result: r10=0x26
 
   COM   r10            ; r10=com(26)=d9              SREG=35
   NEG   r10            ; r10=neg(d9)=27, set C       SREG=01
   SEZ                  ;                             SREG=03
   CP    r10, r11       ; (r10
   MOV   r12, r10       ; r12=27
   DEC   r12            ; r12=26
   SEZ                  ;                             SREG=03
   CPC   r10, r12       ; (r10
   CPI   r17, 0xab      ; (r17
   SWAP  r12            ; r12=swap(r12)=62
 
   LSR r12              ; r12=lsr(r12)=31             SREG=20
   ROR r12              ; r12=ror(r12)=18             SREG=39
   ASR r12              ; r12=asr(r12)=c              SREG=20
 
   ; Intermediate result: r21=0x0c
 
   ; Multiplications return zero for now. Test timing only.
   MUL    r10, r10
   MULS   r17, r17
   MULSU  r17, r17
   FMUL   r17, r17
   FMULS  r17, r17
   FMULSU r17, r17
 
   MOV r0, r12             ; r0=r12=c
   MOV r1, r11             ; r1=r11=d5
   SUB r1, r0              ; r1=r1-r0=c-d5=c9         SREG=34
 
   ; Intermediate result: r1=0xc9
 
   OUT  SREG, r1           ; SREG=r1=c9
   BCLR 7                  ; SREG(7)=0; SREG=49
   BCLR 3                  ; SREG(3)=0; SREG=41
   BSET 1                  ; SREG(1)=1; SREG=43
   BSET 4                  ; SREG(4)=1; SREG=53
 
   ; Configure port A as output.
   LDI R27,  0xFF
   OUT DDRA, R27
   IN  R29, SREG           ; R29=SREG=53
   ; Send R29 to port A.
   OUT PORTA, R29          ; PORTA=R29=53
   CBI PORTA, 0            ; PORTA(0)=0; PORTA=52
   CBI PORTA, 6            ; PORTA(6)=0; PORTA=12
   SBI PORTA, 3            ; PORTA(2)=0; PORTA=1a
   SBI PORTA, 5            ; PORTA(7)=0; PORTA=3a
   IN  R30, PORTA          ; R30=PORTA=3a
   LDI  R31, 0x00          ; R31=0
   ; Test if both IN and LDI correctly update the BPU (IN stalls LDI to steal BPU access).
   SBIW R31:R30, 0x3e      ; R31:R30=R31:R30-3e=00:3a-3e=ff:fc    SREG=55
   BST  R30, 1             ; T=R30(1)=0
   BLD  R30, 6             ; R30(6)=T=0; R30=bc
   MOV  R31, R1            ; R31=c9
   ; Test if both BLD and MOV correctly update the BPU (BLD stalls MOV to steal BPU access).
   ADIW R31:R30, 0x2a      ; R31:R30=R31:R30+2a=c9:bc+2a=c9:e6    SREG=14
   ; Test if both bytes of the result update the BPU.
   ADIW R31:R30, 0x18      ; R31:R30=R31:R30+18=c9:e6+18=c9:fe    SREG=14
   MOV R10, R30
 
   ; Intermediate result: r10=fe
 
   ; Set up the stack
   LDI R25, 0x01
   OUT SPH, R25
   LDI R26, 0x1c
   OUT SPL, R26
 
   MOVW R23:R22, R31:R30      ; R23:R22=R31:R30=c9:fe
   PUSH R22                   ; stack=R22=fe
   POP  R21
   ADD  R21, R12
   ADD  R21, R12
   ADD  R21, R12
   ADD  R21, R12              ; R21=2e
 
   STS 0x0130, R21
   LDS R22, 0x0130            ; R22=2e
   LDI R31, 0x01              ; R31=1
   LDI R30, 0x23              ; R30=23
   INC R22                    ; R22=R22+1=2e+1=2f
   ST  Z, R22                 ; (Z)=(1:23)=R22=2f
   LD  R21, Z                 ; R21=(Z)=(1:23)=2f
 
   LDI R17, 0xf9
   MOV R0, R17
   INC R0
 
   ; Load pointer registers for next tests.
   LDI R27, 0x01              ; X=0140
   LDI R26, 0x40              ;
   LDI R29, 0x01              ; Y=0150
   LDI R28, 0x50              ;
   LDI R31, 0x01              ; Z=0160
   LDI R30, 0x60              ;
 
   ; Load-stores through X pointer
   ST  X+, R0
   ST  X,  R0
   ADIW R27:R26, 0x02
   ST  -X, R0
   LD  R20, X+
   SBIW R27:R26, 0x02
   LD  R21, X
   LD  R22, -X
 
   INC R0
 
   ; Load-stores through Y pointer
   ST  Y+, R0
   ST  Y,  R0
   ADIW R29:R28, 0x02
   ST  -Y, R0
   LD  R20, Y+
   SBIW R29:R28, 0x02
   LD  R21, Y
   LD  R22, -Y
 
   STD Y+0x3b, R0
   LDD R23, Y+0x3b
 
   INC R0
 
   ; Load-stores through Z pointer
   ST  Z+, R0
   ST  Z,  R0
   ADIW R31:R30, 0x02
   ST  -Z, R0
   LD  R20, Z+
   SBIW R31:R30, 0x02
   LD  R21, Z
   LD  R22, -Z
 
   STD Z+0x3c, R0
   LDD R23, Z+0x3c
 
   ; Store into Register File.
   LDI R20, 0xaa
   LDI R21, 0xbb
   LDI R27, 00
   LDI R26, 21
   ST  X+, R20
   ; Check if R21=0xaa.
 
   ; Store into IO File.
   LDI R20, 0xcc
   LDI R31, 0x00
   LDI R30, 0x38
   STD Z+3, R20         ; (3b)=R20=cc (note that PORTA has address 0x3b in the Unified Memory, that is 0x1b in IOF)
   ; Check if PORTA=0xcc
 
   ; Test LPM family instructions.
   LDI R31, 0x03
   LDI R30, 0x74
   LPM
   LPM R17, Z+
   LPM R18, Z+
   LPM R19, Z
 
   LDI R31, 0x03
   LDI R30, 0x45
   LDI R17, 0x00
   OUT RAMPZ, R17
   ELPM
   ELPM R17, Z+
   ELPM R18, Z+
   ELPM R19, Z
 
   ; Jumps ----------------------------
 
   ; RJMP
   RJMP jmp1
   LDI R19, 0xaa
jmp2:
   LDI R19, 0xbb
   LDI R19, 0xcc
   RJMP jmp3
jmp1:
   LDI R19, 0xdd
   LDI R19, 0xee
   RJMP jmp2
jmp3:
   LDI R19, 0xff              ; R19 = dd, ee, bb, cc, ff
 
   ; IJMP
   LDI R19, 0x11
   LDI R31, 0x02
   LDI R30, 0x58
   IJMP
jmp5:                ; 0254
   LDI R19, 0x22
   LDI R31, 0x02
   LDI R30, 0x5c
   IJMP
jmp4:                ; 0258
   LDI R19, 0x33
   LDI R31, 0x02
   LDI R30, 0x54
   IJMP
jmp6:                ; 025c
   LDI R19, 0x44
   LDI R31, 0x02
   LDI R30, 0x61
   IJMP
   LDI R19, 0x55
jmp7:                ; 0261
   LDI R19, 0x66              ; R19 = 11, 33, 22, 44, 66
 
   ; EIJMP
   LDI R19, 0x77
   LDI R17, 0x00
   OUT RAMPZ, R17
   LDI R31, 0x02
   LDI R30, 0x6a
   EIJMP
jmp9:                ; 0268
   LDI R19, 0x88
   RJMP jmp10
jmp8:                ; 026a
   LDI R19, 0x99
   LDI R31, 0x02
   LDI R30, 0x68
   EIJMP
jmp10:               ; 026e
   LDI R19, 0xaa              ; R19 = 77, 99, 88, aa
 
   ; JMP
   LDI R19, 0x10
   JMP jmp11
   LDI R19, 0x11
jmp12:
   LDI R19, 0x12
   ; Stress the JMP a little bit.
   INC R11
   INC R10
   LDI R17, 0x09
   LDI R20, 0xa2
   LDI R29, 0x00
   LDI R28, 20
   ST Y, R17      ; R20=9
   LD R21, Y      ; R21=9
   JMP jmp13
   LDI R19, 0x13
   LDI R19, 0x14
jmp11:
   LDI R19, 0x15
   ; Stress the JMP a little bit.
   INC R11
   INC R10
   MOVW R11:R10, R25:R24
   JMP jmp12
jmp13:
   LDI R19, 0x16              ; R19 = 10, 15, 12, 16
 
   ; Skips ----------------------------
 
   ; CPSE
   LDI R20, 0x10
   LDI R21, 0x10
   LDI R22, 0x11
   LDI R19, 0x21              ; R19 = 21
   CPSE R20, R21
   LDI R19, 0x22
   LDI R19, 0x23              ; R19 = 23
   CPSE R20, R22
   LDI R19, 0x24              ; R19 = 24
   ; Stress CPSE a little bit.
   LDI R31, 0x00
   LDI R30, 19
   CPSE R20, R21
   ST Z+, R0
   ST Z+, R24                 ; R19 = a
   DEC R19                    ; R19 = 9
   CPSE R20, R21
   LD R6, -Z
   LD R7, -Z                  ; R7 = 9
   CPSE R20, R21
   MOVW R19:R18, R5:R4
   LDI R19, 0x25              ; R19 = 25
   CPSE R20, R21
   JMP jmp13
   LDI R19, 0x26              ; R19 = 26
   CPSE R20, R21
   STD Z+0, R23
   STD Z+0, R25               ; R19 = 1
 
   ; SBRC
   LDI R20, 0x41              ; R20 = 41
   SBRC R20, 6
   LDI R19, 0x30              ; R19 = 30
   SBRC R20, 7
   LDI R19, 0x28
   LDI R19, 0x31              ; R19 = 31
   SBRC R20, 7
   LD R18, Z
   SBRC R20, 7
   STD Z+0, R20
   LDI R19, 0x32              ; R19 = 32
   SBRC R20, 7
   JMP jmp13
   LDI R19, 0x33              ; R19 = 33
   SBRC R20, 7
   MOVW R19:R18, R1:R0
   LDI R19, 0x3d              ; R19 = 3d
 
   ; SBRS
   LDI R20, 0x92              ; R20 = 92
   SBRS R20, 6
   LDI R19, 0x40              ; R19 = 40
   SBRS R20, 7
   LDI R19, 0x28
   LDI R19, 0x41              ; R19 = 41
   SBRS R20, 7
   LD R18, Z
   SBRS R20, 7
   STD Z+0, R20
   LDI R19, 0x42              ; R19 = 42
   SBRS R20, 7
   JMP jmp13
   LDI R19, 0x43              ; R19 = 43
   SBRS R20, 7
   MOVW R19:R18, R1:R0
   LDI R19, 0x44              ; R19 = 44
 
   ; SBIC
   LDI R20, 0x41              ; R20 = 41
   OUT PORTA, R20
   SBIC PORTA, 6
   LDI R19, 0x50              ; R19 = 50
   SBIC PORTA, 7
   LDI R19, 0x28
   LDI R19, 0x51              ; R19 = 51
   SBIC PORTA, 7
   LD R18, Z
   SBIC PORTA, 7
   STD Z+0, R20
   LDI R19, 0x52              ; R19 = 52
   SBIC PORTA, 7
   JMP jmp13
   LDI R19, 0x53              ; R19 = 53
   SBIC PORTA, 7
   MOVW R19:R18, R1:R0
   LDI R19, 0x54              ; R19 = 54
 
   ; SBIS
   LDI R20, 0x92              ; R20 = 92
   OUT PORTA, R20
   SBIS PORTA, 6
   LDI R19, 0x60              ; R19 = 60
   SBIS PORTA, 7
   LDI R19, 0x28
   LDI R19, 0x61              ; R19 = 61
   SBIS PORTA, 7
   LD R18, Z
   SBIS PORTA, 7
   STD Z+0, R20
   LDI R19, 0x62              ; R19 = 62
   SBIS PORTA, 7
   JMP jmp13
   LDI R19, 0x63              ; R19 = 63
   SBIS PORTA, 7
   MOVW R19:R18, R1:R0
   LDI R19, 0x64              ; R19 = 64
 
   ; Branches -------------------------
 
   LDI R31, 0x01
   LDI R30, 0x4e
   LDI R16, 0x45
   MOV R3, R16
   LDI R16, 0x03
   MOV R4, R16
 
   ; BRBC
   LDI R19, 0x70
   OUT SREG, R4
   STD Z+5, R3
   LDD R19, Z+5
   BRBC 2, jmp14
   LDI R19, 0x71
jmp15:
   LDI R19, 0x72
   BRBC 1, jmp14
   LDI R19, 0x73
   rjmp jmp16
jmp14:
   INC R3
   OUT SREG, R4
   STD Z+5, R3
   LDD R19, Z+5
   LDI R19, 0x74
   BRBC 3,  jmp15
   LDI R19, 0x75
jmp16:
   LDI R19, 0x76              ; R19 = 70, 45, 46, 74, 72, 73, 76
 
   ; BRBS
   LDI R19, 0x80
   OUT SREG, R4
   STD Z+5, R3
   LDD R19, Z+5
   BRBS 1, jmp17
   LDI R19, 0x81
jmp18:
   LDI R19, 0x82
   BRBS 4, jmp14
   LDI R19, 0x83
   rjmp jmp19
jmp17:
   INC R3
   OUT SREG, R4
   STD Z+5, R3
   LDD R19, Z+5
   LDI R19, 0x84
   BRBS 1,  jmp18
   LDI R19, 0x85
jmp19:
   LDI R19, 0x86              ; R19 = 80, 46, 47, 84, 82, 83, 86
 
 
   ; Calls and returns ----------------
   RCALL jmp20
   LDI R19, 0xa0
   CALL jmp21
   JMP jmp26
 
jmp20:
   LDI R19, 0xa1
   STD Z+5, R3
   RET
   STD Z+5, R3
 
jmp21:
   LDI R19, 0xa3
   RET
   JMP jmp21
 
jmp22:
   LDI R19, 0xa4
   ADIW R25:R24, 0x35
   RET
   BRBS 4, jmp14
 
jmp23:
   LDI R19, 0xa5
   CLR R0
   OUT SREG, R0
   BRBS 4, jmp23
   RET
   BRBS 4, jmp23
 
jmp24:
   LDI R19, 0xa6
   JMP jmp24bis
jmp24bis:
   RET
   JMP jmp24
 
jmp25:
   LDI R19, 0xa7
   CLR R17
   ELPM R17, Z+
   RET
   CPSE R20, R21
 
jmp26:
   LDI R19, 0xa8           ; R19 = a1, a0, a3, a8
 
   NOP
   NOP
   NOP
   NOP
   NOP
   NOP
   NOP
   NOP
   NOP
   NOP
forever:
   RJMP forever

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Subversion Repositories pavr

[/] [pavr/] [trunk/] [test/] [gentest/] [gentest.asm] - Blame information for rev 6

Line No.	Rev	Author	Line
1	4	doru	`; Project`
2			`; pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's`
3			`; AVR core, but about 3x faster in terms of both clock frequency and MIPS.`
4			`; The increase in speed comes from a relatively deep pipeline. The original`
5			`; AVR core has only two pipeline stages (fetch and execute), while pAVR has`
6			`; 6 pipeline stages:`
7			`; 1. PM (read Program Memory)`
8			`; 2. INSTR (load Instruction)`
9			`; 3. RFRD (decode Instruction and read Register File)`
10			`; 4. OPS (load Operands)`
11			`; 5. ALU (execute ALU opcode or access Unified Memory)`
12			`; 6. RFWR (write Register File)`
13			`; Version`
14			`; 0.32`
15			`; Date`
16			`; 2002 August 07`
17			`; Author`
18			`; Doru Cuturela, doruu@yahoo.com`
19			`; License`
20			`; This program is free software; you can redistribute it and/or modify`
21			`; it under the terms of the GNU General Public License as published by`
22			`; the Free Software Foundation; either version 2 of the License, or`
23			`; (at your option) any later version.`
24			`; This program is distributed in the hope that it will be useful,`
25			`; but WITHOUT ANY WARRANTY; without even the implied warranty of`
26			`; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
27			`; GNU General Public License for more details.`
28			`; You should have received a copy of the GNU General Public License`
29			`; along with this program; if not, write to the Free Software`
30			`; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
31
32
33			`; About this file...`
34			`; This tests all instructions, one by one.`
35
36
37
38			`.include "m103def.inc"`
39
40			`; Initialize some registers.`
41			`rjmp start`
42
43			`.org 400`
44			`start:`
45			`LDI R17, 0x90`
46			`MOV R0, R17`
47			`MOV R1, R17`
48			`MOV R2, R17`
49			`MOV R4, R17`
50			`MOV R7, R17`
51			`MOV R12, R17`
52			`MOV R14, R17`
53			`MOV R16, R17`
54			`MOV R18, R17`
55			`MOV R20, R17`
56			`MOV R22, R17`
57			`MOV R23, R17`
58			`MOV R24, R17`
59			`MOV R25, R17`
60			`MOV R26, R17`
61			`MOV R29, R17`
62			`MOV R31, R17`
63			`LDI R28, 0xd5`
64			`MOV R3, R28`
65			`MOV R5, R28`
66			`MOV R6, R28`
67			`MOV R8, R28`
68			`MOV R9, R28`
69			`MOV R10, R28`
70			`MOV R11, R28`
71			`MOV R13, R28`
72			`MOV R15, R28`
73			`MOV R19, R28`
74			`MOV R21, R28`
75			`MOV R24, R28`
76			`MOV R27, R28`
77			`MOV R30, R28`
78
79			`; These replace original nops, for maintaining absolute addresses used for jumping during the test.`
80			`MOV R0, R0`
81			`MOV R0, R0`
82			`MOV R0, R0`
83			`MOV R0, R0`
84			`MOV R0, R0`
85			`MOV R0, R0`
86
87			`ADD R28, R17 ; r28 = d5+90=65 (modulo 256) SREG=19`
88			`ADC R25, R28 ; r25 = 90+65+1=f6 SREG=14`
89			`ADIW R25:R24, 0x35 ; r25:r24 = f6:d5+65=f7:0a SREG=14`
90
91			`SUB R23, R24 ; r23 = 90-a=86 SREG=34`
92			`SUBI R23, 0xf6 ; r23 = 86-f6=90 SREG=15`
93			`SBC R26, R23 ; r26 = 90-90-1=ff SREG=35`
94			`SBIW R27:R26, 0x2d ; r27:r26 = d5:ff-2d=d5:d2 SREG=34`
95
96			`; Intermediate result: r26=0xd2`
97
98			`INC r26 ; r26=d2+1=d3 SREG=34`
99			`INC r26 ; r26=d3+1=d4 SREG=34`
100			`INC r26 ; r26=d4+1=d5 SREG=34`
101			`INC r26 ; r26=d5+1=d6 SREG=34`
102			`INC r26 ; r26=d6+1=d7 SREG=34`
103			`DEC r26 ; r25=d7-1=d6 SREG=34`
104
105			`AND r28, r26 ; r28=65&d6=44 SREG=20`
106			`ANDI r28, 0x43 ; r28=44&43=40 SREG=20`
107			`OR r31, r28 ; r31=90\|40=d0 SREG=34`
108			`ORI r31, 0x63 ; r31=d0\|63=f3 SREG=34`
109			`EOR r10, r31 ; r10=d5^f3=26 SREG=20`
110
111			`; Intermediate result: r10=0x26`
112
113			`COM r10 ; r10=com(26)=d9 SREG=35`
114			`NEG r10 ; r10=neg(d9)=27, set C SREG=01`
115			`SEZ ; SREG=03`
116			`CP r10, r11 ; (r10`
117			`MOV r12, r10 ; r12=27`
118			`DEC r12 ; r12=26`
119			`SEZ ; SREG=03`
120			`CPC r10, r12 ; (r10`
121			`CPI r17, 0xab ; (r17`
122			`SWAP r12 ; r12=swap(r12)=62`
123
124			`LSR r12 ; r12=lsr(r12)=31 SREG=20`
125			`ROR r12 ; r12=ror(r12)=18 SREG=39`
126			`ASR r12 ; r12=asr(r12)=c SREG=20`
127
128			`; Intermediate result: r21=0x0c`
129
130			`; Multiplications return zero for now. Test timing only.`
131			`MUL r10, r10`
132			`MULS r17, r17`
133			`MULSU r17, r17`
134			`FMUL r17, r17`
135			`FMULS r17, r17`
136			`FMULSU r17, r17`
137
138			`MOV r0, r12 ; r0=r12=c`
139			`MOV r1, r11 ; r1=r11=d5`
140			`SUB r1, r0 ; r1=r1-r0=c-d5=c9 SREG=34`
141
142			`; Intermediate result: r1=0xc9`
143
144			`OUT SREG, r1 ; SREG=r1=c9`
145			`BCLR 7 ; SREG(7)=0; SREG=49`
146			`BCLR 3 ; SREG(3)=0; SREG=41`
147			`BSET 1 ; SREG(1)=1; SREG=43`
148			`BSET 4 ; SREG(4)=1; SREG=53`
149
150			`; Configure port A as output.`
151			`LDI R27, 0xFF`
152			`OUT DDRA, R27`
153			`IN R29, SREG ; R29=SREG=53`
154			`; Send R29 to port A.`
155			`OUT PORTA, R29 ; PORTA=R29=53`
156			`CBI PORTA, 0 ; PORTA(0)=0; PORTA=52`
157			`CBI PORTA, 6 ; PORTA(6)=0; PORTA=12`
158			`SBI PORTA, 3 ; PORTA(2)=0; PORTA=1a`
159			`SBI PORTA, 5 ; PORTA(7)=0; PORTA=3a`
160			`IN R30, PORTA ; R30=PORTA=3a`
161			`LDI R31, 0x00 ; R31=0`
162			`; Test if both IN and LDI correctly update the BPU (IN stalls LDI to steal BPU access).`
163			`SBIW R31:R30, 0x3e ; R31:R30=R31:R30-3e=00:3a-3e=ff:fc SREG=55`
164			`BST R30, 1 ; T=R30(1)=0`
165			`BLD R30, 6 ; R30(6)=T=0; R30=bc`
166			`MOV R31, R1 ; R31=c9`
167			`; Test if both BLD and MOV correctly update the BPU (BLD stalls MOV to steal BPU access).`
168			`ADIW R31:R30, 0x2a ; R31:R30=R31:R30+2a=c9:bc+2a=c9:e6 SREG=14`
169			`; Test if both bytes of the result update the BPU.`
170			`ADIW R31:R30, 0x18 ; R31:R30=R31:R30+18=c9:e6+18=c9:fe SREG=14`
171			`MOV R10, R30`
172
173			`; Intermediate result: r10=fe`
174
175			`; Set up the stack`
176			`LDI R25, 0x01`
177			`OUT SPH, R25`
178			`LDI R26, 0x1c`
179			`OUT SPL, R26`
180
181			`MOVW R23:R22, R31:R30 ; R23:R22=R31:R30=c9:fe`
182			`PUSH R22 ; stack=R22=fe`
183			`POP R21`
184			`ADD R21, R12`
185			`ADD R21, R12`
186			`ADD R21, R12`
187			`ADD R21, R12 ; R21=2e`
188
189			`STS 0x0130, R21`
190			`LDS R22, 0x0130 ; R22=2e`
191			`LDI R31, 0x01 ; R31=1`
192			`LDI R30, 0x23 ; R30=23`
193			`INC R22 ; R22=R22+1=2e+1=2f`
194			`ST Z, R22 ; (Z)=(1:23)=R22=2f`
195			`LD R21, Z ; R21=(Z)=(1:23)=2f`
196
197			`LDI R17, 0xf9`
198			`MOV R0, R17`
199			`INC R0`
200
201			`; Load pointer registers for next tests.`
202			`LDI R27, 0x01 ; X=0140`
203			`LDI R26, 0x40 ;`
204			`LDI R29, 0x01 ; Y=0150`
205			`LDI R28, 0x50 ;`
206			`LDI R31, 0x01 ; Z=0160`
207			`LDI R30, 0x60 ;`
208
209			`; Load-stores through X pointer`
210			`ST X+, R0`
211			`ST X, R0`
212			`ADIW R27:R26, 0x02`
213			`ST -X, R0`
214			`LD R20, X+`
215			`SBIW R27:R26, 0x02`
216			`LD R21, X`
217			`LD R22, -X`
218
219			`INC R0`
220
221			`; Load-stores through Y pointer`
222			`ST Y+, R0`
223			`ST Y, R0`
224			`ADIW R29:R28, 0x02`
225			`ST -Y, R0`
226			`LD R20, Y+`
227			`SBIW R29:R28, 0x02`
228			`LD R21, Y`
229			`LD R22, -Y`
230
231			`STD Y+0x3b, R0`
232			`LDD R23, Y+0x3b`
233
234			`INC R0`
235
236			`; Load-stores through Z pointer`
237			`ST Z+, R0`
238			`ST Z, R0`
239			`ADIW R31:R30, 0x02`
240			`ST -Z, R0`
241			`LD R20, Z+`
242			`SBIW R31:R30, 0x02`
243			`LD R21, Z`
244			`LD R22, -Z`
245
246			`STD Z+0x3c, R0`
247			`LDD R23, Z+0x3c`
248
249			`; Store into Register File.`
250			`LDI R20, 0xaa`
251			`LDI R21, 0xbb`
252			`LDI R27, 00`
253			`LDI R26, 21`
254			`ST X+, R20`
255			`; Check if R21=0xaa.`
256
257			`; Store into IO File.`
258			`LDI R20, 0xcc`
259			`LDI R31, 0x00`
260			`LDI R30, 0x38`
261			`STD Z+3, R20 ; (3b)=R20=cc (note that PORTA has address 0x3b in the Unified Memory, that is 0x1b in IOF)`
262			`; Check if PORTA=0xcc`
263
264			`; Test LPM family instructions.`
265			`LDI R31, 0x03`
266			`LDI R30, 0x74`
267			`LPM`
268			`LPM R17, Z+`
269			`LPM R18, Z+`
270			`LPM R19, Z`
271
272			`LDI R31, 0x03`
273			`LDI R30, 0x45`
274			`LDI R17, 0x00`
275			`OUT RAMPZ, R17`
276			`ELPM`
277			`ELPM R17, Z+`
278			`ELPM R18, Z+`
279			`ELPM R19, Z`
280
281			`; Jumps ----------------------------`
282
283			`; RJMP`
284			`RJMP jmp1`
285			`LDI R19, 0xaa`
286			`jmp2:`
287			`LDI R19, 0xbb`
288			`LDI R19, 0xcc`
289			`RJMP jmp3`
290			`jmp1:`
291			`LDI R19, 0xdd`
292			`LDI R19, 0xee`
293			`RJMP jmp2`
294			`jmp3:`
295			`LDI R19, 0xff ; R19 = dd, ee, bb, cc, ff`
296
297			`; IJMP`
298			`LDI R19, 0x11`
299			`LDI R31, 0x02`
300			`LDI R30, 0x58`
301			`IJMP`
302			`jmp5: ; 0254`
303			`LDI R19, 0x22`
304			`LDI R31, 0x02`
305			`LDI R30, 0x5c`
306			`IJMP`
307			`jmp4: ; 0258`
308			`LDI R19, 0x33`
309			`LDI R31, 0x02`
310			`LDI R30, 0x54`
311			`IJMP`
312			`jmp6: ; 025c`
313			`LDI R19, 0x44`
314			`LDI R31, 0x02`
315			`LDI R30, 0x61`
316			`IJMP`
317			`LDI R19, 0x55`
318			`jmp7: ; 0261`
319			`LDI R19, 0x66 ; R19 = 11, 33, 22, 44, 66`
320
321			`; EIJMP`
322			`LDI R19, 0x77`
323			`LDI R17, 0x00`
324			`OUT RAMPZ, R17`
325			`LDI R31, 0x02`
326			`LDI R30, 0x6a`
327			`EIJMP`
328			`jmp9: ; 0268`
329			`LDI R19, 0x88`
330			`RJMP jmp10`
331			`jmp8: ; 026a`
332			`LDI R19, 0x99`
333			`LDI R31, 0x02`
334			`LDI R30, 0x68`
335			`EIJMP`
336			`jmp10: ; 026e`
337			`LDI R19, 0xaa ; R19 = 77, 99, 88, aa`
338
339			`; JMP`
340			`LDI R19, 0x10`
341			`JMP jmp11`
342			`LDI R19, 0x11`
343			`jmp12:`
344			`LDI R19, 0x12`
345			`; Stress the JMP a little bit.`
346			`INC R11`
347			`INC R10`
348			`LDI R17, 0x09`
349			`LDI R20, 0xa2`
350			`LDI R29, 0x00`
351			`LDI R28, 20`
352			`ST Y, R17 ; R20=9`
353			`LD R21, Y ; R21=9`
354			`JMP jmp13`
355			`LDI R19, 0x13`
356			`LDI R19, 0x14`
357			`jmp11:`
358			`LDI R19, 0x15`
359			`; Stress the JMP a little bit.`
360			`INC R11`
361			`INC R10`
362			`MOVW R11:R10, R25:R24`
363			`JMP jmp12`
364			`jmp13:`
365			`LDI R19, 0x16 ; R19 = 10, 15, 12, 16`
366
367			`; Skips ----------------------------`
368
369			`; CPSE`
370			`LDI R20, 0x10`
371			`LDI R21, 0x10`
372			`LDI R22, 0x11`
373			`LDI R19, 0x21 ; R19 = 21`
374			`CPSE R20, R21`
375			`LDI R19, 0x22`
376			`LDI R19, 0x23 ; R19 = 23`
377			`CPSE R20, R22`
378			`LDI R19, 0x24 ; R19 = 24`
379			`; Stress CPSE a little bit.`
380			`LDI R31, 0x00`
381			`LDI R30, 19`
382			`CPSE R20, R21`
383			`ST Z+, R0`
384			`ST Z+, R24 ; R19 = a`
385			`DEC R19 ; R19 = 9`
386			`CPSE R20, R21`
387			`LD R6, -Z`
388			`LD R7, -Z ; R7 = 9`
389			`CPSE R20, R21`
390			`MOVW R19:R18, R5:R4`
391			`LDI R19, 0x25 ; R19 = 25`
392			`CPSE R20, R21`
393			`JMP jmp13`
394			`LDI R19, 0x26 ; R19 = 26`
395			`CPSE R20, R21`
396			`STD Z+0, R23`
397			`STD Z+0, R25 ; R19 = 1`
398
399			`; SBRC`
400			`LDI R20, 0x41 ; R20 = 41`
401			`SBRC R20, 6`
402			`LDI R19, 0x30 ; R19 = 30`
403			`SBRC R20, 7`
404			`LDI R19, 0x28`
405			`LDI R19, 0x31 ; R19 = 31`
406			`SBRC R20, 7`
407			`LD R18, Z`
408			`SBRC R20, 7`
409			`STD Z+0, R20`
410			`LDI R19, 0x32 ; R19 = 32`
411			`SBRC R20, 7`
412			`JMP jmp13`
413			`LDI R19, 0x33 ; R19 = 33`
414			`SBRC R20, 7`
415			`MOVW R19:R18, R1:R0`
416			`LDI R19, 0x3d ; R19 = 3d`
417
418			`; SBRS`
419			`LDI R20, 0x92 ; R20 = 92`
420			`SBRS R20, 6`
421			`LDI R19, 0x40 ; R19 = 40`
422			`SBRS R20, 7`
423			`LDI R19, 0x28`
424			`LDI R19, 0x41 ; R19 = 41`
425			`SBRS R20, 7`
426			`LD R18, Z`
427			`SBRS R20, 7`
428			`STD Z+0, R20`
429			`LDI R19, 0x42 ; R19 = 42`
430			`SBRS R20, 7`
431			`JMP jmp13`
432			`LDI R19, 0x43 ; R19 = 43`
433			`SBRS R20, 7`
434			`MOVW R19:R18, R1:R0`
435			`LDI R19, 0x44 ; R19 = 44`
436
437			`; SBIC`
438			`LDI R20, 0x41 ; R20 = 41`
439			`OUT PORTA, R20`
440			`SBIC PORTA, 6`
441			`LDI R19, 0x50 ; R19 = 50`
442			`SBIC PORTA, 7`
443			`LDI R19, 0x28`
444			`LDI R19, 0x51 ; R19 = 51`
445			`SBIC PORTA, 7`
446			`LD R18, Z`
447			`SBIC PORTA, 7`
448			`STD Z+0, R20`
449			`LDI R19, 0x52 ; R19 = 52`
450			`SBIC PORTA, 7`
451			`JMP jmp13`
452			`LDI R19, 0x53 ; R19 = 53`
453			`SBIC PORTA, 7`
454			`MOVW R19:R18, R1:R0`
455			`LDI R19, 0x54 ; R19 = 54`
456
457			`; SBIS`
458			`LDI R20, 0x92 ; R20 = 92`
459			`OUT PORTA, R20`
460			`SBIS PORTA, 6`
461			`LDI R19, 0x60 ; R19 = 60`
462			`SBIS PORTA, 7`
463			`LDI R19, 0x28`
464			`LDI R19, 0x61 ; R19 = 61`
465			`SBIS PORTA, 7`
466			`LD R18, Z`
467			`SBIS PORTA, 7`
468			`STD Z+0, R20`
469			`LDI R19, 0x62 ; R19 = 62`
470			`SBIS PORTA, 7`
471			`JMP jmp13`
472			`LDI R19, 0x63 ; R19 = 63`
473			`SBIS PORTA, 7`
474			`MOVW R19:R18, R1:R0`
475			`LDI R19, 0x64 ; R19 = 64`
476
477			`; Branches -------------------------`
478
479			`LDI R31, 0x01`
480			`LDI R30, 0x4e`
481			`LDI R16, 0x45`
482			`MOV R3, R16`
483			`LDI R16, 0x03`
484			`MOV R4, R16`
485
486			`; BRBC`
487			`LDI R19, 0x70`
488			`OUT SREG, R4`
489			`STD Z+5, R3`
490			`LDD R19, Z+5`
491			`BRBC 2, jmp14`
492			`LDI R19, 0x71`
493			`jmp15:`
494			`LDI R19, 0x72`
495			`BRBC 1, jmp14`
496			`LDI R19, 0x73`
497			`rjmp jmp16`
498			`jmp14:`
499			`INC R3`
500			`OUT SREG, R4`
501			`STD Z+5, R3`
502			`LDD R19, Z+5`
503			`LDI R19, 0x74`
504			`BRBC 3, jmp15`
505			`LDI R19, 0x75`
506			`jmp16:`
507			`LDI R19, 0x76 ; R19 = 70, 45, 46, 74, 72, 73, 76`
508
509			`; BRBS`
510			`LDI R19, 0x80`
511			`OUT SREG, R4`
512			`STD Z+5, R3`
513			`LDD R19, Z+5`
514			`BRBS 1, jmp17`
515			`LDI R19, 0x81`
516			`jmp18:`
517			`LDI R19, 0x82`
518			`BRBS 4, jmp14`
519			`LDI R19, 0x83`
520			`rjmp jmp19`
521			`jmp17:`
522			`INC R3`
523			`OUT SREG, R4`
524			`STD Z+5, R3`
525			`LDD R19, Z+5`
526			`LDI R19, 0x84`
527			`BRBS 1, jmp18`
528			`LDI R19, 0x85`
529			`jmp19:`
530			`LDI R19, 0x86 ; R19 = 80, 46, 47, 84, 82, 83, 86`
531
532
533			`; Calls and returns ----------------`
534			`RCALL jmp20`
535			`LDI R19, 0xa0`
536			`CALL jmp21`
537			`JMP jmp26`
538
539			`jmp20:`
540			`LDI R19, 0xa1`
541			`STD Z+5, R3`
542			`RET`
543			`STD Z+5, R3`
544
545			`jmp21:`
546			`LDI R19, 0xa3`
547			`RET`
548			`JMP jmp21`
549
550			`jmp22:`
551			`LDI R19, 0xa4`
552			`ADIW R25:R24, 0x35`
553			`RET`
554			`BRBS 4, jmp14`
555
556			`jmp23:`
557			`LDI R19, 0xa5`
558			`CLR R0`
559			`OUT SREG, R0`
560			`BRBS 4, jmp23`
561			`RET`
562			`BRBS 4, jmp23`
563
564			`jmp24:`
565			`LDI R19, 0xa6`
566			`JMP jmp24bis`
567			`jmp24bis:`
568			`RET`
569			`JMP jmp24`
570
571			`jmp25:`
572			`LDI R19, 0xa7`
573			`CLR R17`
574			`ELPM R17, Z+`
575			`RET`
576			`CPSE R20, R21`
577
578			`jmp26:`
579			`LDI R19, 0xa8 ; R19 = a1, a0, a3, a8`
580
581			`NOP`
582			`NOP`
583			`NOP`
584			`NOP`
585			`NOP`
586			`NOP`
587			`NOP`
588			`NOP`
589			`NOP`
590			`NOP`
591			`forever:`
592			`RJMP forever`